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path: root/cpu/ppc4xx/44x_spd_ddr2.c
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Diffstat (limited to 'cpu/ppc4xx/44x_spd_ddr2.c')
-rw-r--r--cpu/ppc4xx/44x_spd_ddr2.c80
1 files changed, 40 insertions, 40 deletions
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index f1d76840f2..30c2e44b46 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -402,8 +402,8 @@ phys_size_t initdram(int board_type)
*/
/* switch to correct I2C bus */
- I2C_SET_BUS(CFG_SPD_BUS_NUM);
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
/*------------------------------------------------------------------
* Clear out the serial presence detect buffers.
@@ -2976,62 +2976,62 @@ phys_size_t initdram(int board_type)
/* Set Memory Bank Configuration Registers */
- mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
- mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
- mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
- mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
+ mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
+ mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
+ mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
+ mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
/* Set Memory Clock Timing Register */
- mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
+ mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
/* Set Refresh Time Register */
- mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
+ mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
/* Set SDRAM Timing Registers */
- mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
- mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
- mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
+ mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
+ mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
+ mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
/* Set Mode and Extended Mode Registers */
- mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
- mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
+ mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
+ mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
/* Set Memory Controller Options 1 Register */
- mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
+ mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
/* Set Manual Initialization Control Registers */
- mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
- mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
- mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
- mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
- mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
- mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
- mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
- mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
- mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
- mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
- mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
- mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
- mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
- mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
- mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
- mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
+ mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
+ mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
+ mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
+ mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
+ mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
+ mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
+ mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
+ mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
+ mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
+ mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
+ mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
+ mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
+ mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
+ mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
+ mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
+ mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
/* Set On-Die Termination Registers */
- mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
- mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
- mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
+ mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
+ mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
+ mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
/* Set Write Timing Register */
- mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
+ mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
/*
* Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
@@ -3052,12 +3052,12 @@ phys_size_t initdram(int board_type)
/* Set Delay Control Registers */
- mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
+ mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
- mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
- mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
- mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
+ mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
+ mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
+ mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
#endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
/*
@@ -3077,7 +3077,7 @@ phys_size_t initdram(int board_type)
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
#if defined(CONFIG_DDR_ECC)
- ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
+ ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
#endif /* defined(CONFIG_DDR_ECC) */
ppc4xx_ibm_ddr2_register_dump();
@@ -3093,7 +3093,7 @@ phys_size_t initdram(int board_type)
#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
- return (CFG_MBYTES_SDRAM << 20);
+ return (CONFIG_SYS_MBYTES_SDRAM << 20);
}
#endif /* CONFIG_SPD_EEPROM */