diff options
Diffstat (limited to 'cpu')
32 files changed, 1255 insertions, 193 deletions
diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c index 706c880db1e..ca45e17edbb 100644 --- a/cpu/74xx_7xx/cpu.c +++ b/cpu/74xx_7xx/cpu.c @@ -215,7 +215,8 @@ soft_restart(unsigned long addr) #if !defined(CONFIG_PCIPPC2) && \ !defined(CONFIG_BAB7xx) && \ - !defined(CONFIG_ELPPC) + !defined(CONFIG_ELPPC) && \ + !defined(CONFIG_PPMC7XX) /* no generic way to do board reset. simply call soft_reset. */ void do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S index ff1cce55d8c..1fc0fe6bc1f 100644 --- a/cpu/74xx_7xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -756,7 +756,8 @@ in_ram: #if defined(CONFIG_AMIGAONEG3SE) || \ defined(CONFIG_DB64360) || \ defined(CONFIG_DB64460) || \ - defined(CONFIG_CPCI750) + defined(CONFIG_CPCI750) || \ + defined(CONFIG_PPMC7XX) mr r4, r9 /* Use RAM copy of the global data */ #endif bl after_reloc diff --git a/cpu/arm920t/s3c24x0/i2c.c b/cpu/arm920t/s3c24x0/i2c.c index ef56cd1c31d..374b6831371 100644 --- a/cpu/arm920t/s3c24x0/i2c.c +++ b/cpu/arm920t/s3c24x0/i2c.c @@ -153,7 +153,7 @@ void i2c_init (int speed, int slaveadd) #endif #ifdef CONFIG_S3C2400 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ - gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00000c00; + gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00001000; #endif /* toggle I2CSCL until bus idle */ diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c index 3ec9b5400e3..1b364123dc5 100644 --- a/cpu/arm920t/s3c24x0/interrupts.c +++ b/cpu/arm920t/s3c24x0/interrupts.c @@ -176,7 +176,9 @@ ulong get_tbclk (void) #if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB) tbclk = timer_load_val * 100; -#elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9) +#elif defined(CONFIG_SBC2410X) || \ + defined(CONFIG_SMDK2410) || \ + defined(CONFIG_VCMA9) tbclk = CFG_HZ; #else # error "tbclk not configured" diff --git a/cpu/ixp/npe/include/IxEthDB.h b/cpu/ixp/npe/include/IxEthDB.h index 43ee802d642..1189c9a1401 100644 --- a/cpu/ixp/npe/include/IxEthDB.h +++ b/cpu/ixp/npe/include/IxEthDB.h @@ -799,10 +799,10 @@ IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBR * @verbatim IxEthDBPortMap portMap; - /* clear all ports from port map */ + // clear all ports from port map memset(portMap, 0, sizeof (portMap)); - /* include portID in port map */ + // include portID in port map portMap[portID / 8] = 1 << (portID % 8); @endverbatim * diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c index e6e5d9bee96..aa6b2bd670c 100644 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@ -2,6 +2,10 @@ * (C) Copyright 2003 * Josef Baumgartner <josef.baumgartner@telex.de> * + * MCF5282 additionals + * (C) Copyright 2005 + * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> + * * See file CREDITS for list of people who contributed to this * project. * @@ -36,7 +40,8 @@ #endif #ifdef CONFIG_M5282 - +#include <asm/m5282.h> +#include <asm/immap_5282.h> #endif #ifdef CONFIG_M5249 @@ -116,7 +121,6 @@ int checkcpu(void) { return 0; }; - #if defined(CONFIG_WATCHDOG) /* Called by macro WATCHDOG_RESET */ void watchdog_reset (void) @@ -158,11 +162,25 @@ int watchdog_init (void) #ifdef CONFIG_M5282 int checkcpu (void) { - puts ("CPU: Freescale Coldfire MCF5282\n"); + unsigned char resetsource = MCFRESET_RSR; + + printf ("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", + MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); + printf ("Reset:%s%s%s%s%s%s%s\n", + (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", + (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", + (resetsource & MCFRESET_RSR_EXT) ? " External" : "", + (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", + (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", + (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", + (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "" + ); return 0; } -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { +int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + MCFRESET_RCR = MCFRESET_RCR_SOFTRST; return 0; }; #endif diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 451e3f3f10b..1748ea9d9b7 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -2,6 +2,10 @@ * (C) Copyright 2003 * Josef Baumgartner <josef.baumgartner@telex.de> * + * MCF5282 additionals + * (C) Copyright 2005 + * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> + * * See file CREDITS for list of people who contributed to this * project. * @@ -172,7 +176,180 @@ int cpu_init_r (void) */ void cpu_init_f (void) { +#ifndef CONFIG_WATCHDOG + /* disable watchdog if we aren't using it */ + MCFWTM_WCR = 0; +#endif + +#ifndef CONFIG_MONITOR_IS_IN_RAM + /* Set speed /PLL */ + MCFCLOCK_SYNCR = MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD); + + /* Set up the GPIO ports */ +#ifdef CFG_PEPAR + MCFGPIO_PEPAR = CFG_PEPAR; +#endif +#ifdef CFG_PFPAR + MCFGPIO_PFPAR = CFG_PFPAR; +#endif +#ifdef CFG_PJPAR + MCFGPIO_PJPAR = CFG_PJPAR; +#endif +#ifdef CFG_PSDPAR + MCFGPIO_PSDPAR = CFG_PSDPAR; +#endif +#ifdef CFG_PASPAR + MCFGPIO_PASPAR = CFG_PASPAR; +#endif +#ifdef CFG_PEHLPAR + MCFGPIO_PEHLPAR = CFG_PEHLPAR; +#endif +#ifdef CFG_PQSPAR + MCFGPIO_PQSPAR = CFG_PQSPAR; +#endif +#ifdef CFG_PTCPAR + MCFGPIO_PTCPAR = CFG_PTCPAR; +#endif +#ifdef CFG_PTDPAR + MCFGPIO_PTDPAR = CFG_PTDPAR; +#endif +#ifdef CFG_PUAPAR + MCFGPIO_PUAPAR = CFG_PUAPAR; +#endif + +#ifdef CFG_DDRUA + MCFGPIO_DDRUA = CFG_DDRUA; +#endif + + /* This is probably a bad place to setup chip selects, but everyone + else is doing it! */ + +#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \ + defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \ + defined(CFG_CS0_WS) + + MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF; + + #if (CFG_CS0_WIDTH == 8) + #define CFG_CS0_PS MCFCSM_CSCR_PS_8 + #elif (CFG_CS0_WIDTH == 16) + #define CFG_CS0_PS MCFCSM_CSCR_PS_16 + #elif (CFG_CS0_WIDTH == 32) + #define CFG_CS0_PS MCFCSM_CSCR_PS_32 + #else + #error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0" + #endif + MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS) + |CFG_CS0_PS + |MCFCSM_CSCR_AA; + + #if (CFG_CS0_RO != 0) + MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1) + |MCFCSM_CSMR_WP|MCFCSM_CSMR_V; + #else + MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)|MCFCSM_CSMR_V; + #endif +#else + #waring "Chip Select 0 are not initialized/used" +#endif + +#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \ + defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \ + defined(CFG_CS1_WS) + + MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF; + + #if (CFG_CS1_WIDTH == 8) + #define CFG_CS1_PS MCFCSM_CSCR_PS_8 + #elif (CFG_CS1_WIDTH == 16) + #define CFG_CS1_PS MCFCSM_CSCR_PS_16 + #elif (CFG_CS1_WIDTH == 32) + #define CFG_CS1_PS MCFCSM_CSCR_PS_32 + #else + #error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1" + #endif + MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS) + |CFG_CS1_PS + |MCFCSM_CSCR_AA; + + #if (CFG_CS1_RO != 0) + MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1) + |MCFCSM_CSMR_WP + |MCFCSM_CSMR_V; + #else + MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1) + |MCFCSM_CSMR_V; + #endif +#else + #warning "Chip Select 1 are not initialized/used" +#endif + +#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \ + defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \ + defined(CFG_CS2_WS) + + MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF; + + #if (CFG_CS2_WIDTH == 8) + #define CFG_CS2_PS MCFCSM_CSCR_PS_8 + #elif (CFG_CS2_WIDTH == 16) + #define CFG_CS2_PS MCFCSM_CSCR_PS_16 + #elif (CFG_CS2_WIDTH == 32) + #define CFG_CS2_PS MCFCSM_CSCR_PS_32 + #else + #error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2" + #endif + MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS) + |CFG_CS2_PS + |MCFCSM_CSCR_AA; + + #if (CFG_CS2_RO != 0) + MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1) + |MCFCSM_CSMR_WP + |MCFCSM_CSMR_V; + #else + MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1) + |MCFCSM_CSMR_V; + #endif +#else + #warning "Chip Select 2 are not initialized/used" +#endif + +#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \ + defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \ + defined(CFG_CS3_WS) + + MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF; + + #if (CFG_CS3_WIDTH == 8) + #define CFG_CS3_PS MCFCSM_CSCR_PS_8 + #elif (CFG_CS3_WIDTH == 16) + #define CFG_CS3_PS MCFCSM_CSCR_PS_16 + #elif (CFG_CS3_WIDTH == 32) + #define CFG_CS3_PS MCFCSM_CSCR_PS_32 + #else + #error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1" + #endif + MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS) + |CFG_CS3_PS + |MCFCSM_CSCR_AA; + + #if (CFG_CS3_RO != 0) + MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1) + |MCFCSM_CSMR_WP + |MCFCSM_CSMR_V; + #else + MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1) + |MCFCSM_CSMR_V; + #endif +#else + #warning "Chip Select 3 are not initialized/used" +#endif + +#endif /* CONFIG_MONITOR_IS_IN_RAM */ + /* defer enabling cache until boot (see do_go) */ + /* icache_enable(); */ } /* diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c index f207dd6acb5..6db62147220 100644 --- a/cpu/mcf52x2/fec.c +++ b/cpu/mcf52x2/fec.c @@ -205,7 +205,9 @@ int eth_rx (void) int eth_init (bd_t * bd) { - +#ifndef CFG_ENET_BD_BASE + DECLARE_GLOBAL_DATA_PTR; +#endif int i; volatile fec_t *fecp = (fec_t *) (FEC_ADDR); @@ -258,6 +260,10 @@ int eth_init (bd_t * bd) #else /* Clear multicast address hash table */ +#ifdef CONFIG_M5282 + fecp->fec_ihash_table_high = 0; + fecp->fec_ihash_table_low = 0; +#else fecp->fec_hash_table_high = 0; fecp->fec_hash_table_low = 0; #endif @@ -273,7 +279,16 @@ int eth_init (bd_t * bd) txIdx = 0; if (!rtx) { +#ifdef CFG_ENET_BD_BASE rtx = (RTXBD *) CFG_ENET_BD_BASE; +#else + rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off - + (((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t) + +0xFF) + & ~0xFF) + ); + debug("set ENET_DB_BASE to %lX\n",(long) rtx); +#endif } /* @@ -307,18 +322,18 @@ int eth_init (bd_t * bd) /* Enable MII mode */ -#if 0 /* Full duplex mode */ + +#if 0 /* Full duplex mode */ fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; -#else /* Half duplex mode */ - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; -#ifdef CONFIG_M5271 - fecp->fec_r_cntrl |= (PKT_MAXBUF_SIZE << 16); /* set max frame length */ -#endif +#else /* Half duplex mode */ + fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */ + fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; fecp->fec_x_cntrl = 0; #endif /* Set MII speed */ - fecp->fec_mii_speed = 0x0e; + fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10; + fecp->fec_mii_speed *= 2; /* Configure port B for MII. */ @@ -422,7 +437,7 @@ static void mii_discover_phy (void) */ udelay (10000); /* wait 10ms */ } - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + for (phyno = 1; phyno < 32 && phyaddr < 0; ++phyno) { phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1)); #ifdef ET_DEBUG printf ("PHY type 0x%x pass %d type ", phytype, pass); diff --git a/cpu/mcf52x2/serial.c b/cpu/mcf52x2/serial.c index 10117889ada..8be09e34fef 100644 --- a/cpu/mcf52x2/serial.c +++ b/cpu/mcf52x2/serial.c @@ -55,45 +55,75 @@ void rs_serial_setbaudrate(int port,int baudrate) { #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5271) volatile unsigned char *uartp; -#ifndef CONFIG_M5271 +# ifndef CONFIG_M5271 double fraction; -#endif +# endif double clock; if (port == 0) - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); else - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); - clock = DoubleClock(baudrate); /* Set baud above */ + clock = DoubleClock(baudrate); /* Set baud above */ - uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ - uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */ + uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ + uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */ -#ifndef CONFIG_M5271 +# ifndef CONFIG_M5271 fraction = ((clock - (int)clock) * 16.0) + 0.5; - uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */ + uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */ +# endif #endif + +#if defined(CONFIG_M5282) + volatile unsigned char *uartp; + long clock; + + switch (port) { + case 1: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); + break; + case 2: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); + break; + default: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + } + + clock = (long) CFG_CLK / ((long) 32 * baudrate); /* Set baud above */ + + uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ + uartp[MCFUART_UBG2] = ((int) clock & 0xff); /* set lsb baud */ + #endif }; -void rs_serial_init(int port,int baudrate) +void rs_serial_init (int port, int baudrate) { - volatile unsigned char *uartp; + volatile unsigned char *uartp; /* - * Reset UART, get it into known state... + * Reset UART, get it into known state... */ - if (port == 0) - uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); - else + switch (port) { + case 1: uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); + break; +#if defined(CONFIG_M5282) + case 2: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); + break; +#endif + default: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + } - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */ + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */ + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */ - uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */ + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */ + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */ /* * Set port for CONSOLE_BAUD_RATE, 8 data bits, 1 stop bit, no parity. @@ -107,7 +137,7 @@ void rs_serial_init(int port,int baudrate) /* Set clock Select Register: Tx/Rx clock is timer */ uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER; - rs_serial_setbaudrate(port,baudrate); + rs_serial_setbaudrate (port, baudrate); /* Enable Tx/Rx */ uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE; @@ -169,9 +199,8 @@ void serial_putc(const char c) { } void serial_puts (const char *s) { - while (*s) { + while (*s) serial_putc(*s++); - } } int serial_getc(void) { diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 3ab812b3d4b..8a83ca5ef7d 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -55,11 +55,15 @@ */ _vectors: -#ifndef CONFIG_R5200 -.long 0x00000000, _START +.long 0x00000000 /* Flash offset is 0 until we setup CS0 */ +#if defined(CONFIG_R5200) +.long 0x400 +#elif defined(CONFIG_M5282) +.long _start - TEXT_BASE #else -.long 0x00000000, 0x400 /* Flash offset is 0 until we setup CS0 */ +.long _START #endif + .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT @@ -100,20 +104,23 @@ _vectors: .text + +#if defined(CFG_INT_FLASH_BASE) && \ + (defined(CONFIG_M5282) || defined(CONFIG_M5281)) + #if (TEXT_BASE == CFG_INT_FLASH_BASE) + .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */ + .long 0xFFFFFFFF /* all sectors protected */ + .long 0x00000000 /* supervisor/User restriction */ + .long 0x00000000 /* programm/data space restriction */ + .long 0x00000000 /* Flash security */ + #endif +#endif .globl _start _start: nop nop move.w #0x2700,%sr - /* if we come from a pre-loader we have no exception table and - * therefore no VBR to set - */ -#if !defined(CONFIG_MONITOR_IS_IN_RAM) - move.l #CFG_FLASH_BASE, %d0 - movec %d0, %VBR -#endif - #if defined(CONFIG_M5272) || defined(CONFIG_M5249) move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */ move.c %d0, %MBAR @@ -128,20 +135,48 @@ _start: movec %d0, %RAMBAR0 #endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */ -#if defined(CONFIG_M5282) || defined(CONFIG_M5271) +#if defined(CONFIG_M5282) || defined(CONFIG_M5271) /* Initialize IPSBAR */ move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ move.l %d0, 0x40000000 -#ifdef CONFIG_M5282 + /* Initialize RAMBAR1: locate SRAM and validate it */ + move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 + movec %d0, %RAMBAR1 + +#if (TEXT_BASE == CFG_INT_FLASH_BASE) + /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */ + + move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0 + move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1 + move.l #(CFG_INIT_RAM_ADDR), %a2 +_copy_flash: + move.l (%a0)+, (%a2)+ + cmp.l %a0, %a1 + bgt.s _copy_flash + jmp CFG_INIT_RAM_ADDR + +_flashbar_setup: /* Initialize FLASHBAR: locate internal Flash and validate it */ move.l #(CFG_INT_FLASH_BASE + 0x21), %d0 movec %d0, %RAMBAR0 -#endif + jmp _after_flashbar_copy.L /* Force jump to absolute address */ +_flashbar_setup_end: + nop +_after_flashbar_copy: +#else + /* Setup code to initialize FLASHBAR, if start from external Memory */ + move.l #(CFG_INT_FLASH_BASE + 0x21), %d0 + movec %d0, %RAMBAR0 +#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */ - /* Initialize RAMBAR1: locate SRAM and validate it */ - move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 - movec %d0, %RAMBAR1 +#endif + /* if we come from a pre-loader we have no exception table and + * therefore no VBR to set + */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + move.l #CFG_FLASH_BASE, %d0 + movec %d0, %VBR #endif #ifdef CONFIG_R5200 @@ -218,7 +253,6 @@ relocate_code: move.l #CFG_MONITOR_BASE, %a1 move.l #__init_end, %a2 move.l %a0, %a3 - /* copy the code to RAM */ 1: move.l (%a1)+, (%a3)+ @@ -229,14 +263,14 @@ relocate_code: * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ - move.l %a0, %a1 + move.l %a0, %a1 add.l #(in_ram - CFG_MONITOR_BASE), %a1 jmp (%a1) in_ram: clear_bss: - /* + /* * Now clear BSS segment */ move.l %a0, %a1 @@ -266,6 +300,23 @@ clear_bss: cmp.l %a2, %a1 bne 7b +#if defined(CONFIG_M5281) || defined(CONFIG_M5282) + /* patch the 3 accesspoints to 3 ichache_state */ + /* quick and dirty */ + + move.l %a0,%d1 + add.l #(icache_state - CFG_MONITOR_BASE),%d1 + move.l %a0,%a1 + add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1 + move.l %d1,(%a1) + move.l %a0,%a1 + add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1 + move.l %d1,(%a1) + move.l %a0,%a1 + add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1 + move.l %d1,(%a1) +#endif + /* calculate relative jump to board_init_r in ram */ move.l %a0, %a1 add.l #(board_init_r - CFG_MONITOR_BASE), %a1 @@ -273,6 +324,10 @@ clear_bss: /* set parameters for board_init_r */ move.l %a0,-(%sp) /* dest_addr */ move.l %d0,-(%sp) /* gd */ + #if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \ + defined(CFG_HALT_BEFOR_RAM_JUMP) + halt + #endif jsr (%a1) /*------------------------------------------------------------------------------*/ @@ -327,6 +382,7 @@ icache_enable: move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/ movec %d0, %CACR /* Enable cache */ moveq #1, %d0 +icache_state_access_1: move.l %d0, icache_state rts #endif @@ -361,18 +417,19 @@ icache_disable: movec %d0, %ACR0 /* Enable cache */ movec %d0, %ACR1 /* Enable cache */ moveq #0, %d0 +icache_state_access_2: move.l %d0, icache_state rts .globl icache_status icache_status: +icache_state_access_3: move.l icache_state, %d0 rts .data icache_state: - .long 1 - + .long 0 /* cache is diabled on inirialization */ /*------------------------------------------------------------------------------*/ diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk index c357615c033..b29986e26b7 100644 --- a/cpu/mips/config.mk +++ b/cpu/mips/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # v=$(shell \ -mips-linux-as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}') +$(CROSS_COMPILE)as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}') MIPSFLAGS=$(shell \ if [ "$v" -lt "14" ]; then \ echo "-mcpu=4kc"; \ diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c index cacb9f05733..6cb523d3c7b 100644 --- a/cpu/mpc5xxx/serial.c +++ b/cpu/mpc5xxx/serial.c @@ -23,6 +23,9 @@ * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with * changes based on the file arch/ppc/mbxboot/m8260_tty.c from the * Linux/PPC sources (m8260_tty.c had no copyright info in it). + * + * Martin Krause, 8 Jun 2006 + * Added CONFIG_SERIAL_MULTI support */ /* @@ -33,6 +36,10 @@ #include <common.h> #include <mpc5xxx.h> +#if defined (CONFIG_SERIAL_MULTI) +#include <serial.h> +#endif + DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_PSC_CONSOLE) @@ -55,9 +62,41 @@ DECLARE_GLOBAL_DATA_PTR; #error CONFIG_PSC_CONSOLE must be in 1 ... 6 #endif +#if defined(CONFIG_SERIAL_MULTI) && !defined(CONFIG_PSC_CONSOLE2) +#error you must define CONFIG_PSC_CONSOLE2 if CONFIG_SERIAL_MULTI is set +#endif + +#if defined(CONFIG_SERIAL_MULTI) +#if CONFIG_PSC_CONSOLE2 == 1 +#define PSC_BASE2 MPC5XXX_PSC1 +#elif CONFIG_PSC_CONSOLE2 == 2 +#define PSC_BASE2 MPC5XXX_PSC2 +#elif CONFIG_PSC_CONSOLE2 == 3 +#define PSC_BASE2 MPC5XXX_PSC3 +#elif defined(CONFIG_MGT5100) +#error CONFIG_PSC_CONSOLE2 must be in 1, 2 or 3 +#elif CONFIG_PSC_CONSOLE2 == 4 +#define PSC_BASE2 MPC5XXX_PSC4 +#elif CONFIG_PSC_CONSOLE2 == 5 +#define PSC_BASE2 MPC5XXX_PSC5 +#elif CONFIG_PSC_CONSOLE2 == 6 +#define PSC_BASE2 MPC5XXX_PSC6 +#else +#error CONFIG_PSC_CONSOLE2 must be in 1 ... 6 +#endif +#endif /* CONFIG_SERIAL_MULTI */ + +#if defined(CONFIG_SERIAL_MULTI) +int serial_init_dev (unsigned long dev_base) +#else int serial_init (void) +#endif { +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif unsigned long baseclk; int div; @@ -100,13 +139,24 @@ int serial_init (void) return (0); } -void -serial_putc(const char c) +#if defined(CONFIG_SERIAL_MULTI) +void serial_putc_dev (unsigned long dev_base, const char c) +#else +void serial_putc(const char c) +#endif { +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif if (c == '\n') +#if defined(CONFIG_SERIAL_MULTI) + serial_putc_dev (dev_base, '\r'); +#else serial_putc('\r'); +#endif /* Wait for last character to go. */ while (!(psc->psc_status & PSC_SR_TXEMP)) @@ -115,18 +165,32 @@ serial_putc(const char c) psc->psc_buffer_8 = c; } -void -serial_puts (const char *s) +#if defined(CONFIG_SERIAL_MULTI) +void serial_puts_dev (unsigned long dev_base, const char *s) +#else +void serial_puts (const char *s) +#endif { while (*s) { +#if defined(CONFIG_SERIAL_MULTI) + serial_putc_dev (dev_base, *s++); +#else serial_putc (*s++); +#endif } } -int -serial_getc(void) +#if defined(CONFIG_SERIAL_MULTI) +int serial_getc_dev (unsigned long dev_base) +#else +int serial_getc(void) +#endif { +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif /* Wait for a character to arrive. */ while (!(psc->psc_status & PSC_SR_RXRDY)) @@ -135,18 +199,32 @@ serial_getc(void) return psc->psc_buffer_8; } -int -serial_tstc(void) +#if defined(CONFIG_SERIAL_MULTI) +int serial_tstc_dev (unsigned long dev_base) +#else +int serial_tstc(void) +#endif { +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif return (psc->psc_status & PSC_SR_RXRDY); } -void -serial_setbrg(void) +#if defined(CONFIG_SERIAL_MULTI) +void serial_setbrg_dev (unsigned long dev_base) +#else +void serial_setbrg(void) +#endif { +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif unsigned long baseclk, div; #if defined(CONFIG_MGT5100) @@ -160,4 +238,87 @@ serial_setbrg(void) psc->ctur = (div >> 8) & 0xFF; psc->ctlr = div & 0xff; } + +#if defined(CONFIG_SERIAL_MULTI) +int serial0_init(void) +{ + return (serial_init_dev(PSC_BASE)); +} + +int serial1_init(void) +{ + return (serial_init_dev(PSC_BASE2)); +} +void serial0_setbrg (void) +{ + serial_setbrg_dev(PSC_BASE); +} +void serial1_setbrg (void) +{ + serial_setbrg_dev(PSC_BASE2); +} + +void serial0_putc(const char c) +{ + serial_putc_dev(PSC_BASE,c); +} + +void serial1_putc(const char c) +{ + serial_putc_dev(PSC_BASE2, c); +} +void serial0_puts(const char *s) +{ + serial_puts_dev(PSC_BASE, s); +} + +void serial1_puts(const char *s) +{ + serial_puts_dev(PSC_BASE2, s); +} + +int serial0_getc(void) +{ + return(serial_getc_dev(PSC_BASE)); +} + +int serial1_getc(void) +{ + return(serial_getc_dev(PSC_BASE2)); +} +int serial0_tstc(void) +{ + return (serial_tstc_dev(PSC_BASE)); +} + +int serial1_tstc(void) +{ + return (serial_tstc_dev(PSC_BASE2)); +} + +struct serial_device serial0_device = +{ + "serial0", + "UART0", + serial0_init, + serial0_setbrg, + serial0_getc, + serial0_tstc, + serial0_putc, + serial0_puts, +}; + +struct serial_device serial1_device = +{ + "serial1", + "UART1", + serial1_init, + serial1_setbrg, + serial1_getc, + serial1_tstc, + serial1_putc, + serial1_puts, +}; +#endif /* CONFIG_SERIAL_MULTI */ + #endif /* CONFIG_PSC_CONSOLE */ diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c index 1a7111fb2a6..c79e5780ad3 100644 --- a/cpu/mpc8xx/cpu_init.c +++ b/cpu/mpc8xx/cpu_init.c @@ -161,6 +161,7 @@ void cpu_init_f (volatile immap_t * immr) defined(CONFIG_RMU) || \ defined(CONFIG_RPXCLASSIC) || \ defined(CONFIG_RPXLITE) || \ + defined(CONFIG_SPC1920) || \ defined(CONFIG_SPD823TS) memctl->memc_br0 = CFG_BR0_PRELIM; diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c index 6006478f97c..6d2755e8304 100644 --- a/cpu/mpc8xx/fec.c +++ b/cpu/mpc8xx/fec.c @@ -396,8 +396,10 @@ static void fec_pin_init(int fecidx) * * to 2.5 MHz. * * This MDC frequency is equal to system clock / (2 * MII_SPEED). * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz. + * + * All MII configuration is done via FEC1 registers: */ - fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; + immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; #if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2) /* our PHYs are the limit at 2.5 MHz */ @@ -508,8 +510,6 @@ static void fec_pin_init(int fecidx) #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ #if !defined(CONFIG_RMII) - -#warning this configuration is not tested; please report if it works immr->im_cpm.cp_pepar |= 0x0003fffc; immr->im_cpm.cp_pedir |= 0x0003fffc; immr->im_cpm.cp_peso &= ~0x000087fc; @@ -822,6 +822,7 @@ static void fec_halt(struct eth_device* dev) #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ #define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */ +#define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */ /* send command to phy using mii, wait for result */ static uint @@ -907,6 +908,9 @@ static int mii_discover_phy(struct eth_device *dev) case PHY_ID_DM9161: printf("Davicom DM9161\n"); break; + case PHY_ID_KSM8995M: + printf("MICREL KS8995M\n"); + break; default: printf("0x%08x\n", phytype); break; diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c index 26a82cc2405..8ae584f2e1d 100644 --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@ -227,9 +227,12 @@ static int smc_init (void) sp->smc_smcm = 0; sp->smc_smce = 0xff; - /* Set up the baud rate generator. - */ +#ifdef CFG_SPC1920_SMC1_CLK4 /* clock source is PLD */ + *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0xff; +#else + /* Set up the baud rate generator */ smc_setbrg (); +#endif /* Make the first buffer the only buffer. */ diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c index 57f91c0aa04..101d5f9cb35 100644 --- a/cpu/mpc8xx/speed.c +++ b/cpu/mpc8xx/speed.c @@ -259,7 +259,11 @@ int get_clocks_866 (void) */ sccr_reg = immr->im_clkrst.car_sccr; sccr_reg &= ~SCCR_EBDF11; +#if defined(CONFIG_TQM885D) + if (gd->cpu_clk <= 80000000) { +#else if (gd->cpu_clk <= 66000000) { +#endif sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */ gd->bus_clk = gd->cpu_clk; } else { @@ -360,7 +364,8 @@ static long init_pll_866 (long clk) #endif /* CONFIG_8xx_CPUCLK_DEFAULT */ -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) +#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ + && !defined(CONFIG_TQM885D) /* * Adjust sdram refresh rate to actual CPU clock * and set timebase source according to actual CPU clock @@ -384,6 +389,6 @@ int adjust_sdram_tbs_8xx (void) return (0); } -#endif /* CONFIG_TQM8xxL/M, !TQM866M */ +#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */ /* ------------------------------------------------------------------------- */ diff --git a/cpu/nios2/epcs.c b/cpu/nios2/epcs.c index a8851e99a22..414c38c2b1d 100644 --- a/cpu/nios2/epcs.c +++ b/cpu/nios2/epcs.c @@ -25,7 +25,7 @@ #if defined(CFG_NIOS_EPCSBASE) #include <command.h> -#include <nios2.h> +#include <asm/io.h> #include <nios2-io.h> #include <nios2-epcs.h> @@ -72,8 +72,7 @@ */ #define EPCS_TIMEOUT 100 /* 100 msec timeout */ -static nios_spi_t *epcs = - (nios_spi_t *)CACHE_BYPASS(CFG_NIOS_EPCSBASE); +static nios_spi_t *epcs = (nios_spi_t *)CFG_NIOS_EPCSBASE; /*********************************************************************** * Device access @@ -81,16 +80,20 @@ static nios_spi_t *epcs = static int epcs_cs (int assert) { ulong start; + unsigned tmp; + if (assert) { - epcs->control |= NIOS_SPI_SSO; + tmp = readl (&epcs->control); + writel (&epcs->control, tmp | NIOS_SPI_SSO); } else { /* Let all bits shift out */ start = get_timer (0); - while ((epcs->status & NIOS_SPI_TMT) == 0) + while ((readl (&epcs->status) & NIOS_SPI_TMT) == 0) if (get_timer (start) > EPCS_TIMEOUT) return (-1); - epcs->control &= ~NIOS_SPI_SSO; + tmp = readl (&epcs->control); + writel (&epcs->control, tmp & ~NIOS_SPI_SSO); } return (0); } @@ -100,10 +103,10 @@ static int epcs_tx (unsigned char c) ulong start; start = get_timer (0); - while ((epcs->status & NIOS_SPI_TRDY) == 0) + while ((readl (&epcs->status) & NIOS_SPI_TRDY) == 0) if (get_timer (start) > EPCS_TIMEOUT) return (-1); - epcs->txdata = c; + writel (&epcs->txdata, c); return (0); } @@ -112,10 +115,10 @@ static int epcs_rx (void) ulong start; start = get_timer (0); - while ((epcs->status & NIOS_SPI_RRDY) == 0) + while ((readl (&epcs->status) & NIOS_SPI_RRDY) == 0) if (get_timer (start) > EPCS_TIMEOUT) return (-1); - return (epcs->rxdata); + return (readl (&epcs->rxdata)); } static unsigned char bitrev[] = { @@ -207,6 +210,21 @@ static struct epcs_devinfo_t devinfo[] = { { 0, 0, 0, 0, 0, 0 } }; +int epcs_reset (void) +{ + /* When booting from an epcs controller, the epcs bootrom + * code may leave the slave select in an asserted state. + * This causes two problems: (1) The initial epcs access + * will fail -- not a big deal, and (2) a software reset + * will cause the bootrom code to hang since it does not + * ensure the select is negated prior to first access -- a + * big deal. Here we just negate chip select and everything + * gets better :-) + */ + epcs_cs (0); /* Negate chip select */ + return (0); +} + epcs_devinfo_t *epcs_dev_find (void) { unsigned char buf[4]; diff --git a/cpu/nios2/exceptions.S b/cpu/nios2/exceptions.S index d3b95cfc7aa..b9c7a587e14 100644 --- a/cpu/nios2/exceptions.S +++ b/cpu/nios2/exceptions.S @@ -30,6 +30,9 @@ .global _exception + .set noat + .set nobreak + _exception: /* SAVE ALL REGS -- this allows trap and unimplemented * instruction handlers to be coded conveniently in C diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c index 4a6da582bb7..4685161b88a 100644 --- a/cpu/nios2/interrupts.c +++ b/cpu/nios2/interrupts.c @@ -27,6 +27,7 @@ #include <nios2.h> #include <nios2-io.h> +#include <asm/io.h> #include <asm/ptrace.h> #include <common.h> #include <command.h> @@ -79,7 +80,7 @@ void tmr_isr (void *arg) /* Interrupt is cleared by writing anything to the * status register. */ - tmr->status = 0; + writel (&tmr->status, 0); timestamp += CFG_NIOS_TMRMS; #ifdef CONFIG_STATUS_LED status_led_tick(timestamp); @@ -88,16 +89,17 @@ void tmr_isr (void *arg) static void tmr_init (void) { - nios_timer_t *tmr =(nios_timer_t *)CACHE_BYPASS(CFG_NIOS_TMRBASE); + nios_timer_t *tmr =(nios_timer_t *)CFG_NIOS_TMRBASE; + + writel (&tmr->status, 0); + writel (&tmr->control, 0); + writel (&tmr->control, NIOS_TIMER_STOP); - tmr->control &= ~(NIOS_TIMER_START | NIOS_TIMER_ITO); - tmr->control |= NIOS_TIMER_STOP; #if defined(CFG_NIOS_TMRCNT) - tmr->periodl = CFG_NIOS_TMRCNT & 0xffff; - tmr->periodh = (CFG_NIOS_TMRCNT >> 16) & 0xffff; + writel (&tmr->periodl, CFG_NIOS_TMRCNT & 0xffff); + writel (&tmr->periodh, (CFG_NIOS_TMRCNT >> 16) & 0xffff); #endif - tmr->control |= ( NIOS_TIMER_ITO | - NIOS_TIMER_CONT | + writel (&tmr->control, NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START ); irq_install_handler (CFG_NIOS_TMRIRQ, tmr_isr, (void *)tmr); } diff --git a/cpu/nios2/serial.c b/cpu/nios2/serial.c index 3d766037a14..0bd3821e395 100644 --- a/cpu/nios2/serial.c +++ b/cpu/nios2/serial.c @@ -24,7 +24,7 @@ #include <common.h> #include <watchdog.h> -#include <nios2.h> +#include <asm/io.h> #include <nios2-io.h> DECLARE_GLOBAL_DATA_PTR; @@ -34,8 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; *-----------------------------------------------------------------*/ #if defined(CONFIG_CONSOLE_JTAG) -static nios_jtag_t *jtag = - (nios_jtag_t *)CACHE_BYPASS(CFG_NIOS_CONSOLE); +static nios_jtag_t *jtag = (nios_jtag_t *)CFG_NIOS_CONSOLE; void serial_setbrg( void ){ return; } int serial_init( void ) { return(0);} @@ -44,9 +43,9 @@ void serial_putc (char c) { unsigned val; - while (NIOS_JTAG_WSPACE (jtag->control) == 0) + while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0) WATCHDOG_RESET (); - jtag->data = (unsigned char)c; + writel (&jtag->data, (unsigned char)c); } void serial_puts (const char *s) @@ -57,7 +56,7 @@ void serial_puts (const char *s) int serial_tstc (void) { - return (jtag->control & NIOS_JTAG_RRDY); + return ( readl (&jtag->control) & NIOS_JTAG_RRDY); } int serial_getc (void) @@ -67,7 +66,7 @@ int serial_getc (void) while (1) { WATCHDOG_RESET (); - val = jtag->data; + val = readl (&jtag->data); if (val & NIOS_JTAG_RVALID) break; } @@ -80,8 +79,7 @@ int serial_getc (void) *-----------------------------------------------------------------*/ #else -static nios_uart_t *uart = (nios_uart_t *) - CACHE_BYPASS(CFG_NIOS_CONSOLE); +static nios_uart_t *uart = (nios_uart_t *) CFG_NIOS_CONSOLE; #if defined(CFG_NIOS_FIXEDBAUD) @@ -98,7 +96,7 @@ void serial_setbrg (void) unsigned div; div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1; - uart->divisor = div; + writel (&uart->divisor,div); return; } @@ -118,9 +116,9 @@ void serial_putc (char c) { if (c == '\n') serial_putc ('\r'); - while ((uart->status & NIOS_UART_TRDY) == 0) + while ((readl (&uart->status) & NIOS_UART_TRDY) == 0) WATCHDOG_RESET (); - uart->txdata = (unsigned char)c; + writel (&uart->txdata,(unsigned char)c); } void serial_puts (const char *s) @@ -132,14 +130,14 @@ void serial_puts (const char *s) int serial_tstc (void) { - return (uart->status & NIOS_UART_RRDY); + return (readl (&uart->status) & NIOS_UART_RRDY); } int serial_getc (void) { while (serial_tstc () == 0) WATCHDOG_RESET (); - return( uart->rxdata & 0x00ff ); + return (readl (&uart->rxdata) & 0x00ff ); } #endif /* CONFIG_JTAG_CONSOLE */ diff --git a/cpu/nios2/sysid.c b/cpu/nios2/sysid.c index 2b7a569cc50..b5a29593ea6 100644 --- a/cpu/nios2/sysid.c +++ b/cpu/nios2/sysid.c @@ -26,20 +26,21 @@ #if defined (CFG_NIOS_SYSID_BASE) #include <command.h> -#include <nios2.h> +#include <asm/io.h> #include <nios2-io.h> #include <linux/time.h> void display_sysid (void) { - struct nios_sysid_t *sysid = - (struct nios_sysid_t *)CACHE_BYPASS(CFG_NIOS_SYSID_BASE); + struct nios_sysid_t *sysid = (struct nios_sysid_t *)CFG_NIOS_SYSID_BASE; struct tm t; char asc[32]; + time_t stamp; - localtime_r ((time_t *)&sysid->timestamp, &t); + stamp = readl (&sysid->timestamp); + localtime_r (&stamp, &t); asctime_r (&t, asc); - printf ("SYSID : %08x, %s", sysid->id, asc); + printf ("SYSID : %08x, %s", readl (&sysid->id), asc); } diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index fad895b3191..cf5eccb01fd 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -438,7 +438,7 @@ void pci_440_init (struct pci_controller *hose) * The PCI initialization sequence enable bit must be set ... if not abort * pci setup since updating the bit requires chip reset. *--------------------------------------------------------------------------*/ -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long strap; mfsdr(sdr_sdstp1,strap); @@ -465,17 +465,30 @@ void pci_440_init (struct pci_controller *hose) hose->first_busno = 0; hose->last_busno = 0xff; + /* PCI I/O space */ pci_set_region(hose->regions + reg_num++, 0x00000000, PCIX0_IOBASE, 0x10000, PCI_REGION_IO); + /* PCI memory space */ pci_set_region(hose->regions + reg_num++, CFG_PCI_TARGBASE, CFG_PCI_MEMBASE, 0x10000000, PCI_REGION_MEM ); + +#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \ + defined(CONFIG_PCI_SYS_MEM_SIZE) + /* System memory space */ + pci_set_region(hose->regions + reg_num++, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + CONFIG_PCI_SYS_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY ); +#endif + hose->region_count = reg_num; pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA); @@ -502,7 +515,7 @@ void pci_440_init (struct pci_controller *hose) out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ #endif -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ #elif defined(PCIX0_BRDGOPT1) @@ -520,8 +533,13 @@ void pci_440_init (struct pci_controller *hose) out32r( PCIX0_POM0SA, 0 ); /* disable */ out32r( PCIX0_POM1SA, 0 ); /* disable */ out32r( PCIX0_POM2SA, 0 ); /* disable */ +#if defined(CONFIG_440SPE) + out32r( PCIX0_POM0LAL, 0x10000000 ); + out32r( PCIX0_POM0LAH, 0x0000000c ); +#else out32r( PCIX0_POM0LAL, 0x00000000 ); out32r( PCIX0_POM0LAH, 0x00000003 ); +#endif out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE ); out32r( PCIX0_POM0PCIAH, 0x00000000 ); out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 86dc2d066e8..fab65aff78a 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -181,6 +181,9 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) { EMAC_4XX_HW_PST hw_p = dev->priv; uint32_t failsafe = 10000; +#if defined(CONFIG_440SPE) + unsigned long mfr; +#endif out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ @@ -202,8 +205,23 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) } /* EMAC RESET */ +#if defined(CONFIG_440SPE) + /* provide clocks for EMAC internal loopback */ + mfsdr (sdr_mfr, mfr); + mfr |= 0x08000000; + mtsdr(sdr_mfr, mfr); +#endif + out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); +#if defined(CONFIG_440SPE) + /* remove clocks for EMAC internal loopback */ + mfsdr (sdr_mfr, mfr); + mfr &= ~0x08000000; + mtsdr(sdr_mfr, mfr); +#endif + + #ifndef CONFIG_NETCONSOLE hw_p->print_speed = 1; /* print speed message again next time */ #endif @@ -301,7 +319,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) return ((int)pfc1); } -#endif +#endif /* CONFIG_440_GX */ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) { @@ -314,12 +332,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) unsigned mode_reg; unsigned short devnum; unsigned short reg_short; -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) sys_info_t sysinfo; -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) int ethgroup = -1; #endif #endif +#if defined(CONFIG_440SPE) + unsigned long mfr; +#endif + EMAC_4XX_HW_PST hw_p = dev->priv; @@ -330,7 +352,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) return -1; } -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* Need to get the OPB frequency so we can access the PHY */ get_sys_info (&sysinfo); #endif @@ -360,6 +382,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) hw_p->stats.pkts_tx = 0; hw_p->stats.pkts_rx = 0; hw_p->stats.pkts_handled = 0; + hw_p->print_speed = 1; /* print speed message again next time */ #endif hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */ @@ -373,7 +396,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */ hw_p->tx_u_index = 0; /* Transmit User Queue Index */ -#if defined(CONFIG_440) && !defined(CONFIG_440SP) +#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) /* set RMII mode */ /* NOTE: 440GX spec states that mode is mutually exclusive */ /* NOTE: Therefore, disable all other EMACS, since we handle */ @@ -406,6 +429,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) __asm__ volatile ("eieio"); /* reset emac so we have access to the phy */ +#if defined(CONFIG_440SPE) + /* provide clocks for EMAC internal loopback */ + mfsdr (sdr_mfr, mfr); + mfr |= 0x08000000; + mtsdr(sdr_mfr, mfr); +#endif out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); __asm__ volatile ("eieio"); @@ -416,7 +445,14 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) failsafe--; } -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440SPE) + /* remove clocks for EMAC internal loopback */ + mfsdr (sdr_mfr, mfr); + mfr &= ~0x08000000; + mtsdr(sdr_mfr, mfr); +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* Whack the M1 register */ mode_reg = 0x0; mode_reg &= ~0x00000038; @@ -468,7 +504,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) if (hw_p->first_init == 0) { miiphy_reset (dev->name, reg); -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) #if defined(CONFIG_CIS8201_PHY) /* * Cicada 8201 PHY needs to have an extended register whacked @@ -544,7 +580,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) (int) speed, (duplex == HALF) ? "HALF" : "FULL"); } -#if defined(CONFIG_440) && !defined(CONFIG_440SP) +#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) mfsdr(sdr_mfr, reg); if (speed == 100) { @@ -575,7 +611,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ /* set the Mal configuration reg */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); #else @@ -759,8 +795,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* set speed */ if (speed == _1000BASET) { -#if defined(CONFIG_440SP) -#define SDR0_PFC1_EM_1000 0x00200000 +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long pfc1; mfsdr (sdr_pfc1, pfc1); pfc1 |= SDR0_PFC1_EM_1000; @@ -787,7 +822,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* set receive low/high water mark register */ #if defined(CONFIG_440) - /* 440GP has a 64 byte burst length */ + /* 440s has a 64 byte burst length */ out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); #else /* 405s have a 16 byte burst length */ @@ -895,7 +930,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, #if defined (CONFIG_440) -#if defined(CONFIG_440SP) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* * Hack: On 440SP all enet irq sources are located on UIC1 * Needs some cleanup. --sr @@ -1367,21 +1402,20 @@ int ppc_4xx_eth_initialize (bd_t * bis) #endif /* set phy num and mode */ bis->bi_phynum[0] = CONFIG_PHY_ADDR; + bis->bi_phymode[0] = 0; + #if defined(CONFIG_PHY1_ADDR) bis->bi_phynum[1] = CONFIG_PHY1_ADDR; + bis->bi_phymode[1] = 0; #endif #if defined(CONFIG_440GX) bis->bi_phynum[2] = CONFIG_PHY2_ADDR; bis->bi_phynum[3] = CONFIG_PHY3_ADDR; - bis->bi_phymode[0] = 0; - bis->bi_phymode[1] = 0; bis->bi_phymode[2] = 2; bis->bi_phymode[3] = 2; -#if defined (CONFIG_440GX) ppc_4xx_eth_setup_bridge(0, bis); #endif -#endif for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { @@ -1478,9 +1512,15 @@ int ppc_4xx_eth_initialize (bd_t * bis) if (0 == virgin) { /* set the MAL IER ??? names may change with new spec ??? */ +#if defined(CONFIG_440SPE) + mal_ier = + MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE | + MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ; +#else mal_ier = MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | MAL_IER_OPBE | MAL_IER_PLBE; +#endif mtdcr (malesr, 0xffffffff); /* clear pending interrupts */ mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */ mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */ @@ -1510,11 +1550,13 @@ int ppc_4xx_eth_initialize (bd_t * bis) #else emac0_dev = dev; #endif + +#if defined(CONFIG_NET_MULTI) #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) miiphy_register (dev->name, emac4xx_miiphy_read, emac4xx_miiphy_write); #endif - +#endif } /* end for each supported device */ return (1); } diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index d9b5d32c90c..71303bcc49f 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -82,7 +82,9 @@ int pci_arbiter_enabled(void) return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK); #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) unsigned long val; mfsdr(sdr_sdstp1, val); @@ -91,8 +93,8 @@ int pci_arbiter_enabled(void) } #endif -#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define I2C_BOOTROM @@ -102,7 +104,9 @@ int i2c_bootrom_enabled(void) return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP); #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) unsigned long val; mfsdr(sdr_sdcs, val); @@ -248,6 +252,14 @@ int checkcpu (void) puts("SP Rev. B"); break; + case PVR_440SPe_RA: + puts("SPe Rev. A"); + break; + + case PVR_440SPe_RB: + puts("SPe Rev. B"); + break; + default: printf (" UNKNOWN (PVR=%08x)", pvr); break; diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 3aae4ce8b99..886f4051562 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -50,18 +50,22 @@ struct irq_action { }; static struct irq_action irq_vecs[32]; +void uic0_interrupt( void * parms); /* UIC0 handler */ #if defined(CONFIG_440) static struct irq_action irq_vecs1[32]; /* For UIC1 */ void uic1_interrupt( void * parms); /* UIC1 handler */ -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) static struct irq_action irq_vecs2[32]; /* For UIC2 */ - -void uic0_interrupt( void * parms); /* UIC0 handler */ void uic2_interrupt( void * parms); /* UIC2 handler */ -#endif /* CONFIG_440GX */ +#endif /* CONFIG_440GX CONFIG_440SPE */ + +#if defined(CONFIG_440SPE) +static struct irq_action irq_vecs3[32]; /* For UIC3 */ +void uic3_interrupt( void * parms); /* UIC3 handler */ +#endif /* CONFIG_440SPE */ #endif /* CONFIG_440 */ @@ -115,11 +119,16 @@ int interrupt_init_cpu (unsigned *decrementer_count) irq_vecs1[vec].handler = NULL; irq_vecs1[vec].arg = NULL; irq_vecs1[vec].count = 0; -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) irq_vecs2[vec].handler = NULL; irq_vecs2[vec].arg = NULL; irq_vecs2[vec].count = 0; #endif /* CONFIG_440GX */ +#if defined(CONFIG_440SPE) + irq_vecs3[vec].handler = NULL; + irq_vecs3[vec].arg = NULL; + irq_vecs3[vec].count = 0; +#endif /* CONFIG_440SPE */ #endif } @@ -221,6 +230,34 @@ void external_interrupt(struct pt_regs *regs) } /* external_interrupt CONFIG_440GX */ +#elif defined(CONFIG_440SPE) +void external_interrupt(struct pt_regs *regs) +{ + ulong uic_msr; + + /* + * Read masked interrupt status register to determine interrupt source + */ + /* 440 SPe uses base uic register */ + uic_msr = mfdcr(uic0msr); + + if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) ) + uic1_interrupt(0); + + if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) ) + uic2_interrupt(0); + + if ( (UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr) ) + uic3_interrupt(0); + + if (uic_msr & ~(UICB0_ALL)) + uic0_interrupt(0); + + mtdcr(uic0sr, uic_msr); + + return; +} /* external_interrupt CONFIG_440SPE */ + #else void external_interrupt(struct pt_regs *regs) @@ -266,7 +303,7 @@ void external_interrupt(struct pt_regs *regs) } #endif -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) /* Handler for UIC0 interrupt */ void uic0_interrupt( void * parms) { @@ -357,8 +394,8 @@ void uic1_interrupt( void * parms) } #endif /* defined(CONFIG_440) */ -#if defined(CONFIG_440GX) -/* Handler for UIC1 interrupt */ +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +/* Handler for UIC2 interrupt */ void uic2_interrupt( void * parms) { ulong uic2_msr; @@ -384,7 +421,7 @@ void uic2_interrupt( void * parms) (*irq_vecs2[vec].handler)(irq_vecs2[vec].arg); } else { mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> vec)); - printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec); + printf ("Masking bogus interrupt vector (uic2) 0x%x\n", vec); } /* @@ -402,6 +439,51 @@ void uic2_interrupt( void * parms) } #endif /* defined(CONFIG_440GX) */ +#if defined(CONFIG_440SPE) +/* Handler for UIC3 interrupt */ +void uic3_interrupt( void * parms) +{ + ulong uic3_msr; + ulong msr_shift; + int vec; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic3_msr = mfdcr(uic3msr); + msr_shift = uic3_msr; + vec = 0; + + while (msr_shift != 0) { + if (msr_shift & 0x80000000) { + /* + * Increment irq counter (for debug purpose only) + */ + irq_vecs3[vec].count++; + + if (irq_vecs3[vec].handler != NULL) { + /* call isr */ + (*irq_vecs3[vec].handler)(irq_vecs3[vec].arg); + } else { + mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> vec)); + printf ("Masking bogus interrupt vector (uic3) 0x%x\n", vec); + } + + /* + * After servicing the interrupt, we have to remove the status indicator. + */ + mtdcr(uic3sr, (0x80000000 >> vec)); + } + + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } +} +#endif /* defined(CONFIG_440SPE) */ + /****************************************************************************/ /* @@ -414,7 +496,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) int i = vec; #if defined(CONFIG_440) -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) if ((vec > 31) && (vec < 64)) { i = vec - 32; irqa = irq_vecs1; @@ -441,7 +523,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) irqa[i].arg = arg; #if defined(CONFIG_440) -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) if ((vec > 31) && (vec < 64)) mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i)); else if (vec > 63) @@ -464,7 +546,7 @@ void irq_free_handler (int vec) int i = vec; #if defined(CONFIG_440) -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) if ((vec > 31) && (vec < 64)) { irqa = irq_vecs1; i = vec - 32; @@ -485,7 +567,7 @@ void irq_free_handler (int vec) #endif #if defined(CONFIG_440) -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) if ((vec > 31) && (vec < 64)) mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i)); else if (vec > 63) @@ -553,7 +635,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf("\n"); #endif -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) printf ("\nUIC 2\n"); printf ("Nr Routine Arg Count\n"); @@ -566,6 +648,19 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf("\n"); #endif +#if defined(CONFIG_440SPE) + printf ("\nUIC 3\n"); + printf ("Nr Routine Arg Count\n"); + + for (vec=0; vec<32; vec++) { + if (irq_vecs3[vec].handler != NULL) + printf ("%02d %08lx %08lx %d\n", + vec+63, (ulong)irq_vecs3[vec].handler, + (ulong)irq_vecs3[vec].arg, irq_vecs3[vec].count); + } + printf("\n"); +#endif + return 0; } #endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index f26f2a203a0..aa580ed48f9 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -50,7 +50,7 @@ #include <405_mal.h> #include <miiphy.h> - +#undef ET_DEBUG /***********************************************************/ /* Dump out to the screen PHY regs */ /***********************************************************/ @@ -90,6 +90,10 @@ int phy_setup_aneg (char *devname, unsigned char addr) PHY_ANLPAR_10); miiphy_write (devname, addr, PHY_ANAR, adv); + miiphy_read (devname, addr, PHY_1000BTCR, &adv); + adv |= (0x0300); + miiphy_write (devname, addr, PHY_1000BTCR, adv); + /* Start/Restart aneg */ miiphy_read (devname, addr, PHY_BMCR, &ctl); ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); @@ -104,7 +108,7 @@ int phy_setup_aneg (char *devname, unsigned char addr) /***********************************************************/ unsigned int miiphy_getemac_offset (void) { -#if (defined(CONFIG_440) && !defined(CONFIG_440SP)) && defined(CONFIG_NET_MULTI) +#if (defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)) && defined(CONFIG_NET_MULTI) unsigned long zmii; unsigned long eoffset; @@ -155,10 +159,12 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, i = 0; /* see if it is ready for sec */ - while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) { + while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { udelay (7); if (i > 5) { -#if 0 +#ifdef ET_DEBUG + sta_reg = in32 (EMAC_STACR + emac_reg); + printf ("read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ printf ("read err 1\n"); #endif return -1; @@ -167,31 +173,41 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, } sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ -#if defined(CONFIG_440GX) - sta_reg |= EMAC_STACR_READ; +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ + sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ; +#else + sta_reg |= EMAC_STACR_READ; +#endif #else sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; #endif -#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) +#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; #endif sta_reg = sta_reg | (addr << 5); /* Phy address */ - + sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ out32 (EMAC_STACR + emac_reg, sta_reg); -#if 0 /* test-only */ +#ifdef ET_DEBUG printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif sta_reg = in32 (EMAC_STACR + emac_reg); +#ifdef ET_DEBUG + printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ +#endif i = 0; - while ((sta_reg & EMAC_STACR_OC) == 0) { + while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { udelay (7); if (i > 5) { return -1; } i++; sta_reg = in32 (EMAC_STACR + emac_reg); +#ifdef ET_DEBUG + printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ +#endif } if ((sta_reg & EMAC_STACR_PHYE) != 0) { return -1; @@ -219,7 +235,7 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, /* see if it is ready for 1000 nsec */ i = 0; - while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) { + while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { if (i > 5) return -1; udelay (7); @@ -228,16 +244,21 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, sta_reg = 0; sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ -#if defined(CONFIG_440GX) - sta_reg |= EMAC_STACR_WRITE; +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ + sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE; +#else + sta_reg |= EMAC_STACR_WRITE; +#endif #else sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; #endif -#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) +#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ #endif - sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */ + sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */ + sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ memcpy (&sta_reg, &value, 2); /* put in data */ out32 (EMAC_STACR + emac_reg, sta_reg); @@ -245,12 +266,18 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, /* wait for completion */ i = 0; sta_reg = in32 (EMAC_STACR + emac_reg); - while ((sta_reg & EMAC_STACR_OC) == 0) { +#ifdef ET_DEBUG + printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ +#endif + while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { udelay (7); if (i > 5) return -1; i++; sta_reg = in32 (EMAC_STACR + emac_reg); +#ifdef ET_DEBUG + printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ +#endif } if ((sta_reg & EMAC_STACR_PHYE) != 0) diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index e31d59d80ea..faeea5c91e7 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -379,7 +379,7 @@ long int initdram(int board_type) /* * Enable the controller, then wait for DCEN to complete */ - mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + mtsdram(mem_cfg0, 0x82000000); /* DCEN=1, PMUD=0, 64-bit */ udelay(10000); if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index 83c947998ed..ad3ca6e819e 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -275,11 +275,11 @@ int serial_tstc () #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300 #endif -#if defined(CONFIG_440SP) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600 #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define CR0_MASK 0xdfffffff #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 @@ -309,14 +309,18 @@ int serial_tstc () #if defined(CONFIG_UART1_CONSOLE) #define ACTING_UART0_BASE UART1_BASE #define ACTING_UART1_BASE UART0_BASE -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) #define UART0_SDR sdr_uart1 #define UART1_SDR sdr_uart0 #endif /* CONFIG_440GX */ #else #define ACTING_UART0_BASE UART0_BASE #define ACTING_UART1_BASE UART1_BASE -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) #define UART0_SDR sdr_uart0 #define UART1_SDR sdr_uart1 #endif /* CONFIG_440GX */ @@ -437,7 +441,8 @@ int serial_init(void) unsigned long tmp; #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) #if defined(CONFIG_SERIAL_MULTI) if (UART0_BASE == dev_base) { mfsdr(UART0_SDR,reg); @@ -466,7 +471,9 @@ int serial_init(void) serial_divs (gd->baudrate, &udiv, &bdiv); #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */ #if defined(CONFIG_SERIAL_MULTI) if (UART0_BASE == dev_base) { @@ -607,8 +614,28 @@ void serial_setbrg (void) #else udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1; #endif /* CONFIG_405EP */ + +#if !defined(CFG_EXT_SERIAL_CLOCK) && \ + ( defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) ) + serial_divs (gd->baudrate, &udiv, &bdiv); + tmp = udiv << CR0_UDIV_POS; /* set the UART divisor */ +#if defined(CONFIG_SERIAL_MULTI) + if (UART0_BASE == dev_base) { + mtsdr (UART0_SDR, tmp); + } else { + mtsdr (UART1_SDR, tmp); + } +#else + mtsdr (UART0_SDR, tmp); +#endif + +#else + tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; +#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */ #if defined(CONFIG_SERIAL_MULTI) out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c index ebd5f3998f3..c24456bea84 100644 --- a/cpu/ppc4xx/spd_sdram.c +++ b/cpu/ppc4xx/spd_sdram.c @@ -745,7 +745,7 @@ long int spd_sdram(void) { */ check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); -#if defined(CONFIG_440GX) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) /* * Soft-reset SDRAM controller. */ @@ -1007,9 +1007,9 @@ void program_cfg0(unsigned long* dimm_populated, } /* - * program Page Management Unit + * program Page Management Unit (0 == enabled) */ - cfg0 |= SDRAM_CFG0_PMUD; + cfg0 &= ~SDRAM_CFG0_PMUD; /* * program Memory Controller Options 0 diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 02b43832f24..e552c034733 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -29,7 +29,11 @@ DECLARE_GLOBAL_DATA_PTR; #define ONE_BILLION 1000000000 - +#ifdef DEBUG +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif #if defined(CONFIG_405GP) || defined(CONFIG_405CR) @@ -283,7 +287,7 @@ ulong get_PCI_freq (void) return sys_info.freqPCI; } -#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) +#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) void get_sys_info (sys_info_t * sysInfo) { unsigned long strp0; @@ -326,6 +330,26 @@ void get_sys_info (sys_info_t * sysInfo) unsigned long m; unsigned long prbdv0; +#if defined(CONFIG_440SPE) + unsigned long sys_freq; + unsigned long sys_per=0; + unsigned long msr; + unsigned long pci_clock_per; + unsigned long sdr_ddrpll; + + /*-------------------------------------------------------------------------+ + | Get the system clock period. + +-------------------------------------------------------------------------*/ + sys_per = determine_sysper(); + + msr = (mfmsr () & ~(MSR_EE)); /* disable interrupts */ + + /*-------------------------------------------------------------------------+ + | Calculate the system clock speed from the period. + +-------------------------------------------------------------------------*/ + sys_freq=(ONE_BILLION/sys_per)*1000; +#endif + /* Extract configured divisors */ mfsdr( sdr_sdstp0,strp0 ); mfsdr( sdr_sdstp1,strp1 ); @@ -360,12 +384,238 @@ void get_sys_info (sys_info_t * sysInfo) m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB; /* Now calculate the individual clocks */ +#if defined(CONFIG_440SPE) + sysInfo->freqVCOMhz = (m * sys_freq) ; +#else sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1); +#endif sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0; sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv; +#if defined(CONFIG_440SPE) + /* Determine PCI Clock Period */ + pci_clock_per = determine_pci_clock_per(); + sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000; + mfsdr(sdr_ddr0, sdr_ddrpll); + sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); +#endif + + +} + +#endif + +#if defined(CONFIG_440SPE) +unsigned long determine_sysper(void) +{ + unsigned int fpga_clocking_reg; + unsigned int master_clock_selection; + unsigned long master_clock_per = 0; + unsigned long fb_div_selection; + unsigned int vco_div_reg_value; + unsigned long vco_div_selection; + unsigned long sys_per = 0; + int extClkVal; + + /*-------------------------------------------------------------------------+ + | Read FPGA reg 0 and reg 1 to get FPGA reg information + +-------------------------------------------------------------------------*/ + fpga_clocking_reg = in16(FPGA_REG16); + + + /* Determine Master Clock Source Selection */ + master_clock_selection = fpga_clocking_reg & FPGA_REG16_MASTER_CLK_MASK; + + switch(master_clock_selection) { + case FPGA_REG16_MASTER_CLK_66_66: + master_clock_per = PERIOD_66_66MHZ; + break; + case FPGA_REG16_MASTER_CLK_50: + master_clock_per = PERIOD_50_00MHZ; + break; + case FPGA_REG16_MASTER_CLK_33_33: + master_clock_per = PERIOD_33_33MHZ; + break; + case FPGA_REG16_MASTER_CLK_25: + master_clock_per = PERIOD_25_00MHZ; + break; + case FPGA_REG16_MASTER_CLK_EXT: + if ((extClkVal==EXTCLK_33_33) + && (extClkVal==EXTCLK_50) + && (extClkVal==EXTCLK_66_66) + && (extClkVal==EXTCLK_83)) { + /* calculate master clock period from external clock value */ + master_clock_per=(ONE_BILLION/extClkVal) * 1000; + } else { + /* Unsupported */ + DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__); + hang(); + } + break; + default: + /* Unsupported */ + DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__); + hang(); + break; + } + + /* Determine FB divisors values */ + if ((fpga_clocking_reg & FPGA_REG16_FB1_DIV_MASK) == FPGA_REG16_FB1_DIV_LOW) { + if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW) + fb_div_selection = FPGA_FB_DIV_6; + else + fb_div_selection = FPGA_FB_DIV_12; + } else { + if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW) + fb_div_selection = FPGA_FB_DIV_10; + else + fb_div_selection = FPGA_FB_DIV_20; + } + + /* Determine VCO divisors values */ + vco_div_reg_value = fpga_clocking_reg & FPGA_REG16_VCO_DIV_MASK; + + switch(vco_div_reg_value) { + case FPGA_REG16_VCO_DIV_4: + vco_div_selection = FPGA_VCO_DIV_4; + break; + case FPGA_REG16_VCO_DIV_6: + vco_div_selection = FPGA_VCO_DIV_6; + break; + case FPGA_REG16_VCO_DIV_8: + vco_div_selection = FPGA_VCO_DIV_8; + break; + case FPGA_REG16_VCO_DIV_10: + default: + vco_div_selection = FPGA_VCO_DIV_10; + break; + } + + if (master_clock_selection == FPGA_REG16_MASTER_CLK_EXT) { + switch(master_clock_per) { + case PERIOD_25_00MHZ: + if (fb_div_selection == FPGA_FB_DIV_12) { + if (vco_div_selection == FPGA_VCO_DIV_4) + sys_per = PERIOD_75_00MHZ; + if (vco_div_selection == FPGA_VCO_DIV_6) + sys_per = PERIOD_50_00MHZ; + } + break; + case PERIOD_33_33MHZ: + if (fb_div_selection == FPGA_FB_DIV_6) { + if (vco_div_selection == FPGA_VCO_DIV_4) + sys_per = PERIOD_50_00MHZ; + if (vco_div_selection == FPGA_VCO_DIV_6) + sys_per = PERIOD_33_33MHZ; + } + if (fb_div_selection == FPGA_FB_DIV_10) { + if (vco_div_selection == FPGA_VCO_DIV_4) + sys_per = PERIOD_83_33MHZ; + if (vco_div_selection == FPGA_VCO_DIV_10) + sys_per = PERIOD_33_33MHZ; + } + if (fb_div_selection == FPGA_FB_DIV_12) { + if (vco_div_selection == FPGA_VCO_DIV_4) + sys_per = PERIOD_100_00MHZ; + if (vco_div_selection == FPGA_VCO_DIV_6) + sys_per = PERIOD_66_66MHZ; + if (vco_div_selection == FPGA_VCO_DIV_8) + sys_per = PERIOD_50_00MHZ; + } + break; + case PERIOD_50_00MHZ: + if (fb_div_selection == FPGA_FB_DIV_6) { + if (vco_div_selection == FPGA_VCO_DIV_4) + sys_per = PERIOD_75_00MHZ; + if (vco_div_selection == FPGA_VCO_DIV_6) + sys_per = PERIOD_50_00MHZ; + } + if (fb_div_selection == FPGA_FB_DIV_10) { + if (vco_div_selection == FPGA_VCO_DIV_6) + sys_per = PERIOD_83_33MHZ; + if (vco_div_selection == FPGA_VCO_DIV_10) + sys_per = PERIOD_50_00MHZ; + } + if (fb_div_selection == FPGA_FB_DIV_12) { + if (vco_div_selection == FPGA_VCO_DIV_6) + sys_per = PERIOD_100_00MHZ; + if (vco_div_selection == FPGA_VCO_DIV_8) + sys_per = PERIOD_75_00MHZ; + } + break; + case PERIOD_66_66MHZ: + if (fb_div_selection == FPGA_FB_DIV_6) { + if (vco_div_selection == FPGA_VCO_DIV_4) + sys_per = PERIOD_100_00MHZ; + if (vco_div_selection == FPGA_VCO_DIV_6) + sys_per = PERIOD_66_66MHZ; + if (vco_div_selection == FPGA_VCO_DIV_8) + sys_per = PERIOD_50_00MHZ; + } + if (fb_div_selection == FPGA_FB_DIV_10) { + if (vco_div_selection == FPGA_VCO_DIV_8) + sys_per = PERIOD_83_33MHZ; + if (vco_div_selection == FPGA_VCO_DIV_10) + sys_per = PERIOD_66_66MHZ; + } + if (fb_div_selection == FPGA_FB_DIV_12) { + if (vco_div_selection == FPGA_VCO_DIV_8) + sys_per = PERIOD_100_00MHZ; + } + break; + default: + break; + } + + if (sys_per == 0) { + /* Other combinations are not supported */ + DEBUGF ("%s[%d] *** sys period compute failed ***\n", __FUNCTION__,__LINE__); + hang(); + } + } else { + /* calcul system clock without cheking */ + /* if engineering option clock no check is selected */ + /* sys_per = master_clock_per * vco_div_selection / fb_div_selection */ + sys_per = (master_clock_per/fb_div_selection) * vco_div_selection; + } + + return(sys_per); + +} + +/*-------------------------------------------------------------------------+ +| determine_pci_clock_per. ++-------------------------------------------------------------------------*/ +unsigned long determine_pci_clock_per(void) +{ + unsigned long pci_clock_selection, pci_period; + + /*-------------------------------------------------------------------------+ + | Read FPGA reg 6 to get PCI 0 FPGA reg information + +-------------------------------------------------------------------------*/ + pci_clock_selection = in16(FPGA_REG16); /* was reg6 averifier */ + + + pci_clock_selection = pci_clock_selection & FPGA_REG16_PCI0_CLK_MASK; + + switch (pci_clock_selection) { + case FPGA_REG16_PCI0_CLK_133_33: + pci_period = PERIOD_133_33MHZ; + break; + case FPGA_REG16_PCI0_CLK_100: + pci_period = PERIOD_100_00MHZ; + break; + case FPGA_REG16_PCI0_CLK_66_66: + pci_period = PERIOD_66_66MHZ; + break; + default: + pci_period = PERIOD_33_33MHZ;; + break; + } + + return(pci_period); } #endif diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 647088f721a..699fa7fd752 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -155,6 +155,11 @@ /**************************************************************************/ _start_440: + /*----------------------------------------------------------------+ + | Core bug fix. Clear the esr + +-----------------------------------------------------------------*/ + li r0,0 + mtspr esr,r0 /*----------------------------------------------------------------*/ /* Clear and set up some registers. */ /*----------------------------------------------------------------*/ @@ -166,7 +171,7 @@ _start_440: mtspr srr1,r0 mtspr csrr0,r0 mtspr csrr1,r0 -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) /* NOTE: 440GX adds machine check status regs */ +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* NOTE: 440GX adds machine check status regs */ mtspr mcsrr0,r0 mtspr mcsrr1,r0 mfspr r1, mcsr @@ -200,6 +205,31 @@ _start_440: ori r1,r1,0x6000 /* cache touch */ mtspr ccr0,r1 +#if defined (CONFIG_440SPE) + /*----------------------------------------------------------------+ + | Initialize Core Configuration Reg1. + | a. ICDPEI: Record even parity. Normal operation. + | b. ICTPEI: Record even parity. Normal operation. + | c. DCTPEI: Record even parity. Normal operation. + | d. DCDPEI: Record even parity. Normal operation. + | e. DCUPEI: Record even parity. Normal operation. + | f. DCMPEI: Record even parity. Normal operation. + | g. FCOM: Normal operation + | h. MMUPEI: Record even parity. Normal operation. + | i. FFF: Flush only as much data as necessary. + | j. TCS: Timebase increments from CPU clock. + +-----------------------------------------------------------------*/ + li r0,0 + mtspr ccr1, r0 + + /*----------------------------------------------------------------+ + | Reset the timebase. + | The previous write to CCR1 sets the timebase source. + +-----------------------------------------------------------------*/ + mtspr tbl, r0 + mtspr tbu, r0 +#endif + /*----------------------------------------------------------------*/ /* Setup interrupt vectors */ /*----------------------------------------------------------------*/ @@ -261,15 +291,26 @@ _start_440: mtspr ivlim,r1 mtspr dvlim,r1 + /*----------------------------------------------------------------+ + |Initialize MMUCR[STID] = 0. + +-----------------------------------------------------------------*/ + mfspr r0,mmucr + addis r1,0,0xFFFF + ori r1,r1,0xFF00 + and r0,r0,r1 + mtspr mmucr,r0 + /*----------------------------------------------------------------*/ /* Clear all TLB entries -- TID = 0, TS = 0 */ /*----------------------------------------------------------------*/ - mtspr mmucr,r0 + addis r0,0,0x0000 li r1,0x003f /* 64 TLB entries */ mtctr r1 -0: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ +rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ + tlbwe r0,r1,0x0001 + tlbwe r0,r1,0x0002 subi r1,r1,0x0001 - bdnz 0b + bdnz rsttlb /*----------------------------------------------------------------*/ /* TLB entry setup -- step thru tlbtab */ @@ -377,7 +418,7 @@ _start: addi r3,r3,32 bdnz ..d_ag #else -#if defined (CONFIG_440GX) || defined(CONFIG_440SP) +#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */ #endif mtdcr isram0_sb1cr,r0 /* Disable bank 1 */ @@ -404,6 +445,19 @@ _start: lis r1, 0x8003 ori r1,r1, 0x0980 /* fourth 64k */ mtdcr isram0_sb3cr,r1 +#elif defined(CONFIG_440SPE) + lis r1,0x0000 /* BAS = 0000_0000 */ + ori r1,r1,0x0984 /* first 64k */ + mtdcr isram0_sb0cr,r1 + lis r1,0x0001 + ori r1,r1,0x0984 /* second 64k */ + mtdcr isram0_sb1cr,r1 + lis r1, 0x0002 + ori r1,r1, 0x0984 /* third 64k */ + mtdcr isram0_sb2cr,r1 + lis r1, 0x0003 + ori r1,r1, 0x0984 /* fourth 64k */ + mtdcr isram0_sb3cr,r1 #else ori r1,r1,0x0380 /* 8k rw */ mtdcr isram0_sb0cr,r1 @@ -1197,7 +1251,7 @@ ppcSync: */ .globl relocate_code relocate_code: -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) /* * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) * to speed up the boot process. Now this cache needs to be disabled. @@ -1412,7 +1466,7 @@ trap_init: cmplw 0, r7, r8 blt 4b -#if !defined(CONFIG_440_GX) +#if !defined(CONFIG_440GX) && !defined(CONFIG_440SPE) addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ mtmsr r7 /* change MSR */ diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h index cbfe41db9cc..93cef026a3f 100644 --- a/cpu/ppc4xx/vecnum.h +++ b/cpu/ppc4xx/vecnum.h @@ -31,7 +31,48 @@ #ifndef _VECNUMS_H_ #define _VECNUMS_H_ -#if defined(CONFIG_440SP) +#if defined(CONFIG_440SPE) +/* UIC 0 */ +#define VECNUM_U0 0 /* UART0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_IIC0 2 /* IIC0 */ +#define VECNUM_IIC1 3 /* IIC1 */ +#define VECNUM_PIM 4 /* PCI inbound message */ +#define VECNUM_PCRW 5 /* PCI command reg write */ +#define VECNUM_PPM 6 /* PCI power management */ +#define VECNUM_MSI0 7 /* PCI MSI level 0 */ +#define VECNUM_MSI1 8 /* PCI MSI level 0 */ +#define VECNUM_MSI2 9 /* PCI MSI level 0 */ +#define VECNUM_D0 12 /* DMA channel 0 */ +#define VECNUM_D1 13 /* DMA channel 1 */ +#define VECNUM_D2 14 /* DMA channel 2 */ +#define VECNUM_D3 15 /* DMA channel 3 */ +#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ + +/* UIC 1 */ +#define VECNUM_MS (32 + 1 ) /* MAL SERR */ +#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */ +#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */ +#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */ +#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */ +#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */ +#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */ +#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */ +#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */ +#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */ +#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ +#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ + +/* UIC 2 */ +#define VECNUM_EIR5 (62 + 24) /* External interrupt 5 */ +#define VECNUM_EIR4 (62 + 25) /* External interrupt 4 */ +#define VECNUM_EIR3 (62 + 26) /* External interrupt 3 */ +#define VECNUM_EIR2 (62 + 27) /* External interrupt 2 */ +#define VECNUM_EIR1 (62 + 28) /* External interrupt 1 */ +#define VECNUM_EIR0 (62 + 29) /* External interrupt 0 */ + +#elif defined(CONFIG_440SP) /* UIC 0 */ #define VECNUM_U0 0 /* UART0 */ |