diff options
Diffstat (limited to 'doc')
28 files changed, 482 insertions, 582 deletions
diff --git a/doc/board/coolpi/genbook_cm5_rk3588.rst b/doc/board/coolpi/genbook_cm5_rk3588.rst index a02e561051a..cad2a28acbd 100644 --- a/doc/board/coolpi/genbook_cm5_rk3588.rst +++ b/doc/board/coolpi/genbook_cm5_rk3588.rst @@ -6,6 +6,7 @@ Cool Pi GenBook is a laptop powered by RK3588, it works with a carrier board connect with CM5. Specification: + * Rockchip RK3588 * LPDDR5X 8/32 GB * eMMC 64 GB @@ -24,11 +25,11 @@ Get the TF-A and DDR init (TPL) binaries .. prompt:: bash - > cd u-boot - > export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin - > export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.46.elf - > make coolpi-genbook-cm5-rk3588_defconfig - > make CROSS_COMPILE=aarch64-linux-gnu- + cd u-boot + export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin + export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.46.elf + make coolpi-genbook-cm5-rk3588_defconfig + make CROSS_COMPILE=aarch64-linux-gnu- This will build ``u-boot-rockchip.bin`` for eMMC and ``u-boot-rockchip-spi.bin`` for SPI Nor. diff --git a/doc/board/index.rst b/doc/board/index.rst index b54c1748d57..b1c470eb2cb 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -55,6 +55,7 @@ Board-specific doc sipeed/index socionext/index sophgo/index + spacemit/index st/index starfive/index ste/index diff --git a/doc/board/kontron/sl28.rst b/doc/board/kontron/sl28.rst index 2cb8ec62be4..5d47ce6c158 100644 --- a/doc/board/kontron/sl28.rst +++ b/doc/board/kontron/sl28.rst @@ -65,12 +65,14 @@ wdt command flags The `wdt start` as well as the `wdt expire` command take a flags argument. The supported bitmask is as follows. -| Bit | Description | -| --- | ----------------------------- | -| 0 | Enable failsafe mode | -| 1 | Lock the control register | -| 2 | Disable board reset | -| 3 | Enable WDT_TIME_OUT# line | +=== ============================== +Bit Description +=== ============================== + 0 Enable failsafe mode + 1 Lock the control register + 2 Disable board reset + 3 Enable WDT_TIME_OUT# line +=== ============================== For example, you can use `wdt expire 1` to issue a reset and boot into the failsafe bootloader. diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst index fa306974645..1ae30c2dcd5 100644 --- a/doc/board/phytec/index.rst +++ b/doc/board/phytec/index.rst @@ -9,6 +9,7 @@ PHYTEC imx8mm-phygate-tauri-l imx93-phycore phycore-am62x + phycore-am62ax phycore-am64x phycore-imx8mm phycore-imx8mp diff --git a/doc/board/phytec/phycore-am62ax.rst b/doc/board/phytec/phycore-am62ax.rst new file mode 100644 index 00000000000..0c5b4814fc2 --- /dev/null +++ b/doc/board/phytec/phycore-am62ax.rst @@ -0,0 +1,183 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Garrett Giordano <ggiordano@phytec.com> + +phyCORE-AM62Ax +============== + +The `phyCORE-AM62Ax <https://www.phytec.com/product/phycore-am62a>`_ is a +SoM (System on Module) featuring TI's AM62Ax SoC. It can be used in combination +with different carrier boards. This module can come with different sizes and +models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM62Ax family. + +A development Kit, called `phyBOARD-Lyra <https://www.phytec.com/product/phyboard-am62x>`_ +is used as a carrier board reference design around the AM62Ax SoM. + +Quickstart +---------- + +* Download sources and TI firmware blobs +* Build Trusted Firmware-A +* Build OP-TEE +* Build U-Boot for the R5 +* Build U-Boot for the A53 +* Create bootable uSD Card +* Boot + +Sources +------- + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_boot_sources + :end-before: .. k3_rst_include_end_boot_sources + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares + :end-before: .. k3_rst_include_end_tifsstub + +Build procedure +--------------- + +Setup the environment variables: + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_common_env_vars_desc + :end-before: .. k3_rst_include_end_common_env_vars_desc + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_board_env_vars_desc + :end-before: .. k3_rst_include_end_board_env_vars_desc + +Set the variables corresponding to this platform: + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_common_env_vars_defn + :end-before: .. k3_rst_include_end_common_env_vars_defn +.. code-block:: bash + + $ export UBOOT_CFG_CORTEXR=phycore_am62ax_r5_defconfig + $ export UBOOT_CFG_CORTEXA=phycore_am62ax_a53_defconfig + $ export TFA_BOARD=lite + $ # we dont use any extra TFA parameters + $ unset TFA_EXTRA_ARGS + $ export OPTEE_PLATFORM=k3-am62ax + $ # we dont use any extra OPTEE parameters + $ unset OPTEE_EXTRA_ARGS + +1. Trusted Firmware-A: + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_build_steps_tfa + :end-before: .. k3_rst_include_end_build_steps_tfa + +2. OP-TEE: + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_build_steps_optee + :end-before: .. k3_rst_include_end_build_steps_optee + +3. U-Boot: + +* 3.1 R5: + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_build_steps_spl_r5 + :end-before: .. k3_rst_include_end_build_steps_spl_r5 + +* 3.2 A53: + +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_build_steps_uboot + :end-before: .. k3_rst_include_end_build_steps_uboot + +uSD Card creation +----------------- + +Use fdisk to partition the uSD card. The layout should look similar to: + +.. code-block:: bash + + $ sudo fdisk -l /dev/mmcblk0 + Disk /dev/mmcblk0: 15 GB, 15913189376 bytes, 31080448 sectors + 242816 cylinders, 4 heads, 32 sectors/track + Units: sectors of 1 * 512 = 512 bytes + + Device Boot StartCHS EndCHS StartLBA EndLBA Sectors Size Id Type + /dev/mmcblk0p1 * 128,0,1 1023,3,32 16384 278527 262144 128M c Win95 FAT32 (LBA) + /dev/mmcblk0p2 1023,3,32 1023,3,32 278528 1693883 1415356 691M 83 Linux + + +Once partitioned, the boot partition has to be formatted with a FAT filesystem. +Assuming the uSD card is `/dev/mmcblk0`: + +.. code-block:: bash + + $ mkfs.vfat /dev/mmcblk0p1 + +To boot from a micro SD card on a HSFS device simply copy the following +artifacts to the FAT partition: + +* tiboot3.bin from R5 build +* tispl.bin from Cortex-A build +* u-boot.img from Cortex-A build + +Boot +---- + +Put the uSD card in the slot on the board and apply power. Check the serial +console for output. + +UART based boot +--------------- + +To boot the board via UART, set the switches to UART mode and connect to the +micro USB port labeled as "Debug UART". After power-on the build artifacts +needs to be uploaded one by one with a tool like sz. + +Example bash script sequence for running on a Linux host PC feeding all boot +artifacts needed to the device. Assuming the host uses /dev/ttyUSB0 as +the main domain serial port: + +.. prompt:: bash $ + + stty -F /dev/ttyUSB0 115200 + sb --xmodem tiboot3.bin > /dev/ttyUSB0 < /dev/ttyUSB0 + sb --ymodem tispl.bin > /dev/ttyUSB0 < /dev/ttyUSB0 + sb --ymodem u-boot.img > /dev/ttyUSB0 < /dev/ttyUSB0 + +Boot Modes +---------- + +The phyCORE-AM62x development kit supports booting from many different +interfaces. By default, the development kit is set to boot from the micro-SD +card. To change the boot device, DIP switches S5 and S6 can be used. +Boot switches should be changed with power off. + +.. list-table:: Boot Modes + :widths: 16 16 16 + :header-rows: 1 + + * - Switch Label + - SW5: 12345678 + - SW6: 12345678 + + * - uSD + - 11000010 + - 01000000 + + * - eMMC + - 11010010 + - 00000000 + + * - OSPI + - 11010000 + - 10000000 + + * - UART + - 11011100 + - 00000000 + +Further Information +------------------- + +Please see :doc:`../ti/am62ax_sk` chapter for further AM62Ax SoC related documentation +and https://docs.phytec.com/projects/yocto-phycore-am62ax/en/latest/ for vendor documentation. diff --git a/doc/board/sophgo/index.rst b/doc/board/sophgo/index.rst index e097afdac64..26dba4a4851 100644 --- a/doc/board/sophgo/index.rst +++ b/doc/board/sophgo/index.rst @@ -6,3 +6,4 @@ Sophgo :maxdepth: 1 milkv_duo + licheerv_nano diff --git a/doc/board/sophgo/licheerv_nano.rst b/doc/board/sophgo/licheerv_nano.rst new file mode 100644 index 00000000000..a75c6a37dc5 --- /dev/null +++ b/doc/board/sophgo/licheerv_nano.rst @@ -0,0 +1,72 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +LicheeRV Nano +============= + +SG2002 RISC-V SoC +----------------- +The SG2002 is a high-performance, low-power 64-bit RISC-V/ARM SoC from Sophgo. + +Mainline support +---------------- +The support for following drivers are already enabled: +1. ns16550 UART Driver. +2. Synopsys Designware MSHC Driver + +Building +~~~~~~~~ +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: console + + export CROSS_COMPILE=<riscv64 toolchain prefix> + cd <U-Boot-dir> + make sipeed_licheerv_nano_defconfig + make + +This will generate u-boot.bin + +Booting +~~~~~~~ +Currently, we rely on vendor FSBL (First Stage Boot Loader) to initialize the +clock and load the u-boot image, then bootup from it. + +To run u-boot.bin on top of FSBL, follow these steps: + +1. Use mainline OpenSBI with a newer version than 1.5 to generate fw_dynamic. + +2. Generate a compatible u-boot.bin using U-Boot with the LicheeRV Nano default + configuration. + +3. Use the vendor-provided tool [1] to create a unified fip.bin file containing + FSBL, OpenSBI, and U-Boot. + Note that you will have to use the file cv181x.bin as the FSBL. + +2. Place the generated fip.bin file into the FAT partition of the SD card. + +3. Insert the SD card into the board and power it on. + +The board will automatically execute the FSBL from the fip.bin file. +Subsequently, it will transition to OpenSBI, and finally, OpenSBI will invoke +U-Boot. + +[1]: https://github.com/sophgo/fiptool + + +Sample boot log from LicheeRV Nano board +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. code-block:: none + + U-Boot 2024.10 (Oct 24 2024 - 15:00:20 +0200)licheerv_nano + + DRAM: 256 MiB + Core: 19 devices, 11 uclasses, devicetree: separate + MMC: mmc@4310000: 0 + Loading Environment from nowhere... OK + In: serial@4140000 + Out: serial@4140000 + Err: serial@4140000 + Net: No ethernet found. + Hit any key to stop autoboot: 0 + licheerv_nano# diff --git a/doc/board/spacemit/bananapi-f3.rst b/doc/board/spacemit/bananapi-f3.rst new file mode 100644 index 00000000000..f2220950a3a --- /dev/null +++ b/doc/board/spacemit/bananapi-f3.rst @@ -0,0 +1,106 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Banana Pi BPI-F3 +================ + +Building +~~~~~~~~ +1. Install the SpacemiT riscv cross compile toolchain_, or skip it if riscv toolchain is installed. + +.. _toolchain: https://archive.spacemit.com/toolchain/ + +2. Setup cross compilation environment variable: + +.. code-block:: console + + export CROSS_COMPILE=<riscv64 toolchain prefix, e.g /opt/spacemit/bin/riscv64-unknown-linux-gnu-> + +3. Before building U-Boot, OpenSBI should be built first. OpenSBI can be +built for SpacemiT K1 SoC as below: + +.. code-block:: console + + git clone https://github.com/cyyself/opensbi -b k1-opensbi + cd opensbi + make PLATFORM=generic + +4. Then build U-Boot as following: + +.. code-block:: console + + cd <U-Boot-dir> + make bananapi-f3_defconfig + make OPENSBI=<OpenSBI-dir>/build/platform/generic/firmware/fw_dynamic.bin + +This will generate u-boot.itb + +Burning +~~~~~~~ +Actually, we can replace the uboot partition of Bianbu Linux which is the bsp_ to validate this patch, +use `balena etcher` to burn the bianbu-minimal.img to the sd card, +and replace the /dev/sdx4 where places the uboot_ with the `u-boot.itb` generated from this patch. +Or use fastboot: +Collect FSBL.bin, u-boot.itb, partition_2M.json, bootinfo_spinor.bin +u-boot-env-default.bin, fw_dynamic.itb from vendor SDK + +.. code-block:: console + + fastboot stage FSBL.bin + fastboot continue + fastboot stage u-boot.itb-vendor # the itb from vendor uboot + fastboot continue + + fastboot flash mtd partition_2M.json + fastboot flash bootinfo bootinfo_spinor.bin + fastboot flash fsbl FSBL.bin + fastboot flash env u-boot-env-default.bin + fastboot flash opensbi fw_dynamic.itb + + fastboot flash uboot u-boot.itb-mainline # the itb from mainline uboot + +.. _bsp: https://archive.spacemit.com/image/k1/version/bianbu/v2.0/ +.. _uboot: https://bianbu-linux.spacemit.com/en/device/boot#21-firmware-layout + +Booting +~~~~~~~ +Sample boot log from Banana Pi BPI-F3 board +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. code-block:: none + + try sd... + bm:3 + j... + + U-Boot SPL 2022.10spacemit-dirty (Oct 21 2024 - 09:01:13 +0000) + [ 0.279] DDR type LPDDR4X + [ 0.292] lpddr4_silicon_init consume 13ms + [ 0.293] Change DDR data rate to 2400MT/s + [ 0.430] ## Checking hash(es) for config conf-1 ... OK + [ 0.432] ## Checking hash(es) for Image opensbi ... OK + [ 0.437] ## Checking hash(es) for Image uboot ... OK + [ 0.443] ## Checking hash(es) for Image fdt-1 ... OK + [ 0.488] ## Checking hash(es) for config config_1 ... OK + [ 0.490] ## Checking hash(es) for Image opensbi ... crc32+ OK + + + U-Boot 2024.10-rc4-00462-g5b138cfcc587-dirty (Nov 28 2024 - 14:56:49 +0800) + + DRAM: 4 GiB + Core: 19 devices, 8 uclasses, devicetree: separate + Loading Environment from nowhere... OK + In: serial@d4017000 + Out: serial@d4017000 + Err: serial@d4017000 + Net: No ethernet found. + => cpu list + 0: cpu@0 spacemit,x60 + 1: cpu@1 spacemit,x60 + 2: cpu@2 spacemit,x60 + 3: cpu@3 spacemit,x60 + 4: cpu@4 spacemit,x60 + 5: cpu@5 spacemit,x60 + 6: cpu@6 spacemit,x60 + 7: cpu@7 spacemit,x60 + => test + => + diff --git a/doc/board/spacemit/index.rst b/doc/board/spacemit/index.rst new file mode 100644 index 00000000000..e7d3d94e459 --- /dev/null +++ b/doc/board/spacemit/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +SpacemiT +======== +.. toctree:: + :maxdepth: 1 + + bananapi-f3 + diff --git a/doc/board/theobroma-systems/puma_rk3399.rst b/doc/board/theobroma-systems/puma_rk3399.rst index 5bc6385e451..a2a5e7bca4b 100644 --- a/doc/board/theobroma-systems/puma_rk3399.rst +++ b/doc/board/theobroma-systems/puma_rk3399.rst @@ -27,6 +27,7 @@ RK3399-Q7 features: * Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF) * NOR Flash: onboard SPI NOR * Companion Controller: onboard additional Cortex-M0 microcontroller + * RTC * fan controller * CAN diff --git a/doc/board/theobroma-systems/tiger_rk3588.rst b/doc/board/theobroma-systems/tiger_rk3588.rst index a73eec7fb9b..46112544c82 100644 --- a/doc/board/theobroma-systems/tiger_rk3588.rst +++ b/doc/board/theobroma-systems/tiger_rk3588.rst @@ -8,6 +8,7 @@ connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3588. It provides the following feature set: + * up to 16GB LPDDR4x * on-module eMMC * SD card (on a baseboard) via edge connector @@ -18,14 +19,20 @@ It provides the following feature set: * HDMI input over FPC connector * CAN * USB + - 1x USB 3.0 dual-role (direct connection) - 2x USB 3.0 host + 1x USB 2.0 host + * PCIe + - 1x PCIe 2.1 Gen3, 4 lanes - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes + * on-module ATtiny816 companion controller, implementing: + - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) + * on-module Secure Element with Global Platform 2.2.1 compliant JavaCard environment diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 5d01f487622..0deb4d768f9 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -46,6 +46,7 @@ K3 SoC based boards in other sections * :doc:`../beagle/am62x_beagleplay` * :doc:`../beagle/j721e_beagleboneai64` * :doc:`../phytec/phycore-am62x` +* :doc:`../phytec/phycore-am62ax` * :doc:`../toradex/verdin-am62` Boot Flow Overview diff --git a/doc/build/docker.rst b/doc/build/docker.rst index 5896dd5ac4a..01ed3505090 100644 --- a/doc/build/docker.rst +++ b/doc/build/docker.rst @@ -4,21 +4,29 @@ GitLab CI / U-Boot runner container In order to have a reproducible and portable build environment for CI we use a container for building in. This means that developers can also reproduce the CI environment, to a large degree at least, locally. This file is located in the tools/docker directory. The docker image supports both amd64 and arm64. Ensure that the -'docker-buildx' Debian package is installed (or the equivalent on another -distribution). +`buildx` Docker CLI plugin is installed. This is often available in your +distribution via the 'docker-buildx' or 'docker-buildx-plugin' package. You will need a multi-platform container, otherwise this error is shown:: ERROR: Multi-platform build is not supported for the docker driver. Switch to a different driver, or turn on the containerd image store, and try again. -You can add one with:: +You can add a simple one with:: sudo docker buildx create --name multiarch --driver docker-container --use -Building is supported on both amd64 (i.e. 64-bit x86) and arm64 machines. While -both amd64 and arm64 happen in parallel, the non-native part will take -considerably longer as it must use QEMU to emulate the foreign code. +This will result in a builder that will use QEMU for the non-native +architectures request in a build. While both amd64 and arm64 happen in +parallel, the non-native part will take considerably longer as it must use QEMU +to emulate the foreign code. An alternative, if you have accesss to reasonably +fast amd64 (i.e. 64-bit x86) and arm64 machines is:: + + sudo docker buildx create --name multiarch-multinode --node localNode --bootstrap --use + sudo docker buildx create --name multiarch-multinode --append --node remoteNode --bootstrap ssh://user@host + +And this will result in a builder named multiarch-multinode that will build +each platform natively on each node. To build the image yourself:: diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 9f9252b18d2..449d0375a1b 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -75,9 +75,9 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2025.01-rc4 was released on Mon 09 December 2024. -.. * U-Boot v2025.01-rc5 was released on Mon 23 December 2024. +* U-Boot v2025.01-rc5 was released on Mon 23 December 2024. -.. * U-Boot v2025.01-rc6 was released on Mon 30 December 2024. +* U-Boot v2025.01-rc6 was released on Mon 30 December 2024. Please note that the following dates are planned only and may be deviated from as needed. diff --git a/doc/develop/sending_patches.rst b/doc/develop/sending_patches.rst index e22b5e3e244..ee6e34089b5 100644 --- a/doc/develop/sending_patches.rst +++ b/doc/develop/sending_patches.rst @@ -377,7 +377,7 @@ The following are a "rule of thumb" as to how the states are used in patchwork today. Not all states are used by all custodians. * New: Patch has been submitted to the list, and none of the maintainers has - changed it's state since. + changed its state since. * Under Review: A custodian is reviewing the patch currently. diff --git a/doc/develop/trace.rst b/doc/develop/trace.rst index 546862020b1..d3c8628d124 100644 --- a/doc/develop/trace.rst +++ b/doc/develop/trace.rst @@ -163,6 +163,17 @@ you will see the time taken by each function shown against its exit record. u-boot-1 [000] 3.116466: funcgraph_entry: 0.063 us | memset(); u-boot-1 [000] 3.116539: funcgraph_exit: 0.143 us | } +The `trace wipe` command may be used to clear the trace buffer. It leaves +tracing in its current enable state. This command is convenient when tracing a +single command, for example: + +.. code-block:: console + + => trace pause; trace wipe + => trace resume; dhcp; trace pause + => trace stats + ... + Flame graph ----------- diff --git a/doc/develop/uefi/fwu_updates.rst b/doc/develop/uefi/fwu_updates.rst index 51e8a28efe1..84713581459 100644 --- a/doc/develop/uefi/fwu_updates.rst +++ b/doc/develop/uefi/fwu_updates.rst @@ -170,7 +170,7 @@ build the tool, enable:: CONFIG_TOOLS_MKEFICAPSULE=y -Run the following commands to generate the accept/revert capsules:: +Run the following commands to generate the accept/revert capsules: .. code-block:: bash @@ -180,7 +180,7 @@ Run the following commands to generate the accept/revert capsules:: <capsule_file_name> Some examples of using the mkeficapsule tool for generation of the -empty capsule would be:: +empty capsule would be: .. code-block:: bash diff --git a/doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt b/doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt deleted file mode 100644 index 0c2bf5eba43..00000000000 --- a/doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3188/RK3066 Clock and Reset Unit - -The RK3188/RK3066 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or - "rockchip,rk3066a-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3188-cru.h and -dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. -Similar macros exist for the reset sources in these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "xin27m" - 27mhz crystal input on rk3066 - optional, - - "ext_hsadc" - external HSADC clock - optional, - - "ext_cif0" - external camera clock - optional, - - "ext_rmii" - external RMII clock - optional, - - "ext_jtag" - externalJTAG clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt b/doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt deleted file mode 100644 index c9fbb76573e..00000000000 --- a/doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3288 Clock and Reset Unit - -The RK3288 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3288-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_hsadc" - external HSADC clock - optional, - - "ext_edp_24m" - external display port clock - optional, - - "ext_vip" - external VIP clock - optional, - - "ext_isp" - external ISP clock - optional, - - "ext_jtag" - external JTAG clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/doc/device-tree-bindings/clock/rockchip.txt b/doc/device-tree-bindings/clock/rockchip.txt deleted file mode 100644 index 22f6769e5d4..00000000000 --- a/doc/device-tree-bindings/clock/rockchip.txt +++ /dev/null @@ -1,77 +0,0 @@ -Device Tree Clock bindings for arch-rockchip - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -== Gate clocks == - -These bindings are deprecated! -Please use the soc specific CRU bindings instead. - -The gate registers form a continuos block which makes the dt node -structure a matter of taste, as either all gates can be put into -one gate clock spanning all registers or they can be divided into -the 10 individual gates containing 16 clocks each. -The code supports both approaches. - -Required properties: -- compatible : "rockchip,rk2928-gate-clk" -- reg : shall be the control register address(es) for the clock. -- #clock-cells : from common clock binding; shall be set to 1 -- clock-output-names : the corresponding gate names that the clock controls -- clocks : should contain the parent clock for each individual gate, - therefore the number of clocks elements should match the number of - clock-output-names - -Example using multiple gate clocks: - - clk_gates0: gate-clk@200000d0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d0 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_core_periph", "gate_cpu_gpll", - "gate_ddrphy", "gate_aclk_cpu", - "gate_hclk_cpu", "gate_pclk_cpu", - "gate_atclk_cpu", "gate_i2s0", - "gate_i2s0_frac", "gate_i2s1", - "gate_i2s1_frac", "gate_i2s2", - "gate_i2s2_frac", "gate_spdif", - "gate_spdif_frac", "gate_testclk"; - - #clock-cells = <1>; - }; - - clk_gates1: gate-clk@200000d4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d4 0x4>; - clocks = <&xin24m>, <&xin24m>, - <&xin24m>, <&dummy>, - <&dummy>, <&xin24m>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_timer0", "gate_timer1", - "gate_timer2", "gate_jtag", - "gate_aclk_lcdc1_src", "gate_otgphy0", - "gate_otgphy1", "gate_ddr_gpll", - "gate_uart0", "gate_frac_uart0", - "gate_uart1", "gate_frac_uart1", - "gate_uart2", "gate_frac_uart2", - "gate_uart3", "gate_frac_uart3"; - - #clock-cells = <1>; - }; diff --git a/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt b/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt deleted file mode 100644 index 388b213249f..00000000000 --- a/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt +++ /dev/null @@ -1,157 +0,0 @@ -* Rockchip Pinmux Controller - -The Rockchip Pinmux Controller, enables the IC -to share one PAD to several functional blocks. The sharing is done by -multiplexing the PAD input/output signals. For each PAD there are several -muxing options with option 0 being the use as a GPIO. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The Rockchip pin configuration node is a node of a group of pins which can be -used for a specific device or function. This node represents both mux and -config of the pins in that group. The 'pins' selects the function mode(also -named pin mode) this pin can work on and the 'config' configures various pad -settings such as pull-up, etc. - -The pins are grouped into up to 5 individual pin banks which need to be -defined as gpio sub-nodes of the pinmux controller. - -Required properties for iomux controller: - - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" - "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" - "rockchip,rk3288-pinctrl" - - rockchip,grf: phandle referencing a syscon providing the - "general register files" - -Optional properties for iomux controller: - - rockchip,pmu: phandle referencing a syscon providing the pmu registers - as some SoCs carry parts of the iomux controller registers there. - Required for at least rk3188 and rk3288. - -Deprecated properties for iomux controller: - - reg: first element is the general register space of the iomux controller - It should be large enough to contain also separate pull registers. - second element is the separate pull register space of the rk3188. - Use rockchip,grf and rockchip,pmu described above instead. - -Required properties for gpio sub nodes: - - compatible: "rockchip,gpio-bank" - - reg: register of the gpio bank (different than the iomux registerset) - - interrupts: base interrupt of the gpio bank in the interrupt controller - - clocks: clock that drives this bank - - gpio-controller: identifies the node as a gpio controller and pin bank. - - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See generic - GPIO binding documentation for description of particular cells. - - interrupt-controller: identifies the controller node as interrupt-parent. - - #interrupt-cells: the value of this property should be 2 and the interrupt - cells should use the standard two-cell scheme described in - bindings/interrupt-controller/interrupts.txt - -Deprecated properties for gpio sub nodes: - - compatible: "rockchip,rk3188-gpio-bank0" - - reg: second element: separate pull register for rk3188 bank0, use - rockchip,pmu described above instead - -Required properties for pin configuration node: - - rockchip,pins: 3 integers array, represents a group of pins mux and config - setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>. - The MUX 0 means gpio and MUX 1 to N mean the specific device function. - The phandle of a node containing the generic pinconfig options - to use, as described in pinctrl-bindings.txt in this directory. - -Examples: - -#include <dt-bindings/pinctrl/rockchip.h> - -... - -pinctrl@20008000 { - compatible = "rockchip,rk3066a-pinctrl"; - rockchip,grf = <&grf>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20034000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20034000 0x100>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 9>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - ... - - pcfg_pull_default: pcfg_pull_default { - bias-pull-pin-default - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>, - <RK_GPIO1 9 1 &pcfg_pull_default>; - }; - }; -}; - -uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&mux_uart2>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; - -Example for rk3188: - - pinctrl@20008000 { - compatible = "rockchip,rk3188-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@0x2000a000 { - compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 9>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@0x2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_gates8 10>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - ... - - }; diff --git a/doc/device-tree-bindings/thermal/rockchip-thermal.txt b/doc/device-tree-bindings/thermal/rockchip-thermal.txt deleted file mode 100644 index ef802de4957..00000000000 --- a/doc/device-tree-bindings/thermal/rockchip-thermal.txt +++ /dev/null @@ -1,68 +0,0 @@ -* Temperature Sensor ADC (TSADC) on rockchip SoCs - -Required properties: -- compatible : "rockchip,rk3288-tsadc" -- reg : physical base address of the controller and length of memory mapped - region. -- interrupts : The interrupt number to the cpu. The interrupt specifier format - depends on the interrupt controller. -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for - the peripheral clock. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the name "tsadc-apb". -- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. -- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value. -- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO. -- rockchip,hw-tshut-polarity : The hardware-controlled active polarity 0:LOW - 1:HIGH. - -Exiample: -tsadc: tsadc@ff280000 { - compatible = "rockchip,rk3288-tsadc"; - reg = <0xff280000 0x100>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "default"; - pinctrl-0 = <&otp_out>; - #thermal-sensor-cells = <1>; - rockchip,hw-tshut-temp = <95000>; - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; -}; - -Example: referring to thermal sensors: -thermal-zones { - cpu_thermal: cpu_thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tsadc 1>; - - trips { - cpu_alert0: cpu_alert { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; diff --git a/doc/device-tree-bindings/usb/dwc2.txt b/doc/device-tree-bindings/usb/dwc2.txt index 61493f7cb0c..7a533f65934 100644 --- a/doc/device-tree-bindings/usb/dwc2.txt +++ b/doc/device-tree-bindings/usb/dwc2.txt @@ -5,10 +5,6 @@ Required properties: - compatible : One of: - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC. - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC. - - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc; - - "rockchip,px30-usb", "rockchip,rk3066-usb", "snps,dwc2": for px30 Soc; - - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc; - - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc; - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs; - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs; - "amlogic,meson8-usb": The DWC2 USB controller instance in Amlogic Meson8 SoCs; diff --git a/doc/device-tree-bindings/video/rockchip-lvds.txt b/doc/device-tree-bindings/video/rockchip-lvds.txt deleted file mode 100644 index 7432e221669..00000000000 --- a/doc/device-tree-bindings/video/rockchip-lvds.txt +++ /dev/null @@ -1,77 +0,0 @@ -Rockchip LVDS interface ------------------- - -Required properties: -- compatible: "rockchip,rk3288-lvds"; - -- reg: physical base address of the controller and length - of memory mapped region. -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. -- clock-names: must contain "pclk_lvds" - -- rockchip,grf: phandle to the general register files syscon - -- rockchip,data-mapping: should be <LVDS_FORMAT_VESA> or <LVDS_FORMAT_JEIDA>, - This describes how the color bits are laid out in the - serialized LVDS signal. -- rockchip,data-width : should be <18> or <24>; -- rockchip,output: should be <LVDS_OUTPUT_RGB>, <LVDS_OUTPUT_SINGLE> or - <LVDS_OUTPUT_DUAL>, This describes the output face. - -- display-timings : described by - doc/device-tree-bindings/video/display-timing.txt. - -Example: - lvds: lvds@ff96c000 { - compatible = "rockchip,rk3288-lvds"; - reg = <0xff96c000 0x4000>; - clocks = <&cru PCLK_LVDS_PHY>; - clock-names = "pclk_lvds"; - pinctrl-names = "default"; - pinctrl-0 = <&lcdc0_ctl>; - rockchip,grf = <&grf>; - status = "disabled"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - lvds_in: port@0 { - reg = <0>; - - #address-cells = <1>; - #size-cells = <0>; - - lvds_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_lvds>; - }; - lvds_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_lvds>; - }; - }; - }; - }; - - &lvds { - rockchip,data-mapping = <LVDS_FORMAT_VESA>; - rockchip,data-width = <24>; - rockchip,output = <LVDS_OUTPUT_DUAL>; - rockchip,panel = <&panel>; - status = "okay"; - - display-timings { - timing@0 { - clock-frequency = <40000000>; - hactive = <1920>; - vactive = <1080>; - hsync-len = <44>; - hfront-porch = <88>; - hback-porch = <148>; - vfront-porch = <4>; - vback-porch = <36>; - vsync-len = <5>; - }; - }; - }; diff --git a/doc/imx/habv4/introduction_habv4.txt b/doc/imx/habv4/introduction_habv4.txt index 25711bbe95a..a2f2d836911 100644 --- a/doc/imx/habv4/introduction_habv4.txt +++ b/doc/imx/habv4/introduction_habv4.txt @@ -240,16 +240,14 @@ root of trust is established and the HAB code can progress with the image authentication. The srktool can be used for generating the SRK Table and its respective SRK -Table Hash. +Table Hash (certificate filenames must be separated by ',' without spaces). - Generating SRK Table and SRK Hash in Linux 64-bit machines: + $ CA_CRT="sha256_2048_65537_v3_ca_crt.pem" $ ../linux64/bin/srktool -h 4 -t SRK_1_2_3_4_table.bin -e \ SRK_1_2_3_4_fuse.bin -d sha256 -c \ - SRK1_sha256_2048_65537_v3_ca_crt.pem,\ - SRK2_sha256_2048_65537_v3_ca_crt.pem,\ - SRK3_sha256_2048_65537_v3_ca_crt.pem,\ - SRK4_sha256_2048_65537_v3_ca_crt.pem + SRK1_"$CA_CRT",SRK2_"$CA_CRT",SRK3_"$CA_CRT",SRK4_"$CA_CRT" The SRK_1_2_3_4_table.bin and SRK_1_2_3_4_fuse.bin files can be used in further steps as explained in HAB guides available under doc/imx/habv4/guides/ diff --git a/doc/usage/cmd/rng.rst b/doc/usage/cmd/rng.rst index 4a61e33d272..c071f01e841 100644 --- a/doc/usage/cmd/rng.rst +++ b/doc/usage/cmd/rng.rst @@ -12,14 +12,14 @@ Synopsis :: rng list - rng [dev] [n] + rng [dev [n]] rng list -------- List all the probed rng devices. -rng [dev] [n] +rng [dev [n]] ------------- The *rng* command reads the random number generator(RNG) device and diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index 7bd9ffce8d8..30fc16794fc 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -499,12 +499,12 @@ Automatically updated variables ------------------------------- The following environment variables may be used and automatically -updated by the network boot commands ("bootp" and "rarpboot"), +updated by the network boot commands ("bootp", "dhcp" and "rarpboot"), depending the information provided by your boot server: -========= =================================================== +========== =================================================================== Variable Notes -========= =================================================== +========== =================================================================== bootfile see above dnsip IP address of your Domain Name Server dnsip2 IP address of your secondary Domain Name Server @@ -514,7 +514,10 @@ ipaddr See above netmask Subnet Mask rootpath Pathname of the root filesystem on the NFS server serverip see above -========= =================================================== +ipaddrN IP address for interface N (>0) (NET_LWIP dhcp only) +netmaskN Subnet mask for interface N (>0) (NET_LWIP dhcp only) +gatewayipN IP address of the Gateway for interface N (>0) (NET_LWIP dhcp only) +========== =================================================================== Special environment variables diff --git a/doc/usage/fit/kernel_fdt.rst b/doc/usage/fit/kernel_fdt.rst index 9cc26fb7831..3802c8292d6 100644 --- a/doc/usage/fit/kernel_fdt.rst +++ b/doc/usage/fit/kernel_fdt.rst @@ -5,50 +5,50 @@ Single kernel and FDT blob :: - /dts-v1/; + /dts-v1/; - / { - description = "Simple image with single Linux kernel and FDT blob"; - #address-cells = <1>; + / { + description = "Simple image with single Linux kernel and FDT blob"; + #address-cells = <1>; - images { - kernel { - description = "Vanilla Linux kernel"; - data = /incbin/("./vmlinux.bin.gz"); - type = "kernel"; - arch = "ppc"; - os = "linux"; - compression = "gzip"; - load = <00000000>; - entry = <00000000>; - hash-1 { - algo = "crc32"; - }; - hash-2 { - algo = "sha256"; - }; - }; - fdt-1 { - description = "Flattened Device Tree blob"; - data = /incbin/("./target.dtb"); - type = "flat_dt"; - arch = "ppc"; - compression = "none"; - hash-1 { - algo = "crc32"; - }; - hash-2 { - algo = "sha256"; - }; - }; - }; + images { + kernel { + description = "Vanilla Linux kernel"; + data = /incbin/("./vmlinux.bin.gz"); + type = "kernel"; + arch = "ppc"; + os = "linux"; + compression = "gzip"; + load = <00000000>; + entry = <00000000>; + hash-1 { + algo = "crc32"; + }; + hash-2 { + algo = "sha256"; + }; + }; + fdt-1 { + description = "Flattened Device Tree blob"; + data = /incbin/("./target.dtb"); + type = "flat_dt"; + arch = "ppc"; + compression = "none"; + hash-1 { + algo = "crc32"; + }; + hash-2 { + algo = "sha256"; + }; + }; + }; - configurations { - default = "conf-1"; - conf-1 { - description = "Boot Linux kernel with FDT blob"; - kernel = "kernel"; - fdt = "fdt-1"; - }; - }; - }; + configurations { + default = "conf-1"; + conf-1 { + description = "Boot Linux kernel with FDT blob"; + kernel = "kernel"; + fdt = "fdt-1"; + }; + }; + }; |