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-rw-r--r--doc/board/index.rst1
-rw-r--r--doc/board/sophgo/index.rst8
-rw-r--r--doc/board/sophgo/milkv_duo.rst64
-rw-r--r--doc/develop/driver-model/migration.rst2
-rw-r--r--doc/develop/falcon.rst158
-rw-r--r--doc/develop/release_cycle.rst7
-rw-r--r--doc/develop/spl.rst37
-rw-r--r--doc/develop/uefi/uefi.rst2
-rw-r--r--doc/usage/cmd/smbios.rst93
-rw-r--r--doc/usage/index.rst1
10 files changed, 367 insertions, 6 deletions
diff --git a/doc/board/index.rst b/doc/board/index.rst
index c96e5fda281..d0f9f355d2e 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -46,6 +46,7 @@ Board-specific doc
sifive/index
sipeed/index
socionext/index
+ sophgo/index
st/index
starfive/index
ste/index
diff --git a/doc/board/sophgo/index.rst b/doc/board/sophgo/index.rst
new file mode 100644
index 00000000000..e097afdac64
--- /dev/null
+++ b/doc/board/sophgo/index.rst
@@ -0,0 +1,8 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Sophgo
+======
+.. toctree::
+ :maxdepth: 1
+
+ milkv_duo
diff --git a/doc/board/sophgo/milkv_duo.rst b/doc/board/sophgo/milkv_duo.rst
new file mode 100644
index 00000000000..cb2ed1ad987
--- /dev/null
+++ b/doc/board/sophgo/milkv_duo.rst
@@ -0,0 +1,64 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Milk-V Duo
+==========
+
+CV1800B RISC-V SoC
+------------------
+The CV1800B is a high-performance, low-power 1+1 64-bit RISC-V SoC from Sophgo.
+
+Mainline support
+----------------
+The support for following drivers are already enabled:
+1. ns16550 UART Driver.
+
+Building
+~~~~~~~~
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: console
+
+ export CROSS_COMPILE=<riscv64 toolchain prefix>
+ cd <U-Boot-dir>
+ make milkv_duo_defconfig
+ make
+
+This will generate u-boot-dtb.bin
+
+Booting
+~~~~~~~
+Currently, we rely on vendor FSBL(First Stage Boot Loader) to initialize the
+clock and load the u-boot image, then bootup from it.
+
+Alternatively, to run u-boot-dtb.bin on top of FSBL, follow these steps:
+
+1. Use the vendor-provided tool to create a unified fip.bin file containing
+ FSBL, OpenSBI, and U-Boot.
+
+2. Place the generated fip.bin file into the FAT partition of the SD card.
+
+3. Insert the SD card into the board and power it on.
+
+The board will automatically execute the FSBL from the fip.bin file.
+Subsequently, it will transition to OpenSBI, and finally, OpenSBI will invoke
+U-Boot.
+
+
+Sample boot log from Milk-V Duo board
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+.. code-block:: none
+
+ U-Boot 2024.01-rc5-00010-g51965baa36 (Dec 28 2023 - 13:15:53 +0800)milkv_duo
+
+ DRAM: 63.3 MiB
+ Core: 10 devices, 8 uclasses, devicetree: separate
+ Loading Environment from nowhere... OK
+ In: serial@4140000
+ Out: serial@4140000
+ Err: serial@4140000
+ Net: No ethernet found.
+ milkv_duo# cpu detail
+ 0: cpu@0 rv64imafdc
+ ID = 0, freq = 0 Hz: L1 cache, MMU
+ milkv_duo#
diff --git a/doc/develop/driver-model/migration.rst b/doc/develop/driver-model/migration.rst
index 03fea943b29..b40a6af9d11 100644
--- a/doc/develop/driver-model/migration.rst
+++ b/doc/develop/driver-model/migration.rst
@@ -13,7 +13,7 @@ CONFIG_DM
* Status: In progress
* Deadline: 2020.01
-Starting with the 2010.01 release CONFIG_DM will be enabled for all boards.
+Starting with the 2020.01 release CONFIG_DM will be enabled for all boards.
This does not concern CONFIG_DM_SPL and CONFIG_DM_TPL. The conversion date for
these configuration items still needs to be defined.
diff --git a/doc/develop/falcon.rst b/doc/develop/falcon.rst
index 8a46c0efa18..244b4ccb5c2 100644
--- a/doc/develop/falcon.rst
+++ b/doc/develop/falcon.rst
@@ -256,3 +256,161 @@ the following command:
Falcon Mode was presented at the RMLL 2012. Slides are available at:
http://schedule2012.rmll.info/IMG/pdf/LSM2012_UbootFalconMode_Babic.pdf
+
+Falcon Mode Boot on RISC-V
+--------------------------
+
+Introduction
+~~~~~~~~~~~~
+
+In the RISC-V environment, OpenSBI is required to enable a supervisor mode
+binary to execute certain privileged operations. The typical boot sequence on
+RISC-V is SPL -> OpenSBI -> U-Boot -> Linux kernel. SPL will load and start
+the OpenSBI initializations, then OpenSBI will bring up the next image, U-Boot
+proper. The OpenSBI binary must be prepared in advance of the U-Boot build
+process and it will be packed together with U-Boot into a file called
+u-boot.itb.
+
+The Falcon Mode on RISC-V platforms is a distinct boot sequence. Borrowing
+ideas from the U-Boot Falcon Mode on ARM, it skips the U-Boot proper phase
+in the normal boot process and allows OpenSBI to load and start the Linux
+kernel. Its boot sequence is SPL -> OpenSBI -> Linux kernel. The OpenSBI
+binary and Linux kernel binary must be prepared prior to the U-Boot build
+process and they will be packed together as a FIT image named linux.itb in
+this process.
+
+CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT enables the Falcon Mode boot on RISC-V.
+This configuration setting tells OpenSBI that Linux kernel is its next OS
+image and makes it load and start the kernel afterwards.
+
+Note that the Falcon Mode boot bypasses a lot of initializations by U-Boot.
+If the Linux kernel expects hardware initializations by U-Boot, make sure to
+port the relevant code to the SPL build process.
+
+Configuration
+~~~~~~~~~~~~~
+
+CONFIG_SPL_LOAD_FIT_ADDRESS
+ Specifies the address to load u-boot.itb in a normal boot. When the Falcon
+ Mode boot is enabled, it specifies the load address of linux.itb.
+
+CONFIG_SYS_TEXT_BASE
+ Specifies the address of the text section for a u-boot proper in a normal
+ boot. When the Falcon Mode boot is enabled, it specifies the text section
+ address for the Linux kernel image.
+
+CONFIG_SPL_PAYLOAD_ARGS_ADDR
+ The address in the RAM to which the FDT blob is to be moved by the SPL.
+ SPL places the FDT blob right after the kernel. As the kernel does not
+ include the BSS section in its size calculation, SPL ends up placing
+ the FDT blob within the BSS section of the kernel. This may cause the
+ FDT blob to be cleared during kernel BSS initialization. To avoid the
+ issue, be sure to move the FDT blob out of the kernel first.
+
+CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT
+ Activates the Falcon Mode boot on RISC-V.
+
+Example for Andes AE350 Board
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+A FDT blob is required to boot the Linux kernel from the SPL. Andes AE350
+platforms generally come with a builtin dtb. To load a custom DTB, follow
+these steps:
+
+1. Load the custom DTB to SDRAM::
+
+ => fatload mmc 0:1 0x20000000 user_custom.dtb
+
+2. Set the SPI speed::
+
+ => sf probe 0:0 50000000 0
+
+3. Erase sectors from the SPI Flash::
+
+ => sf erase 0xf0000 0x10000
+
+4. Write the FDT blob to the erased sectors of the Flash::
+
+ => sf write 0x20000000 0xf0000 0x10000
+
+Console Log of AE350 Falcon Mode Boot
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ U-Boot SPL 2023.01-00031-g777ecdea66 (Oct 31 2023 - 18:41:36 +0800)
+ Trying to boot from RAM
+
+ OpenSBI v1.2-51-g7304e42
+ ____ _____ ____ _____
+ / __ \ / ____| _ \_ _|
+ | | | |_ __ ___ _ __ | (___ | |_) || |
+ | | | | '_ \ / _ \ '_ \ \___ \| _ < | |
+ | |__| | |_) | __/ | | |____) | |_) || |_
+ \____/| .__/ \___|_| |_|_____/|____/_____|
+ | |
+ |_|
+
+ Platform Name : andestech,ax25
+ Platform Features : medeleg
+ Platform HART Count : 1
+ Platform IPI Device : andes_plicsw
+ Platform Timer Device : andes_plmt @ 60000000Hz
+ Platform Console Device : uart8250
+ Platform HSM Device : andes_smu
+ Platform PMU Device : andes_pmu
+ Platform Reboot Device : atcwdt200
+ Platform Shutdown Device : ---
+ Firmware Base : 0x0
+ Firmware Size : 196 KB
+ Runtime SBI Version : 1.0
+
+ Domain0 Name : root
+ Domain0 Boot HART : 0
+ Domain0 HARTs : 0*
+ Domain0 Region00 : 0x0000000000000000-0x000000000003ffff ()
+ Domain0 Region01 : 0x00000000e6000000-0x00000000e60fffff (I,R)
+ Domain0 Region02 : 0x00000000e6400000-0x00000000e67fffff (I)
+ Domain0 Region03 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
+ Domain0 Next Address : 0x0000000001800000
+ Domain0 Next Arg1 : 0x0000000001700000
+ Domain0 Next Mode : S-mode
+ Domain0 SysReset : yes
+
+ Boot HART ID : 0
+ Boot HART Domain : root
+ Boot HART Priv Version : v1.11
+ Boot HART Base ISA : rv64imafdcx
+ Boot HART ISA Extensions : none
+ Boot HART PMP Count : 8
+ Boot HART PMP Granularity : 4
+ Boot HART PMP Address Bits: 31
+ Boot HART MHPM Count : 4
+ Boot HART MHPM Bits : 64
+ Boot HART MIDELEG : 0x0000000000000222
+ Boot HART MEDELEG : 0x000000000000b109
+ [ 0.000000] Linux version 6.1.47-09019-g0584b09ad862-dirty
+ [ 0.000000] OF: fdt: Ignoring memory range 0x0 - 0x1800000
+ [ 0.000000] Machine model: andestech,ax25
+ [ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
+ [ 0.000000] printk: bootconsole [sbi0] enabled
+ [ 0.000000] Disabled 4-level and 5-level paging
+ [ 0.000000] efi: UEFI not found.
+ [ 0.000000] Zone ranges:
+ [ 0.000000] DMA32 [mem 0x0000000001800000-0x000000003fffffff]
+ [ 0.000000] Normal empty
+ [ 0.000000] Movable zone start for each node
+ [ 0.000000] Early memory node ranges
+ [ 0.000000] node 0: [mem 0x0000000001800000-0x000000003fffffff]
+ [ 0.000000] Initmem setup node 0 [mem 0x0000000001800000-0x000000003fffffff]
+ [ 0.000000] SBI specification v1.0 detected
+ [ 0.000000] SBI implementation ID=0x1 Version=0x10002
+ [ 0.000000] SBI TIME extension detected
+ [ 0.000000] SBI IPI extension detected
+ [ 0.000000] SBI RFENCE extension detected
+ [ 0.000000] SBI SRST extension detected
+ [ 0.000000] SBI HSM extension detected
+ [ 0.000000] riscv: base ISA extensions acim
+ [ 0.000000] riscv: ELF capabilities acim
+ [ 0.000000] percpu: Embedded 18 pages/cpu s35000 r8192 d30536 u73728
+ [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 252500
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 27733135f5e..4f18623b28e 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -50,8 +50,7 @@ Current Status
* U-Boot v2024.01 was released on Mon 08 January 2024.
-* The Merge Window for the next release (v2024.04) is **open** until the -rc1
- release on Mon 29 January 2024.
+* The Merge Window for the next release (v2024.04) is **closed**.
* The next branch is now **closed**.
@@ -63,9 +62,9 @@ Future Releases
.. The following commented out dates are for when release candidates are
planned to be tagged.
-.. For the next scheduled release, release candidates were made on::
+For the next scheduled release, release candidates were made on::
-.. * U-Boot v2024.01-rc1 was released on Mon 29 January 2024.
+* U-Boot v2024.01-rc1 was released on Mon 29 January 2024.
.. * U-Boot v2024.01-rc2 was released on Mon 12 February 2024.
diff --git a/doc/develop/spl.rst b/doc/develop/spl.rst
index 76e87f07c72..0a3e572310a 100644
--- a/doc/develop/spl.rst
+++ b/doc/develop/spl.rst
@@ -65,6 +65,15 @@ CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/raw/nand_spl_load.o)
CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o)
CONFIG_SPL_RAM_DEVICE (common/spl/spl.c)
CONFIG_SPL_WATCHDOG (drivers/watchdog/libwatchdog.o)
+CONFIG_SPL_SYSCON (drivers/core/syscon-uclass.o)
+CONFIG_SPL_GZIP (lib/gzip.o)
+CONFIG_SPL_VIDEO (drivers/video/video-uclass.o drivers/video/vidconsole-uclass.o)
+CONFIG_SPL_SPLASH_SCREEN (common/splash.o)
+CONFIG_SPL_SPLASH_SOURCE (common/splash_source.o)
+CONFIG_SPL_GPIO (drivers/gpio)
+CONFIG_SPL_DM_GPIO (drivers/gpio/gpio-uclass.o)
+CONFIG_SPL_BMP (drivers/video/bmp.o)
+CONFIG_SPL_BLOBLIST (common/bloblist.o)
Adding SPL-specific code
------------------------
@@ -164,3 +173,31 @@ cflow will spit out a number of warnings as it does not parse
the config files and picks functions based on #ifdef. Parsing the '.i'
files instead introduces another set of headaches. These warnings are
not usually important to understanding the flow, however.
+
+
+Reserving memory in SPL
+-----------------------
+
+If memory needs to be reserved in RAM during SPL stage with the requirement that
+the SPL reserved memory remains preserved across further boot stages too
+then it needs to be reserved mandatorily starting from end of RAM. This is to
+ensure that further stages can simply skip this region before carrying out
+further reservations or updating the relocation address.
+
+Also out of these regions which are to be preserved across further stages of
+boot, video framebuffer memory region must be reserved first starting from
+end of RAM for which helper function spl_reserve_video_from_ram_top is provided
+which makes sure that video memory is placed at top of reservation area with
+further reservations below it.
+
+The corresponding information of reservation for those regions can be passed to
+further boot stages using a bloblist. For e.g. the information for
+framebuffer area reserved by SPL can be passed onto U-boot using
+BLOBLISTT_U_BOOT_VIDEO.
+
+The further boot stages need to parse each of the bloblist passed from SPL stage
+starting from video bloblist and skip this whole SPL reserved memory area from
+end of RAM as per the bloblists received, before carrying out further
+reservations or updating the relocation address. For e.g, U-boot proper uses
+function "setup_relocaddr_from_bloblist" to parse the bloblists passed from
+previous stage and skip the memory reserved from previous stage accordingly.
diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
index c739242b6a8..0389b269c01 100644
--- a/doc/develop/uefi/uefi.rst
+++ b/doc/develop/uefi/uefi.rst
@@ -193,7 +193,7 @@ on the sandbox
.. code-block:: bash
cd <U-Boot source directory>
- pytest.py test/py/tests/test_efi_secboot/test_signed.py --bd sandbox
+ pytest test/py/tests/test_efi_secboot/test_signed.py --bd sandbox
UEFI binaries may be signed by Microsoft using the following certificates:
diff --git a/doc/usage/cmd/smbios.rst b/doc/usage/cmd/smbios.rst
new file mode 100644
index 00000000000..1ffd706d7de
--- /dev/null
+++ b/doc/usage/cmd/smbios.rst
@@ -0,0 +1,93 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later:
+
+smbios command
+==============
+
+Synopsis
+--------
+
+::
+
+ smbios
+
+Description
+-----------
+
+The smbios command displays information from the SMBIOS tables.
+
+Examples
+--------
+
+The example below shows an example output of the smbios command.
+
+::
+
+ => smbios
+ SMBIOS 2.8.0 present.
+ 8 structures occupying 81 bytes
+ Table at 0x6d35018
+
+ Handle 0x0100, DMI type 1, 27 bytes at 0x6d35018
+ System Information
+ Manufacturer: QEMU
+ Product Name: Standard PC (i440FX + PIIX, 1996)
+ Version: pc-i440fx-2.5
+ Serial Number:
+ UUID 00000000-0000-0000-0000-000000000000
+ Wake Up Type:
+ Serial Number:
+ SKU Number:
+
+ Handle 0x0300, DMI type 3, 22 bytes at 0x6d35069
+ Header and Data:
+ 00000000: 03 16 00 03 01 01 02 00 00 03 03 03 02 00 00 00
+ 00000010: 00 00 00 00 00 00
+ Strings:
+ String 1: QEMU
+ String 2: pc-i440fx-2.5
+
+ Handle 0x0400, DMI type 4, 42 bytes at 0x6d35093
+ Header and Data:
+ 00000000: 04 2a 00 04 01 03 01 02 63 06 00 00 fd ab 81 07
+ 00000010: 03 00 00 00 d0 07 d0 07 41 01 ff ff ff ff ff ff
+ 00000020: 00 00 00 01 01 01 02 00 01 00
+ Strings:
+ String 1: CPU 0
+ String 2: QEMU
+ String 3: pc-i440fx-2.5
+
+ Handle 0x1000, DMI type 16, 23 bytes at 0x6d350d7
+ Header and Data:
+ 00000000: 10 17 00 10 01 03 06 00 00 02 00 fe ff 01 00 00
+ 00000010: 00 00 00 00 00 00 00
+
+ Handle 0x1100, DMI type 17, 40 bytes at 0x6d350f0
+ Header and Data:
+ 00000000: 11 28 00 11 00 10 fe ff ff ff ff ff 80 00 09 00
+ 00000010: 01 00 07 02 00 00 00 02 00 00 00 00 00 00 00 00
+ 00000020: 00 00 00 00 00 00 00 00
+ Strings:
+ String 1: DIMM 0
+ String 2: QEMU
+
+ Handle 0x1300, DMI type 19, 31 bytes at 0x6d35125
+ Header and Data:
+ 00000000: 13 1f 00 13 00 00 00 00 ff ff 01 00 00 10 01 00
+ 00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+ Handle 0x2000, DMI type 32, 11 bytes at 0x6d35146
+ Header and Data:
+ 00000000: 20 0b 00 20 00 00 00 00 00 00 00
+
+ Handle 0x7f00, DMI type 127, 4 bytes at 0x6d35153
+ End Of Table
+
+Configuration
+-------------
+
+The command is only available if CONFIG_CMD_SMBIOS=y.
+
+Return value
+------------
+
+The return value $? is 0 (true) on success, 1 (false) otherwise.
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index c171c029b80..0d174eefaa5 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -103,6 +103,7 @@ Shell commands
cmd/size
cmd/sleep
cmd/sm
+ cmd/smbios
cmd/sound
cmd/source
cmd/temperature