diff options
Diffstat (limited to 'drivers/adc')
| -rw-r--r-- | drivers/adc/Kconfig | 4 | ||||
| -rw-r--r-- | drivers/adc/rockchip-saradc.c | 202 |
2 files changed, 186 insertions, 20 deletions
diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index a01d73846b7..c9cdbe6942d 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -13,6 +13,7 @@ config ADC config ADC_EXYNOS bool "Enable Exynos 54xx ADC driver" + depends on ADC help This enables basic driver for Exynos ADC compatible with Exynos54xx. It provides: @@ -22,6 +23,7 @@ config ADC_EXYNOS config ADC_SANDBOX bool "Enable Sandbox ADC test driver" + depends on ADC help This enables driver for Sandbox ADC device emulation. It provides: @@ -31,6 +33,7 @@ config ADC_SANDBOX config SARADC_MESON bool "Enable Amlogic Meson SARADC driver" + depends on ADC imply REGMAP help This enables driver for Amlogic Meson SARADC. @@ -41,6 +44,7 @@ config SARADC_MESON config SARADC_ROCKCHIP bool "Enable Rockchip SARADC driver" + depends on ADC help This enables driver for Rockchip SARADC. It provides: diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index 03caca78b5f..10ded1b088f 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -10,12 +10,17 @@ #include <clk.h> #include <dm.h> #include <errno.h> -#include <asm/io.h> +#include <reset.h> +#include <asm/arch-rockchip/hardware.h> +#include <linux/bitfield.h> #include <linux/bitops.h> +#include <linux/delay.h> #include <linux/err.h> #include <linux/printk.h> #include <power/regulator.h> +#define usleep_range(a, b) udelay((b)) + #define SARADC_CTRL_CHN_MASK GENMASK(2, 0) #define SARADC_CTRL_POWER_CTRL BIT(3) #define SARADC_CTRL_IRQ_ENABLE BIT(5) @@ -23,46 +28,163 @@ #define SARADC_TIMEOUT (100 * 1000) -struct rockchip_saradc_regs { +struct rockchip_saradc_regs_v1 { unsigned int data; unsigned int stas; unsigned int ctrl; unsigned int dly_pu_soc; }; +struct rockchip_saradc_regs_v2 { + unsigned int conv_con; +#define SARADC2_SINGLE_MODE BIT(5) +#define SARADC2_START BIT(4) +#define SARADC2_CONV_CHANNELS GENMASK(3, 0) + unsigned int t_pd_soc; + unsigned int t_as_soc; + unsigned int t_das_soc; + unsigned int t_sel_soc; + unsigned int high_comp[16]; + unsigned int low_comp[16]; + unsigned int debounce; + unsigned int ht_int_en; + unsigned int lt_int_en; + unsigned int reserved[24]; + unsigned int mt_int_en; + unsigned int end_int_en; +#define SARADC2_EN_END_INT BIT(0) + unsigned int st_con; + unsigned int status; + unsigned int end_int_st; + unsigned int ht_int_st; + unsigned int lt_int_st; + unsigned int mt_int_st; + unsigned int data[16]; + unsigned int auto_ch_en; +}; + +union rockchip_saradc_regs { + struct rockchip_saradc_regs_v1 *v1; + struct rockchip_saradc_regs_v2 *v2; +}; struct rockchip_saradc_data { int num_bits; int num_channels; unsigned long clk_rate; + int (*channel_data)(struct udevice *dev, int channel, unsigned int *data); + int (*start_channel)(struct udevice *dev, int channel); + int (*stop)(struct udevice *dev); }; struct rockchip_saradc_priv { - struct rockchip_saradc_regs *regs; + union rockchip_saradc_regs regs; int active_channel; const struct rockchip_saradc_data *data; + struct reset_ctl *reset; }; +int rockchip_saradc_channel_data_v1(struct udevice *dev, int channel, + unsigned int *data) +{ + struct rockchip_saradc_priv *priv = dev_get_priv(dev); + + if ((readl(&priv->regs.v1->ctrl) & SARADC_CTRL_IRQ_STATUS) != + SARADC_CTRL_IRQ_STATUS) + return -EBUSY; + + /* Read value */ + *data = readl(&priv->regs.v1->data); + + /* Power down adc */ + writel(0, &priv->regs.v1->ctrl); + + return 0; +} + +int rockchip_saradc_channel_data_v2(struct udevice *dev, int channel, + unsigned int *data) +{ + struct rockchip_saradc_priv *priv = dev_get_priv(dev); + + if (!(readl(&priv->regs.v2->end_int_st) & SARADC2_EN_END_INT)) + return -EBUSY; + + /* Read value */ + *data = readl(&priv->regs.v2->data[channel]); + + /* Acknowledge the interrupt */ + writel(SARADC2_EN_END_INT, &priv->regs.v2->end_int_st); + + return 0; +} int rockchip_saradc_channel_data(struct udevice *dev, int channel, unsigned int *data) { struct rockchip_saradc_priv *priv = dev_get_priv(dev); struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); + int ret; if (channel != priv->active_channel) { pr_err("Requested channel is not active!"); return -EINVAL; } - if ((readl(&priv->regs->ctrl) & SARADC_CTRL_IRQ_STATUS) != - SARADC_CTRL_IRQ_STATUS) - return -EBUSY; + ret = priv->data->channel_data(dev, channel, data); + if (ret) { + if (ret != -EBUSY) + pr_err("Error reading channel data, %d!", ret); + return ret; + } - /* Read value */ - *data = readl(&priv->regs->data); *data &= uc_pdata->data_mask; - /* Power down adc */ - writel(0, &priv->regs->ctrl); + return 0; +} + +int rockchip_saradc_start_channel_v1(struct udevice *dev, int channel) +{ + struct rockchip_saradc_priv *priv = dev_get_priv(dev); + + /* 8 clock periods as delay between power up and start cmd */ + writel(8, &priv->regs.v1->dly_pu_soc); + + /* Select the channel to be used and trigger conversion */ + writel(SARADC_CTRL_POWER_CTRL | (channel & SARADC_CTRL_CHN_MASK) | + SARADC_CTRL_IRQ_ENABLE, &priv->regs.v1->ctrl); + + return 0; +} + +static void rockchip_saradc_reset_controller(struct reset_ctl *reset) +{ + reset_assert(reset); + usleep_range(10, 20); + reset_deassert(reset); +} + +int rockchip_saradc_start_channel_v2(struct udevice *dev, int channel) +{ + struct rockchip_saradc_priv *priv = dev_get_priv(dev); + + /* + * Downstream says + * """If read other chn at anytime, then chn1 will error, assert + * controller as a workaround.""" + */ + if (priv->reset) + rockchip_saradc_reset_controller(priv->reset); + + writel(0xc, &priv->regs.v2->t_das_soc); + writel(0x20, &priv->regs.v2->t_pd_soc); + + /* Acknowledge any previous interrupt */ + writel(SARADC2_EN_END_INT, &priv->regs.v2->end_int_st); + + rk_clrsetreg(&priv->regs.v2->conv_con, + SARADC2_CONV_CHANNELS | SARADC2_START | SARADC2_SINGLE_MODE, + FIELD_PREP(SARADC2_CONV_CHANNELS, channel) | + FIELD_PREP(SARADC2_START, 1) | + FIELD_PREP(SARADC2_SINGLE_MODE, 1)); return 0; } @@ -70,30 +192,46 @@ int rockchip_saradc_channel_data(struct udevice *dev, int channel, int rockchip_saradc_start_channel(struct udevice *dev, int channel) { struct rockchip_saradc_priv *priv = dev_get_priv(dev); + int ret; if (channel < 0 || channel >= priv->data->num_channels) { pr_err("Requested channel is invalid!"); return -EINVAL; } - /* 8 clock periods as delay between power up and start cmd */ - writel(8, &priv->regs->dly_pu_soc); - - /* Select the channel to be used and trigger conversion */ - writel(SARADC_CTRL_POWER_CTRL | (channel & SARADC_CTRL_CHN_MASK) | - SARADC_CTRL_IRQ_ENABLE, &priv->regs->ctrl); + ret = priv->data->start_channel(dev, channel); + if (ret) { + pr_err("Error starting channel, %d!", ret); + return ret; + } priv->active_channel = channel; return 0; } -int rockchip_saradc_stop(struct udevice *dev) +int rockchip_saradc_stop_v1(struct udevice *dev) { struct rockchip_saradc_priv *priv = dev_get_priv(dev); /* Power down adc */ - writel(0, &priv->regs->ctrl); + writel(0, &priv->regs.v1->ctrl); + + return 0; +} + +int rockchip_saradc_stop(struct udevice *dev) +{ + struct rockchip_saradc_priv *priv = dev_get_priv(dev); + + if (priv->data->stop) { + int ret = priv->data->stop(dev); + + if (ret) { + pr_err("Error stopping channel, %d!", ret); + return ret; + } + } priv->active_channel = -1; @@ -109,6 +247,8 @@ int rockchip_saradc_probe(struct udevice *dev) int vref_uv; int ret; + priv->reset = devm_reset_control_get_optional(dev, "saradc-apb"); + ret = clk_get_by_index(dev, 0, &clk); if (ret) return ret; @@ -125,6 +265,9 @@ int rockchip_saradc_probe(struct udevice *dev) return ret; } + if (priv->reset) + rockchip_saradc_reset_controller(priv->reset); + vref_uv = regulator_get_value(vref); if (vref_uv < 0) { printf("can't get vref-supply value: %d\n", vref_uv); @@ -146,8 +289,8 @@ int rockchip_saradc_of_to_plat(struct udevice *dev) struct rockchip_saradc_data *data; data = (struct rockchip_saradc_data *)dev_get_driver_data(dev); - priv->regs = dev_read_addr_ptr(dev); - if (!priv->regs) { + priv->regs.v1 = dev_read_addr_ptr(dev); + if (!priv->regs.v1) { pr_err("Dev: %s - can't get address!", dev->name); return -EINVAL; } @@ -171,18 +314,35 @@ static const struct rockchip_saradc_data saradc_data = { .num_bits = 10, .num_channels = 3, .clk_rate = 1000000, + .channel_data = rockchip_saradc_channel_data_v1, + .start_channel = rockchip_saradc_start_channel_v1, + .stop = rockchip_saradc_stop_v1, }; static const struct rockchip_saradc_data rk3066_tsadc_data = { .num_bits = 12, .num_channels = 2, .clk_rate = 50000, + .channel_data = rockchip_saradc_channel_data_v1, + .start_channel = rockchip_saradc_start_channel_v1, + .stop = rockchip_saradc_stop_v1, }; static const struct rockchip_saradc_data rk3399_saradc_data = { .num_bits = 10, .num_channels = 6, .clk_rate = 1000000, + .channel_data = rockchip_saradc_channel_data_v1, + .start_channel = rockchip_saradc_start_channel_v1, + .stop = rockchip_saradc_stop_v1, +}; + +static const struct rockchip_saradc_data rk3588_saradc_data = { + .num_bits = 12, + .num_channels = 8, + .clk_rate = 1000000, + .channel_data = rockchip_saradc_channel_data_v2, + .start_channel = rockchip_saradc_start_channel_v2, }; static const struct udevice_id rockchip_saradc_ids[] = { @@ -192,6 +352,8 @@ static const struct udevice_id rockchip_saradc_ids[] = { .data = (ulong)&rk3066_tsadc_data }, { .compatible = "rockchip,rk3399-saradc", .data = (ulong)&rk3399_saradc_data }, + { .compatible = "rockchip,rk3588-saradc", + .data = (ulong)&rk3588_saradc_data }, { } }; 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