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-rw-r--r--drivers/cache/cache-andes-l2.c9
-rw-r--r--drivers/cache/cache-l2x0.c2
-rw-r--r--drivers/cache/cache-sifive-ccache.c1
-rw-r--r--drivers/cache/cache-uclass.c1
-rw-r--r--drivers/cache/sandbox_cache.c2
5 files changed, 5 insertions, 10 deletions
diff --git a/drivers/cache/cache-andes-l2.c b/drivers/cache/cache-andes-l2.c
index 45d29f2fbd9..45a4f216b07 100644
--- a/drivers/cache/cache-andes-l2.c
+++ b/drivers/cache/cache-andes-l2.c
@@ -4,7 +4,6 @@
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/
-#include <common.h>
#include <command.h>
#include <cache.h>
#include <dm.h>
@@ -30,7 +29,7 @@ struct l2cache {
volatile u64 cctl_command2;
volatile u64 cctl_access_line2;
volatile u64 cctl_command3;
- volatile u64 cctl_access_line4;
+ volatile u64 cctl_access_line3;
volatile u64 cctl_status;
};
@@ -97,13 +96,15 @@ static int andes_l2_disable(struct udevice *dev)
struct andes_l2_plat *plat = dev_get_plat(dev);
volatile struct l2cache *regs = plat->regs;
u8 hart = gd->arch.boot_hart;
+
void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
+ void __iomem *cctlstatus = (void __iomem *)CCTL_STATUS_REG(regs, hart);
if ((regs) && (readl(&regs->control) & L2_ENABLE)) {
writel(L2_WBINVAL_ALL, cctlcmd);
- while ((readl(&regs->cctl_status) & CCTL_STATUS_MSK(hart))) {
- if ((readl(&regs->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
+ while ((readl(cctlstatus) & CCTL_STATUS_MSK(hart))) {
+ if ((readl(cctlstatus) & CCTL_STATUS_ILLEGAL(hart))) {
printf("L2 flush illegal! hanging...");
hang();
}
diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
index 560f4c94f1e..8b29af42338 100644
--- a/drivers/cache/cache-l2x0.c
+++ b/drivers/cache/cache-l2x0.c
@@ -2,7 +2,6 @@
/*
* Copyright (C) 2019 Intel Corporation <www.intel.com>
*/
-#include <common.h>
#include <command.h>
#include <dm.h>
@@ -63,7 +62,6 @@ static int l2x0_probe(struct udevice *dev)
return 0;
}
-
static const struct udevice_id l2x0_ids[] = {
{ .compatible = "arm,pl310-cache" },
{}
diff --git a/drivers/cache/cache-sifive-ccache.c b/drivers/cache/cache-sifive-ccache.c
index 521df40466f..cc00b80f60b 100644
--- a/drivers/cache/cache-sifive-ccache.c
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -3,7 +3,6 @@
* Copyright (C) 2021 SiFive
*/
-#include <common.h>
#include <cache.h>
#include <dm.h>
#include <asm/io.h>
diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
index 0c13dbdb75c..300e7bc86e1 100644
--- a/drivers/cache/cache-uclass.c
+++ b/drivers/cache/cache-uclass.c
@@ -5,7 +5,6 @@
#define LOG_CATEGORY UCLASS_CACHE
-#include <common.h>
#include <cache.h>
#include <dm.h>
diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c
index 955dfc8a0f8..375892fafb0 100644
--- a/drivers/cache/sandbox_cache.c
+++ b/drivers/cache/sandbox_cache.c
@@ -3,7 +3,6 @@
* Copyright (C) 2019 Intel Corporation <www.intel.com>
*/
-#include <common.h>
#include <cache.h>
#include <dm.h>
#include <errno.h>
@@ -28,7 +27,6 @@ static int snadbox_disable(struct udevice *dev)
return 0;
}
-
static const struct cache_ops sandbox_cache_ops = {
.get_info = sandbox_get_info,
.enable = sandbox_enable,