diff options
Diffstat (limited to 'drivers/clk/qcom')
| -rw-r--r-- | drivers/clk/qcom/clock-apq8016.c | 21 | ||||
| -rw-r--r-- | drivers/clk/qcom/clock-apq8096.c | 7 | ||||
| -rw-r--r-- | drivers/clk/qcom/clock-qcs404.c | 25 |
3 files changed, 28 insertions, 25 deletions
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index c0ce570edc7..e6647f7c41d 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -13,6 +13,7 @@ #include <errno.h> #include <asm/io.h> #include <linux/bitops.h> +#include <dt-bindings/clock/qcom,gcc-msm8916.h> #include "clock-qcom.h" @@ -102,20 +103,20 @@ static const struct bcr_regs uart2_regs = { }; /* UART: 115200 */ -static int clk_init_uart(struct msm_clk_priv *priv) +int apq8016_clk_init_uart(phys_addr_t base) { /* Enable AHB clock */ - clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk); + clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk); /* 7372800 uart block clock @ GPLL0 */ - clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625, + clk_rcg_set_rate_mnd(base, &uart2_regs, 1, 144, 15625, CFG_CLK_SRC_GPLL0, 16); /* Vote for gpll0 clock */ - clk_enable_gpll0(priv->base, &gpll0_vote_clk); + clk_enable_gpll0(base, &gpll0_vote_clk); /* Enable core clk */ - clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); + clk_enable_cbc(base + BLSP1_UART2_APPS_CBCR); return 0; } @@ -125,14 +126,14 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) struct msm_clk_priv *priv = dev_get_priv(clk->dev); switch (clk->id) { - case 0: /* SDC1 */ + case GCC_SDCC1_APPS_CLK: /* SDC1 */ return clk_init_sdc(priv, 0, rate); break; - case 1: /* SDC2 */ + case GCC_SDCC2_APPS_CLK: /* SDC2 */ return clk_init_sdc(priv, 1, rate); break; - case 4: /* UART2 */ - return clk_init_uart(priv); + case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */ + return apq8016_clk_init_uart(priv->base); break; default: return 0; @@ -145,7 +146,7 @@ static struct msm_clk_data apq8016_clk_data = { static const struct udevice_id gcc_apq8016_of_match[] = { { - .compatible = "qcom,gcc-apq8016", + .compatible = "qcom,gcc-msm8916", .data = (ulong)&apq8016_clk_data, }, { } diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index cf1a347309a..a4731613c5e 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -13,6 +13,7 @@ #include <errno.h> #include <asm/io.h> #include <linux/bitops.h> +#include <dt-bindings/clock/qcom,gcc-msm8996.h> #include "clock-qcom.h" @@ -107,10 +108,10 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate) struct msm_clk_priv *priv = dev_get_priv(clk->dev); switch (clk->id) { - case 0: /* SDC1 */ + case GCC_SDCC1_APPS_CLK: /* SDC1 */ return clk_init_sdc(priv, rate); break; - case 4: /*UART2*/ + case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/ return clk_init_uart(priv); default: return 0; @@ -123,7 +124,7 @@ static struct msm_clk_data apq8096_clk_data = { static const struct udevice_id gcc_apq8096_of_match[] = { { - .compatible = "qcom,gcc-apq8096", + .compatible = "qcom,gcc-msm8996", .data = (ulong)&apq8096_clk_data, }, { } diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index f5b35280392..958312b8884 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -193,24 +193,18 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case GCC_BLSP1_UART2_APPS_CLK: - /* UART: 115200 */ + /* UART: 1843200Hz for a fixed 115200 baudrate (19200000 * (12/125)) */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125, CFG_CLK_SRC_CXO, 16); clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); - break; - case GCC_BLSP1_AHB_CLK: - clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk); - break; + return 1843200; case GCC_SDCC1_APPS_CLK: /* SDCC1: 200MHz */ clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1)); - break; - case GCC_SDCC1_AHB_CLK: - clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1)); - break; + return rate; case GCC_ETH_RGMII_CLK: if (rate == 250000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0, @@ -224,11 +218,15 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) else if (rate == 5000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50, CFG_CLK_SRC_GPLL1, 8); - break; - default: - return 0; + return rate; } + /* There is a bug only seeming to affect this board where the MMC driver somehow calls + * clk_set_rate() on a clock with id 0 which is associated with the qcom_clk device. + * The only clock with ID 0 is the xo_board clock which should not be associated with + * this device... + */ + log_debug("Unknown clock id %ld\n", clk->id); return 0; } @@ -305,6 +303,9 @@ static int qcs404_clk_enable(struct clk *clk) clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0, CFG_CLK_SRC_CXO); break; + case GCC_SDCC1_AHB_CLK: + clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1)); + break; default: return 0; } |