summaryrefslogtreecommitdiff
path: root/drivers/clk
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/clk-uclass.c39
-rw-r--r--drivers/clk/clk_fixed_rate.c45
-rw-r--r--drivers/clk/ti/Kconfig24
-rw-r--r--drivers/clk/ti/Makefile2
-rw-r--r--drivers/clk/ti/clk-k3-pll.c283
-rw-r--r--drivers/clk/ti/clk-k3.c374
-rw-r--r--drivers/clk/ti/clk-sci.c6
7 files changed, 771 insertions, 2 deletions
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 53e7be764d3..3d2344f009e 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -241,6 +241,15 @@ static int clk_set_default_parents(struct udevice *dev, int stage)
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
index, &clk);
+ /*
+ * If the clock provider is not ready yet, let it handle
+ * the re-programming later.
+ */
+ if (ret == -EPROBE_DEFER) {
+ ret = 0;
+ continue;
+ }
+
if (ret) {
debug("%s: could not get assigned clock %d for %s\n",
__func__, index, dev_read_name(dev));
@@ -309,6 +318,15 @@ static int clk_set_default_rates(struct udevice *dev, int stage)
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
index, &clk);
+ /*
+ * If the clock provider is not ready yet, let it handle
+ * the re-programming later.
+ */
+ if (ret == -EPROBE_DEFER) {
+ ret = 0;
+ continue;
+ }
+
if (ret) {
dev_dbg(dev,
"could not get assigned clock %d (err = %d)\n",
@@ -502,6 +520,8 @@ struct clk *clk_get_parent(struct clk *clk)
return NULL;
pdev = dev_get_parent(clk->dev);
+ if (!pdev)
+ return ERR_PTR(-ENODEV);
pclk = dev_get_clk_ptr(pdev);
if (!pclk)
return ERR_PTR(-ENODEV);
@@ -548,6 +568,22 @@ ulong clk_round_rate(struct clk *clk, ulong rate)
return ops->round_rate(clk, rate);
}
+static void clk_clean_rate_cache(struct clk *clk)
+{
+ struct udevice *child_dev;
+ struct clk *clkp;
+
+ if (!clk)
+ return;
+
+ clk->rate = 0;
+
+ list_for_each_entry(child_dev, &clk->dev->child_head, sibling_node) {
+ clkp = dev_get_clk_ptr(child_dev);
+ clk_clean_rate_cache(clkp);
+ }
+}
+
ulong clk_set_rate(struct clk *clk, ulong rate)
{
const struct clk_ops *ops;
@@ -560,6 +596,9 @@ ulong clk_set_rate(struct clk *clk, ulong rate)
if (!ops->set_rate)
return -ENOSYS;
+ /* Clean up cached rates for us and all child clocks */
+ clk_clean_rate_cache(clk);
+
return ops->set_rate(clk, rate);
}
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 09f9ef26a42..325a9b2dcfb 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -9,6 +9,9 @@
#include <dm/device-internal.h>
#include <linux/clk-provider.h>
+#define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock"
+#define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock"
+
static ulong clk_fixed_rate_get_rate(struct clk *clk)
{
return to_clk_fixed_rate(clk->dev)->fixed_rate;
@@ -40,6 +43,15 @@ void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
clk->enable_count = 0;
}
+static ulong clk_fixed_rate_raw_get_rate(struct clk *clk)
+{
+ return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate;
+}
+
+const struct clk_ops clk_fixed_rate_raw_ops = {
+ .get_rate = clk_fixed_rate_raw_get_rate,
+};
+
static int clk_fixed_rate_of_to_plat(struct udevice *dev)
{
clk_fixed_rate_ofdata_to_plat_(dev, to_clk_fixed_rate(dev));
@@ -47,6 +59,32 @@ static int clk_fixed_rate_of_to_plat(struct udevice *dev)
return 0;
}
+#if CONFIG_IS_ENABLED(CLK_CCF)
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+ ulong rate)
+{
+ struct clk *clk;
+ struct clk_fixed_rate *fixed;
+ int ret;
+
+ fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
+ if (!fixed)
+ return ERR_PTR(-ENOMEM);
+
+ fixed->fixed_rate = rate;
+
+ clk = &fixed->clk;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name, NULL);
+ if (ret) {
+ kfree(fixed);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+#endif
+
static const struct udevice_id clk_fixed_rate_match[] = {
{
.compatible = "fixed-clock",
@@ -63,3 +101,10 @@ U_BOOT_DRIVER(fixed_clock) = {
.ops = &clk_fixed_rate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
+
+U_BOOT_DRIVER(clk_fixed_rate_raw) = {
+ .name = UBOOT_DM_CLK_FIXED_RATE_RAW,
+ .id = UCLASS_CLK,
+ .ops = &clk_fixed_rate_raw_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index 2dc86d44a98..fbcdefd889a 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -41,3 +41,27 @@ config CLK_TI_SCI
This enables the clock driver support over TI System Control Interface
available on some new TI's SoCs. If you wish to use clock resources
managed by the TI System Controller, say Y here. Otherwise, say N.
+
+config CLK_K3_PLL
+ bool "PLL clock support for K3 SoC family of devices"
+ depends on CLK && LIB_RATIONAL
+ help
+ Enables PLL clock support for K3 SoC family of devices.
+
+config SPL_CLK_K3_PLL
+ bool "PLL clock support for K3 SoC family of devices"
+ depends on CLK && LIB_RATIONAL && SPL
+ help
+ Enables PLL clock support for K3 SoC family of devices.
+
+config CLK_K3
+ bool "Clock support for K3 SoC family of devices"
+ depends on CLK
+ help
+ Enables the clock translation layer from DT to device clocks.
+
+config SPL_CLK_K3
+ bool "Clock support for K3 SoC family of devices"
+ depends on CLK && SPL
+ help
+ Enables the clock translation layer from DT to device clocks.
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 9f56b477360..07aa9a53e08 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -11,3 +11,5 @@ obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3) += clk-k3.o
diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c
new file mode 100644
index 00000000000..bf2407a020a
--- /dev/null
+++ b/drivers/clk/ti/clk-k3-pll.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 SoC PLL clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo <t-kristo@ti.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <clk-uclass.h>
+#include <linux/clk-provider.h>
+#include "k3-clk.h"
+#include <linux/rational.h>
+
+/* 16FFT register offsets */
+#define PLL_16FFT_CFG 0x08
+#define PLL_KICK0 0x10
+#define PLL_KICK1 0x14
+#define PLL_16FFT_CTRL 0x20
+#define PLL_16FFT_STAT 0x24
+#define PLL_16FFT_FREQ_CTRL0 0x30
+#define PLL_16FFT_FREQ_CTRL1 0x34
+#define PLL_16FFT_DIV_CTRL 0x38
+
+/* CTRL register bits */
+#define PLL_16FFT_CTRL_BYPASS_EN BIT(31)
+#define PLL_16FFT_CTRL_PLL_EN BIT(15)
+#define PLL_16FFT_CTRL_DSM_EN BIT(1)
+
+/* STAT register bits */
+#define PLL_16FFT_STAT_LOCK BIT(0)
+
+/* FREQ_CTRL0 bits */
+#define PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK 0xfff
+
+/* DIV CTRL register bits */
+#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK 0x3f
+
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24
+#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN BIT(15)
+
+/* KICK register magic values */
+#define PLL_KICK0_VALUE 0x68ef3490
+#define PLL_KICK1_VALUE 0xd172bc5a
+
+/**
+ * struct ti_pll_clk - TI PLL clock data info structure
+ * @clk: core clock structure
+ * @reg: memory address of the PLL controller
+ */
+struct ti_pll_clk {
+ struct clk clk;
+ void __iomem *reg;
+};
+
+#define to_clk_pll(_clk) container_of(_clk, struct ti_pll_clk, clk)
+
+static int ti_pll_wait_for_lock(struct clk *clk)
+{
+ struct ti_pll_clk *pll = to_clk_pll(clk);
+ u32 stat;
+ int i;
+
+ for (i = 0; i < 100000; i++) {
+ stat = readl(pll->reg + PLL_16FFT_STAT);
+ if (stat & PLL_16FFT_STAT_LOCK)
+ return 0;
+ }
+
+ printf("%s: pll (%s) failed to lock\n", __func__,
+ clk->dev->name);
+
+ return -EBUSY;
+}
+
+static ulong ti_pll_clk_get_rate(struct clk *clk)
+{
+ struct ti_pll_clk *pll = to_clk_pll(clk);
+ u64 current_freq;
+ u64 parent_freq = clk_get_parent_rate(clk);
+ u32 pllm;
+ u32 plld;
+ u32 pllfm;
+ u32 ctrl;
+
+ /* Check if we are in bypass */
+ ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+ if (ctrl & PLL_16FFT_CTRL_BYPASS_EN)
+ return parent_freq;
+
+ pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0);
+ pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
+
+ plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) &
+ PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
+
+ current_freq = parent_freq * pllm / plld;
+
+ if (pllfm) {
+ u64 tmp;
+
+ tmp = parent_freq * pllfm;
+ do_div(tmp, plld);
+ tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+ current_freq += tmp;
+ }
+
+ return current_freq;
+}
+
+static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct ti_pll_clk *pll = to_clk_pll(clk);
+ u64 current_freq;
+ u64 parent_freq = clk_get_parent_rate(clk);
+ int ret;
+ u32 ctrl;
+ unsigned long pllm;
+ u32 pllfm = 0;
+ unsigned long plld;
+ u32 rem;
+ int shift;
+
+ debug("%s(clk=%p, rate=%u)\n", __func__, clk, (u32)rate);
+
+ if (ti_pll_clk_get_rate(clk) == rate)
+ return rate;
+
+ if (rate != parent_freq)
+ /*
+ * Attempt with higher max multiplier value first to give
+ * some space for fractional divider to kick in.
+ */
+ for (shift = 8; shift >= 0; shift -= 8) {
+ rational_best_approximation(rate, parent_freq,
+ ((PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK + 1) << shift) - 1,
+ PLL_16FFT_DIV_CTRL_REF_DIV_MASK, &pllm, &plld);
+ if (pllm / plld <= PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK)
+ break;
+ }
+
+ /* Put PLL to bypass mode */
+ ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+ ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
+ writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+ if (rate == parent_freq) {
+ debug("%s: put %s to bypass\n", __func__, clk->dev->name);
+ return rate;
+ }
+
+ debug("%s: pre-frac-calc: rate=%u, parent_freq=%u, plld=%u, pllm=%u\n",
+ __func__, (u32)rate, (u32)parent_freq, (u32)plld, (u32)pllm);
+
+ /* Check if we need fractional config */
+ if (plld > 1) {
+ pllfm = pllm % plld;
+ pllfm <<= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+ rem = pllfm % plld;
+ pllfm /= plld;
+ if (rem)
+ pllfm++;
+ pllm /= plld;
+ plld = 1;
+ }
+
+ if (pllfm)
+ ctrl |= PLL_16FFT_CTRL_DSM_EN;
+ else
+ ctrl &= ~PLL_16FFT_CTRL_DSM_EN;
+
+ writel(pllm, pll->reg + PLL_16FFT_FREQ_CTRL0);
+ writel(pllfm, pll->reg + PLL_16FFT_FREQ_CTRL1);
+ writel(plld, pll->reg + PLL_16FFT_DIV_CTRL);
+
+ ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
+ ctrl |= PLL_16FFT_CTRL_PLL_EN;
+ writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+ ret = ti_pll_wait_for_lock(clk);
+ if (ret)
+ return ret;
+
+ debug("%s: pllm=%u, plld=%u, pllfm=%u, parent_freq=%u\n",
+ __func__, (u32)pllm, (u32)plld, (u32)pllfm, (u32)parent_freq);
+
+ current_freq = parent_freq * pllm / plld;
+
+ if (pllfm) {
+ u64 tmp;
+
+ tmp = parent_freq * pllfm;
+ do_div(tmp, plld);
+ tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+ current_freq += tmp;
+ }
+
+ return current_freq;
+}
+
+static int ti_pll_clk_enable(struct clk *clk)
+{
+ struct ti_pll_clk *pll = to_clk_pll(clk);
+ u32 ctrl;
+
+ ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+ ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
+ ctrl |= PLL_16FFT_CTRL_PLL_EN;
+ writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+ return ti_pll_wait_for_lock(clk);
+}
+
+static int ti_pll_clk_disable(struct clk *clk)
+{
+ struct ti_pll_clk *pll = to_clk_pll(clk);
+ u32 ctrl;
+
+ ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+ ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
+ writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+ return 0;
+}
+
+static const struct clk_ops ti_pll_clk_ops = {
+ .get_rate = ti_pll_clk_get_rate,
+ .set_rate = ti_pll_clk_set_rate,
+ .enable = ti_pll_clk_enable,
+ .disable = ti_pll_clk_disable,
+};
+
+struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
+ void __iomem *reg)
+{
+ struct ti_pll_clk *pll;
+ int ret;
+ int i;
+ u32 cfg, ctrl, hsdiv_presence_bit, hsdiv_ctrl_offs;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->reg = reg;
+
+ ret = clk_register(&pll->clk, "ti-pll-clk", name, parent_name);
+ if (ret) {
+ printf("%s: failed to register: %d\n", __func__, ret);
+ kfree(pll);
+ return ERR_PTR(ret);
+ }
+
+ /* Unlock the PLL registers */
+ writel(PLL_KICK0_VALUE, pll->reg + PLL_KICK0);
+ writel(PLL_KICK1_VALUE, pll->reg + PLL_KICK1);
+
+ /* Enable all HSDIV outputs */
+ cfg = readl(pll->reg + PLL_16FFT_CFG);
+ for (i = 0; i < 16; i++) {
+ hsdiv_presence_bit = BIT(16 + i);
+ hsdiv_ctrl_offs = 0x80 + (i * 4);
+ /* Enable HSDIV output if present */
+ if ((hsdiv_presence_bit & cfg) != 0UL) {
+ ctrl = readl(pll->reg + hsdiv_ctrl_offs);
+ ctrl |= PLL_16FFT_HSDIV_CTRL_CLKOUT_EN;
+ writel(ctrl, pll->reg + hsdiv_ctrl_offs);
+ }
+ }
+
+ return &pll->clk;
+}
+
+U_BOOT_DRIVER(ti_pll_clk) = {
+ .name = "ti-pll-clk",
+ .id = UCLASS_CLK,
+ .ops = &ti_pll_clk_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
new file mode 100644
index 00000000000..e921894e7a2
--- /dev/null
+++ b/drivers/clk/ti/clk-k3.c
@@ -0,0 +1,374 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo <t-kristo@ti.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <soc.h>
+#include <clk-uclass.h>
+#include "k3-clk.h"
+
+#define PLL_MIN_FREQ 800000000
+#define PLL_MAX_FREQ 3200000000UL
+#define PLL_MAX_DIV 127
+
+/**
+ * struct clk_map - mapping from dev/clk id tuples towards physical clocks
+ * @dev_id: device ID for the clock
+ * @clk_id: clock ID for the clock
+ * @clk: pointer to the registered clock entry for the mapping
+ */
+struct clk_map {
+ u16 dev_id;
+ u32 clk_id;
+ struct clk *clk;
+};
+
+/**
+ * struct ti_clk_data - clock controller information structure
+ * @map: mapping from dev/clk id tuples to physical clock entries
+ * @size: number of entries in the map
+ */
+struct ti_clk_data {
+ struct clk_map *map;
+ int size;
+};
+
+static ulong osc_freq;
+
+static void clk_add_map(struct ti_clk_data *data, struct clk *clk,
+ u32 dev_id, u32 clk_id)
+{
+ struct clk_map *map;
+
+ debug("%s: added clk=%p, data=%p, dev=%d, clk=%d\n", __func__,
+ clk, data, dev_id, clk_id);
+ if (!clk)
+ return;
+
+ map = data->map + data->size++;
+
+ map->dev_id = dev_id;
+ map->clk_id = clk_id;
+ map->clk = clk;
+}
+
+static const struct soc_attr ti_k3_soc_clk_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_J721E)
+ {
+ .family = "J721E",
+ .data = &j721e_clk_platdata,
+ },
+ {
+ .family = "J7200",
+ .data = &j7200_clk_platdata,
+ },
+#endif
+ { /* sentinel */ }
+};
+
+static int ti_clk_probe(struct udevice *dev)
+{
+ struct ti_clk_data *data = dev_get_priv(dev);
+ struct clk *clk;
+ const char *name;
+ const struct clk_data *ti_clk_data;
+ int i, j;
+ const struct soc_attr *soc_match_data;
+ const struct ti_k3_clk_platdata *pdata;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ soc_match_data = soc_device_match(ti_k3_soc_clk_data);
+ if (!soc_match_data)
+ return -ENODEV;
+
+ pdata = (const struct ti_k3_clk_platdata *)soc_match_data->data;
+
+ data->map = kcalloc(pdata->soc_dev_clk_data_cnt, sizeof(*data->map),
+ GFP_KERNEL);
+ data->size = 0;
+
+ for (i = 0; i < pdata->clk_list_cnt; i++) {
+ ti_clk_data = &pdata->clk_list[i];
+
+ switch (ti_clk_data->type) {
+ case CLK_TYPE_FIXED_RATE:
+ name = ti_clk_data->clk.fixed_rate.name;
+ clk = clk_register_fixed_rate(NULL,
+ name,
+ ti_clk_data->clk.fixed_rate.rate);
+ break;
+ case CLK_TYPE_DIV:
+ name = ti_clk_data->clk.div.name;
+ clk = clk_register_divider(NULL, name,
+ ti_clk_data->clk.div.parent,
+ ti_clk_data->clk.div.flags,
+ map_physmem(ti_clk_data->clk.div.reg, 0, MAP_NOCACHE),
+ ti_clk_data->clk.div.shift,
+ ti_clk_data->clk.div.width,
+ 0);
+ break;
+ case CLK_TYPE_MUX:
+ name = ti_clk_data->clk.mux.name;
+ clk = clk_register_mux(NULL, name,
+ ti_clk_data->clk.mux.parents,
+ ti_clk_data->clk.mux.num_parents,
+ ti_clk_data->clk.mux.flags,
+ map_physmem(ti_clk_data->clk.mux.reg, 0, MAP_NOCACHE),
+ ti_clk_data->clk.mux.shift,
+ ti_clk_data->clk.mux.width,
+ 0);
+ break;
+ case CLK_TYPE_PLL:
+ name = ti_clk_data->clk.pll.name;
+ clk = clk_register_ti_pll(name,
+ ti_clk_data->clk.pll.parent,
+ map_physmem(ti_clk_data->clk.pll.reg, 0, MAP_NOCACHE));
+
+ if (!osc_freq)
+ osc_freq = clk_get_rate(clk_get_parent(clk));
+ break;
+ default:
+ name = NULL;
+ clk = NULL;
+ printf("WARNING: %s has encountered unknown clk type %d\n",
+ __func__, ti_clk_data->type);
+ }
+
+ if (clk && ti_clk_data->default_freq)
+ clk_set_rate(clk, ti_clk_data->default_freq);
+
+ if (clk && name) {
+ for (j = 0; j < pdata->soc_dev_clk_data_cnt; j++) {
+ if (!strcmp(name, pdata->soc_dev_clk_data[j].clk_name)) {
+ clk_add_map(data, clk, pdata->soc_dev_clk_data[j].dev_id,
+ pdata->soc_dev_clk_data[j].clk_id);
+ }
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int _clk_cmp(u32 dev_id, u32 clk_id, const struct clk_map *map)
+{
+ if (map->dev_id == dev_id && map->clk_id == clk_id)
+ return 0;
+ if (map->dev_id > dev_id ||
+ (map->dev_id == dev_id && map->clk_id > clk_id))
+ return -1;
+ return 1;
+}
+
+static int bsearch(u32 dev_id, u32 clk_id, struct clk_map *map, int num)
+{
+ int result;
+ int idx;
+
+ for (idx = 0; idx < num; idx++) {
+ result = _clk_cmp(dev_id, clk_id, &map[idx]);
+
+ if (result == 0)
+ return idx;
+ }
+
+ return -ENOENT;
+}
+
+static int ti_clk_of_xlate(struct clk *clk,
+ struct ofnode_phandle_args *args)
+{
+ struct ti_clk_data *data = dev_get_priv(clk->dev);
+ int idx;
+
+ debug("%s(clk=%p, args_count=%d [0]=%d [1]=%d)\n", __func__, clk,
+ args->args_count, args->args[0], args->args[1]);
+
+ if (args->args_count != 2) {
+ debug("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ if (!data->size)
+ return -EPROBE_DEFER;
+
+ idx = bsearch(args->args[0], args->args[1], data->map, data->size);
+ if (idx < 0)
+ return idx;
+
+ clk->id = idx;
+
+ return 0;
+}
+
+static ulong ti_clk_get_rate(struct clk *clk)
+{
+ struct ti_clk_data *data = dev_get_priv(clk->dev);
+ struct clk *clkp = data->map[clk->id].clk;
+
+ return clk_get_rate(clkp);
+}
+
+static ulong ti_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct ti_clk_data *data = dev_get_priv(clk->dev);
+ struct clk *clkp = data->map[clk->id].clk;
+ int div = 1;
+ ulong child_rate;
+ const struct clk_ops *ops;
+ ulong new_rate, rem;
+ ulong diff, new_diff;
+
+ /*
+ * We must propagate rate change to parent if current clock type
+ * does not allow setting it.
+ */
+ while (clkp) {
+ ops = clkp->dev->driver->ops;
+ if (ops->set_rate)
+ break;
+
+ /*
+ * Store child rate so we can calculate the clock rate
+ * that must be passed to parent
+ */
+ child_rate = clk_get_rate(clkp);
+ clkp = clk_get_parent(clkp);
+ if (clkp) {
+ debug("%s: propagating rate change to parent %s, rate=%u.\n",
+ __func__, clkp->dev->name, (u32)rate / div);
+ div *= clk_get_rate(clkp) / child_rate;
+ }
+ }
+
+ if (!clkp)
+ return -ENOSYS;
+
+ child_rate = clk_get_rate(clkp);
+
+ new_rate = clk_set_rate(clkp, rate / div);
+
+ diff = abs(new_rate - rate / div);
+
+ debug("%s: clk=%s, div=%d, rate=%u, new_rate=%u, diff=%u\n", __func__,
+ clkp->dev->name, div, (u32)rate, (u32)new_rate, (u32)diff);
+
+ /*
+ * If the new rate differs by 50% of the target,
+ * modify parent. This handles typical cases where we have a hsdiv
+ * following directly a PLL
+ */
+
+ if (diff > rate / div / 2) {
+ ulong pll_tgt;
+ int pll_div = 0;
+
+ clk = clkp;
+
+ debug("%s: propagating rate change to parent, rate=%u.\n",
+ __func__, (u32)rate / div);
+
+ clkp = clk_get_parent(clkp);
+
+ if (rate > osc_freq) {
+ if (rate > PLL_MAX_FREQ / 2 && rate < PLL_MAX_FREQ) {
+ pll_tgt = rate;
+ pll_div = 1;
+ } else {
+ for (pll_div = 2; pll_div < PLL_MAX_DIV; pll_div++) {
+ pll_tgt = rate / div * pll_div;
+ if (pll_tgt >= PLL_MIN_FREQ && pll_tgt <= PLL_MAX_FREQ)
+ break;
+ }
+ }
+ } else {
+ pll_tgt = osc_freq;
+ pll_div = rate / div / osc_freq;
+ }
+
+ debug("%s: pll_tgt=%u, rate=%u, div=%u\n", __func__,
+ (u32)pll_tgt, (u32)rate, pll_div);
+
+ clk_set_rate(clkp, pll_tgt);
+
+ return clk_set_rate(clk, rate / div) * div;
+ }
+
+ /*
+ * If the new rate differs by at least 5% of the target,
+ * we must check for rounding error in a divider, so try
+ * set rate with rate + (parent_freq % rate).
+ */
+
+ if (diff > rate / div / 20) {
+ u64 parent_freq = clk_get_parent_rate(clkp);
+
+ rem = parent_freq % rate;
+ new_rate = clk_set_rate(clkp, (rate / div) + rem);
+ new_diff = abs(new_rate - rate / div);
+
+ if (new_diff > diff) {
+ new_rate = clk_set_rate(clkp, rate / div);
+ } else {
+ debug("%s: Using better rate %lu that gives diff %lu\n",
+ __func__, new_rate, new_diff);
+ }
+ }
+
+ return new_rate;
+}
+
+static int ti_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct ti_clk_data *data = dev_get_priv(clk->dev);
+ struct clk *clkp = data->map[clk->id].clk;
+ struct clk *parentp = data->map[parent->id].clk;
+
+ return clk_set_parent(clkp, parentp);
+}
+
+static int ti_clk_enable(struct clk *clk)
+{
+ struct ti_clk_data *data = dev_get_priv(clk->dev);
+ struct clk *clkp = data->map[clk->id].clk;
+
+ return clk_enable(clkp);
+}
+
+static int ti_clk_disable(struct clk *clk)
+{
+ struct ti_clk_data *data = dev_get_priv(clk->dev);
+ struct clk *clkp = data->map[clk->id].clk;
+
+ return clk_disable(clkp);
+}
+
+static const struct udevice_id ti_clk_of_match[] = {
+ { .compatible = "ti,k2g-sci-clk" },
+ { /* sentinel */ },
+};
+
+static const struct clk_ops ti_clk_ops = {
+ .of_xlate = ti_clk_of_xlate,
+ .set_rate = ti_clk_set_rate,
+ .get_rate = ti_clk_get_rate,
+ .enable = ti_clk_enable,
+ .disable = ti_clk_disable,
+ .set_parent = ti_clk_set_parent,
+};
+
+U_BOOT_DRIVER(ti_clk) = {
+ .name = "ti-clk",
+ .id = UCLASS_CLK,
+ .of_match = ti_clk_of_match,
+ .probe = ti_clk_probe,
+ .priv_auto = sizeof(struct ti_clk_data),
+ .ops = &ti_clk_ops,
+};
diff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c
index 6f0fdaa111c..acb9eadf03c 100644
--- a/drivers/clk/ti/clk-sci.c
+++ b/drivers/clk/ti/clk-sci.c
@@ -111,10 +111,12 @@ static ulong ti_sci_clk_set_rate(struct clk *clk, ulong rate)
#endif
ret = cops->set_freq(sci, clk->id, clk->data, 0, rate, ULONG_MAX);
- if (ret)
+ if (ret) {
dev_err(clk->dev, "%s: set_freq failed (%d)\n", __func__, ret);
+ return ret;
+ }
- return ret;
+ return rate;
}
static int ti_sci_clk_set_parent(struct clk *clk, struct clk *parent)
generated by cgit v1.2.3 (git 2.0.4) at 2025-11-05 19:55:16 +0000