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-rw-r--r--drivers/clk/clk-uclass.c59
-rw-r--r--drivers/clk/clk_sandbox_test.c29
-rw-r--r--drivers/clk/clk_zynqmp.c1
-rw-r--r--drivers/clk/renesas/r8a7790-cpg-mssr.c10
-rw-r--r--drivers/clk/renesas/r8a7792-cpg-mssr.c10
-rw-r--r--drivers/clk/renesas/r8a7794-cpg-mssr.c10
-rw-r--r--drivers/clk/uniphier/Kconfig1
-rw-r--r--drivers/clk/uniphier/clk-uniphier-sys.c6
8 files changed, 104 insertions, 22 deletions
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index ad763795d9e..53f418bfddd 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -104,6 +104,39 @@ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
return clk_get_by_indexed_prop(dev, "clocks", index, clk);
}
+int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
+{
+ int i, ret, err, count;
+
+ bulk->count = 0;
+
+ count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
+ if (count < 1)
+ return count;
+
+ bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
+ if (!bulk->clks)
+ return -ENOMEM;
+
+ for (i = 0; i < count; i++) {
+ ret = clk_get_by_index(dev, i, &bulk->clks[i]);
+ if (ret < 0)
+ goto bulk_get_err;
+
+ ++bulk->count;
+ }
+
+ return 0;
+
+bulk_get_err:
+ err = clk_release_all(bulk->clks, bulk->count);
+ if (err)
+ debug("%s: could release all clocks for %p\n",
+ __func__, dev);
+
+ return ret;
+}
+
static int clk_set_default_parents(struct udevice *dev)
{
struct clk clk, parent_clk;
@@ -336,6 +369,19 @@ int clk_enable(struct clk *clk)
return ops->enable(clk);
}
+int clk_enable_bulk(struct clk_bulk *bulk)
+{
+ int i, ret;
+
+ for (i = 0; i < bulk->count; i++) {
+ ret = clk_enable(&bulk->clks[i]);
+ if (ret < 0 && ret != -ENOSYS)
+ return ret;
+ }
+
+ return 0;
+}
+
int clk_disable(struct clk *clk)
{
const struct clk_ops *ops = clk_dev_ops(clk->dev);
@@ -348,6 +394,19 @@ int clk_disable(struct clk *clk)
return ops->disable(clk);
}
+int clk_disable_bulk(struct clk_bulk *bulk)
+{
+ int i, ret;
+
+ for (i = 0; i < bulk->count; i++) {
+ ret = clk_disable(&bulk->clks[i]);
+ if (ret < 0 && ret != -ENOSYS)
+ return ret;
+ }
+
+ return 0;
+}
+
UCLASS_DRIVER(clk) = {
.id = UCLASS_CLK,
.name = "clk",
diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c
index 999100de9d2..d0898815b39 100644
--- a/drivers/clk/clk_sandbox_test.c
+++ b/drivers/clk/clk_sandbox_test.c
@@ -11,6 +11,7 @@
struct sandbox_clk_test {
struct clk clks[SANDBOX_CLK_TEST_ID_COUNT];
+ struct clk_bulk bulk;
};
static const char * const sandbox_clk_test_names[] = {
@@ -34,6 +35,13 @@ int sandbox_clk_test_get(struct udevice *dev)
return 0;
}
+int sandbox_clk_test_get_bulk(struct udevice *dev)
+{
+ struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+ return clk_get_bulk(dev, &sbct->bulk);
+}
+
ulong sandbox_clk_test_get_rate(struct udevice *dev, int id)
{
struct sandbox_clk_test *sbct = dev_get_priv(dev);
@@ -64,6 +72,13 @@ int sandbox_clk_test_enable(struct udevice *dev, int id)
return clk_enable(&sbct->clks[id]);
}
+int sandbox_clk_test_enable_bulk(struct udevice *dev)
+{
+ struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+ return clk_enable_bulk(&sbct->bulk);
+}
+
int sandbox_clk_test_disable(struct udevice *dev, int id)
{
struct sandbox_clk_test *sbct = dev_get_priv(dev);
@@ -74,6 +89,13 @@ int sandbox_clk_test_disable(struct udevice *dev, int id)
return clk_disable(&sbct->clks[id]);
}
+int sandbox_clk_test_disable_bulk(struct udevice *dev)
+{
+ struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+ return clk_disable_bulk(&sbct->bulk);
+}
+
int sandbox_clk_test_free(struct udevice *dev)
{
struct sandbox_clk_test *sbct = dev_get_priv(dev);
@@ -88,6 +110,13 @@ int sandbox_clk_test_free(struct udevice *dev)
return 0;
}
+int sandbox_clk_test_release_bulk(struct udevice *dev)
+{
+ struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+ return clk_release_bulk(&sbct->bulk);
+}
+
static const struct udevice_id sandbox_clk_test_ids[] = {
{ .compatible = "sandbox,clk-test" },
{ }
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 4ef8662af56..d0d6c898bc5 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -702,6 +702,7 @@ static struct clk_ops zynqmp_clk_ops = {
};
static const struct udevice_id zynqmp_clk_ids[] = {
+ { .compatible = "xlnx,zynqmp-clk" },
{ .compatible = "xlnx,zynqmp-clkc" },
{ }
};
diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c
index 33ab9ad7cce..360c02c5fda 100644
--- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
@@ -40,7 +40,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7790_core_clks[] __initconst = {
+static const struct cpg_core_clk r8a7790_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@@ -90,7 +90,7 @@ static const struct cpg_core_clk r8a7790_core_clks[] __initconst = {
DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
};
-static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
+static const struct mssr_mod_clk r8a7790_mod_clks[] = {
DEF_MOD("msiof0", 0, R8A7790_CLK_MP),
DEF_MOD("vcp1", 100, R8A7790_CLK_ZS),
DEF_MOD("vcp0", 101, R8A7790_CLK_ZS),
@@ -209,10 +209,6 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
-static const unsigned int r8a7790_crit_mod_clks[] __initconst = {
- MOD_CLK_ID(408), /* INTC-SYS (GIC) */
-};
-
/*
* CPG Clock Data
*/
@@ -235,7 +231,7 @@ static const unsigned int r8a7790_crit_mod_clks[] __initconst = {
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
};
diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index 260bb892d60..4ba18b18bea 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -39,7 +39,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
+static const struct cpg_core_clk r8a7792_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
@@ -78,7 +78,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1),
};
-static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
+static const struct mssr_mod_clk r8a7792_mod_clks[] = {
DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
DEF_MOD("jpu", 106, R8A7792_CLK_M2),
DEF_MOD("tmu1", 111, R8A7792_CLK_P),
@@ -152,10 +152,6 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
};
-static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
- MOD_CLK_ID(408), /* INTC-SYS (GIC) */
-};
-
/*
* CPG Clock Data
*/
@@ -179,7 +175,7 @@ static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
{ 1, 208, 106, 200 },
{ 1, 208, 88, 200 },
{ 1, 156, 80, 150 },
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index 90bac3deedb..e8f57c3d015 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -40,7 +40,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
+static const struct cpg_core_clk r8a7794_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@@ -85,7 +85,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
};
-static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
+static const struct mssr_mod_clk r8a7794_mod_clks[] = {
DEF_MOD("msiof0", 0, R8A7794_CLK_MP),
DEF_MOD("vcp0", 101, R8A7794_CLK_ZS),
DEF_MOD("vpc0", 103, R8A7794_CLK_ZS),
@@ -188,10 +188,6 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
DEF_MOD("scifa5", 1108, R8A7794_CLK_MP),
};
-static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
- MOD_CLK_ID(408), /* INTC-SYS (GIC) */
-};
-
/*
* CPG Clock Data
*/
@@ -210,7 +206,7 @@ static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] = {
{ 1, 208, 88, 200 },
{ 1, 156, 66, 150 },
{ 2, 240, 102, 230 },
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index 3666d8414ce..a26ca8c1cda 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -2,7 +2,6 @@ config CLK_UNIPHIER
def_bool y
depends on ARCH_UNIPHIER
select CLK
- select SPL_CLK if SPL
help
Support for clock controllers on UniPhier SoCs.
Say Y if you want to control clocks provided by System Control
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index c852c78659b..0230a18608a 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -21,7 +21,10 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\
defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
UNIPHIER_LD4_SYS_CLK_NAND(2),
+ UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */
+ UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */
UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */
+ UNIPHIER_CLK_GATE_SIMPLE(10, 0x2260, 0), /* ether-phy (Pro4) */
UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6), /* gio (Pro4, Pro5) */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */
UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */
@@ -34,6 +37,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
UNIPHIER_LD11_SYS_CLK_NAND(2),
+ UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */
UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */
UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */
@@ -45,6 +49,8 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
UNIPHIER_LD11_SYS_CLK_NAND(2),
+ UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */
+ UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */
UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */
UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5), /* usb31-0 (gio1) */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6), /* usb31-1 (gio1-1) */
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-26 18:36:57 +0000