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-rw-r--r--drivers/clk/sunxi/Kconfig7
-rw-r--r--drivers/clk/sunxi/Makefile1
-rw-r--r--drivers/clk/sunxi/clk_a10.c2
-rw-r--r--drivers/clk/sunxi/clk_a10s.c2
-rw-r--r--drivers/clk/sunxi/clk_a23.c2
-rw-r--r--drivers/clk/sunxi/clk_a31.c2
-rw-r--r--drivers/clk/sunxi/clk_a64.c4
-rw-r--r--drivers/clk/sunxi/clk_a80.c2
-rw-r--r--drivers/clk/sunxi/clk_a83t.c2
-rw-r--r--drivers/clk/sunxi/clk_f1c100s.c74
-rw-r--r--drivers/clk/sunxi/clk_h3.c4
-rw-r--r--drivers/clk/sunxi/clk_h6.c4
-rw-r--r--drivers/clk/sunxi/clk_h616.c4
-rw-r--r--drivers/clk/sunxi/clk_h6_r.c6
-rw-r--r--drivers/clk/sunxi/clk_r40.c2
-rw-r--r--drivers/clk/sunxi/clk_sunxi.c3
-rw-r--r--drivers/clk/sunxi/clk_v3s.c2
17 files changed, 121 insertions, 2 deletions
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index f19908113e1..bf11fad6eef 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -10,6 +10,13 @@ config CLK_SUNXI
if CLK_SUNXI
+config CLK_SUNIV_F1C100S
+ bool "Clock driver for Allwinner F1C100s"
+ default MACH_SUNIV
+ help
+ This enables common clock driver support for platforms based
+ on Allwinner F1C100s SoC.
+
config CLK_SUN4I_A10
bool "Clock driver for Allwinner A10/A20"
default MACH_SUN4I || MACH_SUN7I
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 48a48a2f000..895da02ebea 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
obj-$(CONFIG_CLK_SUNXI) += clk_sun6i_rtc.o
+obj-$(CONFIG_CLK_SUNIV_F1C100S) += clk_f1c100s.o
obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index 90b929d3d32..db92848aafd 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -31,6 +31,8 @@ static struct ccu_clk_gate a10_gates[] = {
[CLK_AHB_GMAC] = GATE(0x064, BIT(17)),
+ [CLK_APB0_PIO] = GATE(0x068, BIT(5)),
+
[CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
[CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
[CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index addf4f4d5cd..0c6564ef3b6 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -25,6 +25,8 @@ static struct ccu_clk_gate a10s_gates[] = {
[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
[CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
+ [CLK_APB0_PIO] = GATE(0x068, BIT(5)),
+
[CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
[CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
[CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index c45d2c35298..0280fb51e2d 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -23,6 +23,8 @@ static struct ccu_clk_gate a23_gates[] = {
[CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
[CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
+ [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
+
[CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 251fc3b705e..26d25f32408 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -30,6 +30,8 @@ static struct ccu_clk_gate a31_gates[] = {
[CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)),
[CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),
+ [CLK_APB1_PIO] = GATE(0x068, BIT(5)),
+
[CLK_APB2_I2C0] = GATE(0x06c, BIT(0)),
[CLK_APB2_I2C1] = GATE(0x06c, BIT(1)),
[CLK_APB2_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 1004a795033..cbb9168edb9 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -14,6 +14,8 @@
#include <linux/bitops.h>
static const struct ccu_clk_gate a64_gates[] = {
+ [CLK_PLL_PERIPH0] = GATE(0x028, BIT(31)),
+
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
@@ -26,6 +28,8 @@ static const struct ccu_clk_gate a64_gates[] = {
[CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
[CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
+ [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
+
[CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
index 8a0834d83a3..1ee1f99a8f4 100644
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -25,6 +25,8 @@ static const struct ccu_clk_gate a80_gates[] = {
[CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
[CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
+ [CLK_BUS_PIO] = GATE(0x590, BIT(5)),
+
[CLK_BUS_I2C0] = GATE(0x594, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x594, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x594, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 8c6043f51e2..4b57434cfaa 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -25,6 +25,8 @@ static struct ccu_clk_gate a83t_gates[] = {
[CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
[CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
+ [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
+
[CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_f1c100s.c b/drivers/clk/sunxi/clk_f1c100s.c
new file mode 100644
index 00000000000..72cf8a6e5c0
--- /dev/null
+++ b/drivers/clk/sunxi/clk_f1c100s.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+)
+/*
+ * Copyright (C) 2019 George Hilliard <thirtythreeforty@gmail.com>.
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
+#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+
+static struct ccu_clk_gate f1c100s_gates[] = {
+ [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
+ [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
+ [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
+ [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
+ [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
+
+ [CLK_BUS_I2C0] = GATE(0x068, BIT(16)),
+ [CLK_BUS_I2C1] = GATE(0x068, BIT(17)),
+ [CLK_BUS_I2C2] = GATE(0x068, BIT(18)),
+ [CLK_BUS_PIO] = GATE(0x068, BIT(19)),
+
+ [CLK_BUS_UART0] = GATE(0x06c, BIT(20)),
+ [CLK_BUS_UART1] = GATE(0x06c, BIT(21)),
+ [CLK_BUS_UART2] = GATE(0x06c, BIT(22)),
+
+ [CLK_USB_PHY0] = GATE(0x0cc, BIT(1)),
+};
+
+static struct ccu_reset f1c100s_resets[] = {
+ [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
+
+ [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
+ [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
+ [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
+ [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
+ [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
+
+ [RST_BUS_I2C0] = RESET(0x2d0, BIT(16)),
+ [RST_BUS_I2C1] = RESET(0x2d0, BIT(17)),
+ [RST_BUS_I2C2] = RESET(0x2d0, BIT(18)),
+ [RST_BUS_UART0] = RESET(0x2d0, BIT(20)),
+ [RST_BUS_UART1] = RESET(0x2d0, BIT(21)),
+ [RST_BUS_UART2] = RESET(0x2d0, BIT(22)),
+};
+
+static const struct ccu_desc f1c100s_ccu_desc = {
+ .gates = f1c100s_gates,
+ .resets = f1c100s_resets,
+};
+
+static int f1c100s_clk_bind(struct udevice *dev)
+{
+ return sunxi_reset_bind(dev, ARRAY_SIZE(f1c100s_resets));
+}
+
+static const struct udevice_id f1c100s_clk_ids[] = {
+ { .compatible = "allwinner,suniv-f1c100s-ccu",
+ .data = (ulong)&f1c100s_ccu_desc },
+ { }
+};
+
+U_BOOT_DRIVER(clk_suniv_f1c100s) = {
+ .name = "suniv_f1c100s_ccu",
+ .id = UCLASS_CLK,
+ .of_match = f1c100s_clk_ids,
+ .priv_auto = sizeof(struct ccu_priv),
+ .ops = &sunxi_clk_ops,
+ .probe = sunxi_clk_probe,
+ .bind = f1c100s_clk_bind,
+};
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 59afba53eef..08a830bd188 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -14,6 +14,8 @@
#include <linux/bitops.h>
static struct ccu_clk_gate h3_gates[] = {
+ [CLK_PLL_PERIPH0] = GATE(0x028, BIT(31)),
+
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
@@ -30,6 +32,8 @@ static struct ccu_clk_gate h3_gates[] = {
[CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
[CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
+ [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
+
[CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index 4a53788352c..b3202342932 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -14,6 +14,10 @@
#include <linux/bitops.h>
static struct ccu_clk_gate h6_gates[] = {
+ [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31)),
+
+ [CLK_APB1] = GATE_DUMMY,
+
[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
index af97d3bb9f7..80099727def 100644
--- a/drivers/clk/sunxi/clk_h616.c
+++ b/drivers/clk/sunxi/clk_h616.c
@@ -13,6 +13,10 @@
#include <linux/bitops.h>
static struct ccu_clk_gate h616_gates[] = {
+ [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31) | BIT(27)),
+
+ [CLK_APB1] = GATE_DUMMY,
+
[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_h6_r.c b/drivers/clk/sunxi/clk_h6_r.c
index b9e527e16ac..c592886a258 100644
--- a/drivers/clk/sunxi/clk_h6_r.c
+++ b/drivers/clk/sunxi/clk_h6_r.c
@@ -11,6 +11,8 @@
#include <linux/bitops.h>
static struct ccu_clk_gate h6_r_gates[] = {
+ [CLK_R_APB1] = GATE_DUMMY,
+
[CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)),
[CLK_R_APB1_TWD] = GATE(0x12c, BIT(0)),
[CLK_R_APB1_PWM] = GATE(0x13c, BIT(0)),
@@ -50,8 +52,8 @@ static const struct udevice_id h6_r_clk_ids[] = {
{ }
};
-U_BOOT_DRIVER(clk_sun6i_h6_r) = {
- .name = "sun6i_h6_r_ccu",
+U_BOOT_DRIVER(clk_sun50i_h6_r) = {
+ .name = "sun50i_h6_r_ccu",
.id = UCLASS_CLK,
.of_match = h6_r_clk_ids,
.priv_auto = sizeof(struct ccu_priv),
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index 4d5b69a9765..45633a2a524 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -32,6 +32,8 @@ static struct ccu_clk_gate r40_gates[] = {
[CLK_BUS_GMAC] = GATE(0x064, BIT(17)),
+ [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
+
[CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
index 9673b58a492..9a21367a5d0 100644
--- a/drivers/clk/sunxi/clk_sunxi.c
+++ b/drivers/clk/sunxi/clk_sunxi.c
@@ -27,6 +27,9 @@ static int sunxi_set_gate(struct clk *clk, bool on)
const struct ccu_clk_gate *gate = priv_to_gate(priv, clk->id);
u32 reg;
+ if ((gate->flags & CCU_CLK_F_DUMMY_GATE))
+ return 0;
+
if (!(gate->flags & CCU_CLK_F_IS_VALID)) {
printf("%s: (CLK#%ld) unhandled\n", __func__, clk->id);
return 0;
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index cce5c658ca0..67d215cbba8 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -20,6 +20,8 @@ static struct ccu_clk_gate v3s_gates[] = {
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_OTG] = GATE(0x060, BIT(24)),
+ [CLK_BUS_PIO] = GATE(0x068, BIT(5)),
+
[CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-05 00:37:10 +0000