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-rw-r--r--drivers/clk/mediatek/Makefile1
-rw-r--r--drivers/clk/mediatek/clk-mt7629.c14
-rw-r--r--drivers/clk/mediatek/clk-mt7981.c1
-rw-r--r--drivers/clk/mediatek/clk-mt7986.c1
-rw-r--r--drivers/clk/mediatek/clk-mt7987.c848
-rw-r--r--drivers/clk/mediatek/clk-mt7988.c1
-rw-r--r--drivers/clk/qcom/Kconfig16
-rw-r--r--drivers/clk/qcom/Makefile2
-rw-r--r--drivers/clk/qcom/clock-qcom.c19
-rw-r--r--drivers/clk/qcom/clock-qcom.h2
-rw-r--r--drivers/clk/qcom/clock-sa8775p.c142
-rw-r--r--drivers/clk/qcom/clock-sm8550.c36
-rw-r--r--drivers/clk/qcom/clock-sm8650.c36
-rw-r--r--drivers/clk/qcom/clock-x1e80100.c402
-rw-r--r--drivers/clk/rockchip/clk_rk3288.c8
-rw-r--r--drivers/clk/stm32/clk-stm32h7.c3
16 files changed, 1527 insertions, 5 deletions
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index e631f79e4dd..e412c92cafc 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o
obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o
obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o
+obj-$(CONFIG_TARGET_MT7987) += clk-mt7987.o
obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index 380ab9b9b0b..94fc5e51456 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -574,6 +574,18 @@ static const struct mtk_clk_tree mt7629_clk_tree = {
.muxes = top_muxes,
};
+static const struct mtk_clk_tree mt7629_peri_clk_tree = {
+ .xtal_rate = 40 * MHZ,
+ .xtal2_rate = 20 * MHZ,
+ .gates_offs = CLK_PERI_PWM1_PD,
+ .fdivs_offs = CLK_TOP_TO_USB3_SYS,
+ .muxes_offs = CLK_TOP_AXI_SEL,
+ .plls = apmixed_plls,
+ .fclks = top_fixed_clks,
+ .fdivs = top_fixed_divs,
+ .muxes = top_muxes,
+};
+
static int mt7629_mcucfg_probe(struct udevice *dev)
{
void __iomem *base;
@@ -619,7 +631,7 @@ static int mt7629_infracfg_probe(struct udevice *dev)
static int mt7629_pericfg_probe(struct udevice *dev)
{
- return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs);
+ return mtk_common_clk_gate_init(dev, &mt7629_peri_clk_tree, peri_cgs);
}
static int mt7629_ethsys_probe(struct udevice *dev)
diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c
index 97073918006..60814652322 100644
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -359,6 +359,7 @@ static const struct mtk_parent infra_pcie_parents[] = {
.id = _id, .mux_reg = (_reg) + 0x8, \
.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
.mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
+ .gate_shift = -1, .upd_shift = -1, \
.parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
}
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index c5cc77243d0..f9d6f9c1749 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -366,6 +366,7 @@ static const struct mtk_parent infra_pcie_parents[] = {
.id = _id, .mux_reg = (_reg) + 0x8, \
.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
.mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
+ .gate_shift = -1, .upd_shift = -1, \
.parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
}
diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c
new file mode 100644
index 00000000000..173686a38e8
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7987.c
@@ -0,0 +1,848 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7987 SoC
+ *
+ * Copyright (C) 2024 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <dm.h>
+#include <log.h>
+#include <asm/arch-mediatek/reset.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mediatek,mt7987-clk.h>
+#include <linux/bitops.h>
+
+#include "clk-mtk.h"
+
+#define MT7987_XTAL_RATE (40 * MHZ)
+#define MT7987_CLK_PDN 0x250
+#define MT7987_CLK_PDN_EN_WRITE BIT(31)
+
+#define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)
+
+#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
+
+/* FIXED PLLS */
+static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
+ FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
+ FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
+ FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
+ FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
+ FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
+ FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
+ FIXED_CLK(CLK_APMIXED_ARM_LL, CLK_XTAL, 2000000000),
+ FIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 384000000),
+};
+
+static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = {
+ .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
+ .fclks = apmixedsys_mtk_plls,
+ .flags = CLK_APMIXED,
+ .xtal_rate = 40 * MHZ,
+};
+
+static const struct udevice_id mt7987_fixed_pll_compat[] = {
+ { .compatible = "mediatek,mt7987-fixed-plls" },
+ { .compatible = "mediatek,mt7987-apmixedsys" },
+ {}
+};
+
+static int mt7987_fixed_pll_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt7987_fixed_pll_clk_tree);
+}
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ .name = "mt7987-clock-fixed-pll",
+ .id = UCLASS_CLK,
+ .of_match = mt7987_fixed_pll_compat,
+ .probe = mt7987_fixed_pll_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+/* TOPCKGEN FIXED DIV */
+static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
+ PLL_FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", CLK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", CLK_APMIXED_MPLL, 1, 3),
+ PLL_FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", CLK_APMIXED_MPLL, 1, 6),
+ PLL_FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", CLK_APMIXED_MPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", CLK_APMIXED_MPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", CLK_APMIXED_MPLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_CB_APLL2_D4, "cb_apll2_d4", CLK_APMIXED_APLL2, 1, 4),
+ PLL_FACTOR(CLK_TOP_CB_NET1_D3, "cb_net1_d3", CLK_APMIXED_NET1PLL, 1, 3),
+ PLL_FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", CLK_APMIXED_NET1PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", CLK_APMIXED_NET1PLL, 1, 5),
+ PLL_FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", CLK_APMIXED_NET1PLL, 1, 10),
+ PLL_FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", CLK_APMIXED_NET1PLL, 1, 20),
+ PLL_FACTOR(CLK_TOP_CB_NET1_D7, "cb_net1_d7", CLK_APMIXED_NET1PLL, 1, 7),
+ PLL_FACTOR(CLK_TOP_NET1_D7_D2, "net1_d7_d2", CLK_APMIXED_NET1PLL, 1, 14),
+ PLL_FACTOR(CLK_TOP_NET1_D7_D4, "net1_d7_d4", CLK_APMIXED_NET1PLL, 1, 28),
+ PLL_FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", CLK_APMIXED_NET1PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", CLK_APMIXED_NET1PLL, 1, 32),
+ PLL_FACTOR(CLK_TOP_NET1_D8_D8, "net1_d8_d8", CLK_APMIXED_NET1PLL, 1, 64),
+ PLL_FACTOR(CLK_TOP_NET1_D8_D16, "net1_d8_d16", CLK_APMIXED_NET1PLL, 1, 128),
+ PLL_FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", CLK_APMIXED_NET2PLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", CLK_APMIXED_NET2PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", CLK_APMIXED_NET2PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_NET2_D4_D8, "net2_d4_d8", CLK_APMIXED_NET2PLL, 1, 32),
+ PLL_FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", CLK_APMIXED_NET2PLL, 1, 6),
+ PLL_FACTOR(CLK_TOP_NET2_D7_D2, "net2_d7_d2", CLK_APMIXED_NET2PLL, 1, 14),
+ PLL_FACTOR(CLK_TOP_CB_NET2_D8, "cb_net2_d8", CLK_APMIXED_NET2PLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_MSDC_D2, "msdc_d2", CLK_APMIXED_MSDCPLL, 1, 2),
+ XTAL_FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1),
+ TOP_FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CLK_TOP_CB_CKSQ_40M, 1, 2),
+ TOP_FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", CLK_TOP_CB_CKSQ_40M, 1, 1250),
+ TOP_FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CLK_TOP_CB_CKSQ_40M, 1, 1221),
+};
+
+/* TOPCKGEN MUX PARENTS */
+#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED)
+#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
+
+/* CLK_TOP_NETSYS_SEL (netsys_sel) in topckgen */
+static const struct mtk_parent netsys_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_CB_NET2_D2)
+};
+
+/* CLK_TOP_NETSYS_500M_SEL (netsys_500m_sel) in topckgen */
+static const struct mtk_parent netsys_500m_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_CB_NET1_D5),
+ TOP_PARENT(CLK_TOP_NET1_D5_D2)
+};
+
+/* CLK_TOP_NETSYS_2X_SEL (netsys_2x_sel) in topckgen */
+static const struct mtk_parent netsys_2x_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ APMIXED_PARENT(CLK_APMIXED_NET2PLL)
+};
+
+/* CLK_TOP_ETH_GMII_SEL (eth_gmii_sel) in topckgen */
+static const struct mtk_parent eth_gmii_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_NET1_D5_D4)
+};
+
+/* CLK_TOP_EIP_SEL (eip_sel) in topckgen */
+static const struct mtk_parent eip_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_CB_NET1_D3),
+ APMIXED_PARENT(CLK_APMIXED_NET2PLL),
+ TOP_PARENT(CLK_TOP_CB_NET1_D4),
+ TOP_PARENT(CLK_TOP_CB_NET1_D5)
+};
+
+/* CLK_TOP_AXI_INFRA_SEL (axi_infra_sel) in topckgen */
+static const struct mtk_parent axi_infra_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_NET1_D8_D2)
+};
+
+/* CLK_TOP_UART_SEL (uart_sel) in topckgen */
+static const struct mtk_parent uart_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_CB_M_D8),
+ TOP_PARENT(CLK_TOP_M_D8_D2)
+};
+
+/* CLK_TOP_EMMC_250M_SEL (emmc_250m_sel) in topckgen */
+static const struct mtk_parent emmc_250m_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_NET1_D5_D2),
+ TOP_PARENT(CLK_TOP_NET1_D7_D2)
+};
+
+/* CLK_TOP_EMMC_400M_SEL (emmc_400m_sel) in topckgen */
+static const struct mtk_parent emmc_400m_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ APMIXED_PARENT(CLK_APMIXED_MSDCPLL),
+ TOP_PARENT(CLK_TOP_CB_NET1_D7),
+ TOP_PARENT(CLK_TOP_CB_M_D2),
+ TOP_PARENT(CLK_TOP_NET1_D7_D2),
+ TOP_PARENT(CLK_TOP_CB_NET2_D6)
+};
+
+/* CLK_TOP_SPI_SEL (spi_sel) in topckgen */
+static const struct mtk_parent spi_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_CB_M_D2),
+ TOP_PARENT(CLK_TOP_NET1_D7_D2),
+ TOP_PARENT(CLK_TOP_NET1_D8_D2),
+ TOP_PARENT(CLK_TOP_CB_NET2_D6),
+ TOP_PARENT(CLK_TOP_NET1_D5_D4),
+ TOP_PARENT(CLK_TOP_CB_M_D4),
+ TOP_PARENT(CLK_TOP_NET1_D8_D4)
+};
+
+/* CLK_TOP_NFI_SEL (nfi_sel) in topckgen */
+static const struct mtk_parent nfi_parents[] = {
+ TOP_PARENT(CLK_TOP_CKSQ_40M_D2),
+ TOP_PARENT(CLK_TOP_NET1_D8_D2),
+ TOP_PARENT(CLK_TOP_CB_M_D3),
+ TOP_PARENT(CLK_TOP_NET1_D5_D4),
+ TOP_PARENT(CLK_TOP_CB_M_D4),
+ TOP_PARENT(CLK_TOP_NET1_D7_D4),
+ TOP_PARENT(CLK_TOP_NET1_D8_D4),
+ TOP_PARENT(CLK_TOP_M_D3_D2),
+ TOP_PARENT(CLK_TOP_NET2_D7_D2),
+ TOP_PARENT(CLK_TOP_CB_M_D8)
+};
+
+/* CLK_TOP_PWM_SEL (pwm_sel) in topckgen */
+static const struct mtk_parent pwm_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_NET1_D8_D2),
+ TOP_PARENT(CLK_TOP_NET1_D5_D4),
+ TOP_PARENT(CLK_TOP_CB_M_D4),
+ TOP_PARENT(CLK_TOP_M_D8_D2),
+ TOP_PARENT(CLK_TOP_CB_RTC_32K)
+};
+
+/* CLK_TOP_I2C_SEL (i2c_sel) in topckgen */
+static const struct mtk_parent i2c_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_NET1_D5_D4),
+ TOP_PARENT(CLK_TOP_CB_M_D4),
+ TOP_PARENT(CLK_TOP_NET1_D8_D4)
+};
+
+/* CLK_TOP_PCIE_MBIST_250M_SEL (pcie_mbist_250m_sel) in topckgen */
+static const struct mtk_parent pcie_mbist_250m_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_NET1_D5_D2)
+};
+
+/* CLK_TOP_PEXTP_TL_SEL (pextp_tl_ck_sel) in topckgen */
+static const struct mtk_parent pextp_tl_ck_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_CB_NET2_D6),
+ TOP_PARENT(CLK_TOP_NET1_D7_D4),
+ TOP_PARENT(CLK_TOP_M_D8_D2),
+ TOP_PARENT(CLK_TOP_CB_RTC_32K)
+};
+
+/* CLK_TOP_AUD_SEL (aud_sel) in topckgen */
+static const struct mtk_parent aud_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ APMIXED_PARENT(CLK_APMIXED_APLL2)
+};
+
+/* CLK_TOP_A1SYS_SEL (a1sys_sel) in topckgen */
+static const struct mtk_parent a1sys_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_CB_APLL2_D4)
+};
+
+/* CLK_TOP_AUD_L_SEL (aud_l_sel) in topckgen */
+static const struct mtk_parent aud_l_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ APMIXED_PARENT(CLK_APMIXED_APLL2),
+ TOP_PARENT(CLK_TOP_M_D8_D2)
+};
+
+/* CLK_TOP_USB_PHY_SEL (usb_phy_sel) in topckgen */
+static const struct mtk_parent usb_phy_parents[] = {
+ TOP_PARENT(CLK_TOP_CKSQ_40M_D2),
+ TOP_PARENT(CLK_TOP_M_D8_D2)
+};
+
+/* CLK_TOP_SGM_0_SEL (sgm_0_sel) in topckgen */
+static const struct mtk_parent sgm_0_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ APMIXED_PARENT(CLK_APMIXED_SGMPLL)
+};
+
+/* CLK_TOP_SGM_SBUS_0_SEL (sgm_sbus_0_sel) in topckgen */
+static const struct mtk_parent sgm_sbus_0_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_NET1_D8_D4)
+};
+
+/* CLK_TOP_SYSAPB_SEL (sysapb_sel) in topckgen */
+static const struct mtk_parent sysapb_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_M_D3_D2)
+};
+
+/* CLK_TOP_ETH_REFCK_50M_SEL (eth_refck_50m_sel) in topckgen */
+static const struct mtk_parent eth_refck_50m_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_NET2_D4_D4)
+};
+
+/* CLK_TOP_ETH_SYS_200M_SEL (eth_sys_200m_sel) in topckgen */
+static const struct mtk_parent eth_sys_200m_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_CB_NET2_D4)
+};
+
+/* CLK_TOP_ETH_XGMII_SEL (eth_xgmii_sel) in topckgen */
+static const struct mtk_parent eth_xgmii_parents[] = {
+ TOP_PARENT(CLK_TOP_CKSQ_40M_D2),
+ TOP_PARENT(CLK_TOP_NET1_D8_D8),
+ TOP_PARENT(CLK_TOP_NET1_D8_D16)
+};
+
+/* CLK_TOP_DRAMC_MD32_SEL (dramc_md32_sel) in topckgen */
+static const struct mtk_parent dramc_md32_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_CB_M_D2),
+ APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL)
+};
+
+/* CLK_TOP_DA_XTP_GLB_P0_SEL (da_xtp_glb_p0_sel) in topckgen */
+static const struct mtk_parent da_xtp_glb_p0_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_CB_NET2_D8)
+};
+
+/* CLK_TOP_DA_CKM_XTAL_SEL (da_ckm_xtal_sel) in topckgen */
+static const struct mtk_parent da_ckm_xtal_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_M_D8_D2)
+};
+
+/* CLK_TOP_ETH_MII_SEL (eth_mii_sel) in topckgen */
+static const struct mtk_parent eth_mii_parents[] = {
+ TOP_PARENT(CLK_TOP_CKSQ_40M_D2),
+ TOP_PARENT(CLK_TOP_NET2_D4_D8)
+};
+
+/* CLK_TOP_EMMC_200M_SEL (emmc_200m_sel) in topckgen */
+static const struct mtk_parent emmc_200m_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_MSDC_D2),
+ TOP_PARENT(CLK_TOP_NET1_D7_D2),
+ TOP_PARENT(CLK_TOP_CB_NET2_D6),
+ TOP_PARENT(CLK_TOP_NET1_D7_D4)
+};
+
+#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
+ _shift, _width, _gate, _upd_ofs, _upd) \
+ { \
+ .id = (_id), .mux_reg = (_mux_ofs), \
+ .mux_set_reg = (_mux_set_ofs), .mux_clr_reg = (_mux_clr_ofs), \
+ .upd_reg = (_upd_ofs), .upd_shift = (_upd), \
+ .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \
+ .gate_reg = (_mux_ofs), .gate_shift = (_gate), \
+ .parent_flags = (_parents), \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
+ }
+
+/* TOPCKGEN MUX_GATE */
+static const struct mtk_composite topckgen_mtk_muxes[] = {
+ TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
+ 0x000, 0x004, 0x008, 0, 1, 7, 0x1C0, 0),
+ TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
+ netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2, 15, 0x1C0, 1),
+ TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents,
+ 0x000, 0x004, 0x008, 16, 1, 23, 0x1C0, 2),
+ TOP_MUX(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents,
+ 0x000, 0x004, 0x008, 24, 1, 31, 0x1C0, 3),
+ TOP_MUX(CLK_TOP_EIP_SEL, "eip_sel", eip_parents,
+ 0x010, 0x014, 0x018, 0, 3, 7, 0x1C0, 4),
+ TOP_MUX(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents,
+ 0x010, 0x014, 0x018, 8, 1, 15, 0x1C0, 5),
+ TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
+ 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
+ TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents,
+ 0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7),
+ TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents,
+ 0x020, 0x024, 0x028, 0, 3, 7, 0x1C0, 8),
+ TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
+ 0x020, 0x024, 0x028, 8, 3, 15, 0x1C0, 9),
+ TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
+ 0x020, 0x024, 0x028, 16, 3, 23, 0x1C0, 10),
+ TOP_MUX(CLK_TOP_NFI_SEL, "nfi_sel", nfi_parents,
+ 0x020, 0x024, 0x028, 24, 4, 31, 0x1C0, 11),
+ TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
+ 0x030, 0x034, 0x038, 0, 3, 7, 0x1C0, 12),
+ TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
+ 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
+ TOP_MUX(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
+ pcie_mbist_250m_parents, 0x030, 0x034, 0x038, 16, 1, 23, 0x1C0, 14),
+ TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
+ 0x030, 0x034, 0x038, 24, 3, 31, 0x1C0, 15),
+ TOP_MUX(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
+ pextp_tl_ck_parents, 0x040, 0x044, 0x048, 0, 3, 7, 0x1C0, 16),
+ TOP_MUX(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents,
+ 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
+ TOP_MUX(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents,
+ 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
+ TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents,
+ 0x040, 0x044, 0x048, 24, 1, 31, 0x1C0, 19),
+ TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
+ 0x050, 0x054, 0x058, 0, 1, 7, 0x1C0, 20),
+ TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
+ 0x050, 0x054, 0x058, 8, 2, 15, 0x1C0, 21),
+ TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents,
+ 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
+ TOP_MUX(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", usb_phy_parents,
+ 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
+ TOP_MUX(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents,
+ 0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24),
+ TOP_MUX(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", sgm_sbus_0_parents,
+ 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
+ TOP_MUX(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents,
+ 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
+ TOP_MUX(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", sgm_sbus_0_parents,
+ 0x060, 0x064, 0x068, 24, 1, 31, 0x1C0, 27),
+ TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents,
+ 0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28),
+ TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
+ 0x070, 0x074, 0x078, 8, 1, 15, 0x1C0, 29),
+ TOP_MUX(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
+ eth_refck_50m_parents, 0x070, 0x074, 0x078, 16, 1, 23, 0x1C0, 30),
+ TOP_MUX(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
+ eth_sys_200m_parents, 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0),
+ TOP_MUX(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents,
+ 0x080, 0x084, 0x088, 0, 1, 7, 0x1C4, 1),
+ TOP_MUX(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents,
+ 0x080, 0x084, 0x088, 8, 2, 15, 0x1C4, 2),
+ TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", usb_phy_parents,
+ 0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3),
+ TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
+ 0x080, 0x084, 0x088, 24, 2, 31, 0x1C4, 4),
+ TOP_MUX(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel",
+ usb_phy_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
+ TOP_MUX(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", usb_phy_parents,
+ 0x090, 0x094, 0x098, 8, 1, 15, 0x1C4, 6),
+ TOP_MUX(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", usb_phy_parents,
+ 0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7),
+ TOP_MUX(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
+ da_xtp_glb_p0_parents, 0x090, 0x094, 0x098, 24, 1, 31, 0x1C4, 8),
+ TOP_MUX(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
+ da_xtp_glb_p0_parents, 0x0A0, 0x0A4, 0x0A8, 0, 1, 7, 0x1C4, 9),
+ TOP_MUX(CLK_TOP_CKM_SEL, "ckm_sel", usb_phy_parents,
+ 0x0A0, 0x0A4, 0x0A8, 8, 1, 15, 0x1C4, 10),
+ TOP_MUX(CLK_TOP_DA_CKM_XTAL_SEL, "da_ckm_xtal_sel",
+ da_ckm_xtal_parents, 0x0A0, 0x0A4, 0x0A8, 16, 1, 23, 0x1C4, 11),
+ TOP_MUX(CLK_TOP_PEXTP_SEL, "pextp_sel", usb_phy_parents,
+ 0x0A0, 0x0A4, 0x0A8, 24, 1, 31, 0x1C4, 12),
+ TOP_MUX(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents,
+ 0x0B0, 0x0B4, 0x0B8, 0, 1, 7, 0x1C4, 13),
+ TOP_MUX(CLK_TOP_EMMC_200M_SEL, "emmc_200m_sel", emmc_200m_parents,
+ 0x0B0, 0x0B4, 0x0B8, 8, 3, 15, 0x1C4, 14),
+};
+
+static const struct mtk_clk_tree mt7987_topckgen_clk_tree = {
+ .muxes_offs = CLK_TOP_NETSYS_SEL,
+ .fdivs = topckgen_mtk_fixed_factors,
+ .muxes = topckgen_mtk_muxes,
+ .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,
+ .xtal_rate = MT7987_XTAL_RATE,
+};
+
+static const struct udevice_id mt7987_topckgen_compat[] = {
+ { .compatible = "mediatek,mt7987-topckgen" },
+ {}
+};
+
+static int mt7987_topckgen_probe(struct udevice *dev)
+{
+ struct mtk_clk_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+
+ writel(MT7987_CLK_PDN_EN_WRITE, priv->base + MT7987_CLK_PDN);
+ return mtk_common_clk_init(dev, &mt7987_topckgen_clk_tree);
+}
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+ .name = "mt7987-clock-topckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt7987_topckgen_compat,
+ .probe = mt7987_topckgen_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+/* INFRASYS MUX PARENTS */
+
+/* CLK_INFRA_MUX_UART0_SEL (infra_mux_uart0_sel) in infracfg */
+static const int infra_mux_uart0_parents[] = {
+ CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_UART_SEL
+};
+
+/* CLK_INFRA_MUX_UART1_SEL (infra_mux_uart1_sel) in infracfg */
+static const int infra_mux_uart1_parents[] = {
+ CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_UART_SEL
+};
+
+/* CLK_INFRA_MUX_UART2_SEL (infra_mux_uart2_sel) in infracfg */
+static const int infra_mux_uart2_parents[] = {
+ CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_UART_SEL
+};
+
+/* CLK_INFRA_MUX_SPI0_SEL (infra_mux_spi0_sel) in infracfg */
+static const int infra_mux_spi0_parents[] = {
+ CLK_TOP_I2C_SEL,
+ CLK_TOP_SPI_SEL
+};
+
+/* CLK_INFRA_MUX_SPI1_SEL (infra_mux_spi1_sel) in infracfg */
+static const int infra_mux_spi1_parents[] = {
+ CLK_TOP_I2C_SEL,
+ CLK_TOP_SPIM_MST_SEL
+};
+
+/* CLK_INFRA_MUX_SPI2_BCK_SEL (infra_mux_spi2_bck_sel) in infracfg */
+static const int infra_mux_spi2_bck_parents[] = {
+ CLK_TOP_I2C_SEL,
+ CLK_TOP_SPI_SEL
+};
+
+/* CLK_INFRA_PWM_BCK_SEL (infra_pwm_bck_sel) in infracfg */
+static const int infra_pwm_bck_parents[] = {
+ CLK_TOP_CB_RTC_32P7K,
+ CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_SYSAXI_SEL,
+ CLK_TOP_PWM_SEL
+};
+
+/* CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL (infra_pcie_gfmux_tl_ck_o_p0_sel) in infracfg */
+static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
+ CLK_TOP_CB_RTC_32P7K,
+ CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_PEXTP_TL_SEL
+};
+
+/* CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL (infra_pcie_gfmux_tl_ck_o_p1_sel) in infracfg */
+static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
+ CLK_TOP_CB_RTC_32P7K,
+ CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_PEXTP_TL_P1_SEL
+};
+
+#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
+ { \
+ .id = (_id), .mux_reg = (_reg) + 0x8, \
+ .mux_clr_reg = (_reg) + 0x4, .mux_set_reg = (_reg) + 0x0, \
+ .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \
+ .gate_shift = -1, .upd_shift = -1, \
+ .parent = (_parents), .num_parents = ARRAY_SIZE(_parents), \
+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \
+ }
+
+/* INFRA MUX */
+static const struct mtk_composite infracfg_mtk_mux[] = {
+ INFRA_MUX(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
+ infra_mux_uart0_parents, 0x0010, 0, 1),
+ INFRA_MUX(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
+ infra_mux_uart1_parents, 0x0010, 1, 1),
+ INFRA_MUX(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
+ infra_mux_uart2_parents, 0x0010, 2, 1),
+ INFRA_MUX(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
+ infra_mux_spi0_parents, 0x0010, 4, 1),
+ INFRA_MUX(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
+ infra_mux_spi1_parents, 0x0010, 5, 1),
+ INFRA_MUX(CLK_INFRA_MUX_SPI2_BCK_SEL, "infra_mux_spi2_bck_sel",
+ infra_mux_spi2_bck_parents, 0x0010, 6, 1),
+ INFRA_MUX(CLK_INFRA_PWM_BCK_SEL, "infra_pwm_bck_sel",
+ infra_pwm_bck_parents, 0x0010, 14, 2),
+ INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_ck_o_p0_sel",
+ infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0020, 0, 2),
+ INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_ck_o_p1_sel",
+ infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0020, 2, 2),
+};
+
+static const struct mtk_gate_regs infra_0_cg_regs = {
+ .set_ofs = 0x10,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x18,
+};
+
+static const struct mtk_gate_regs infra_1_cg_regs = {
+ .set_ofs = 0x40,
+ .clr_ofs = 0x44,
+ .sta_ofs = 0x48,
+};
+
+static const struct mtk_gate_regs infra_2_cg_regs = {
+ .set_ofs = 0x50,
+ .clr_ofs = 0x54,
+ .sta_ofs = 0x58,
+};
+
+static const struct mtk_gate_regs infra_3_cg_regs = {
+ .set_ofs = 0x60,
+ .clr_ofs = 0x64,
+ .sta_ofs = 0x68,
+};
+
+#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \
+ { \
+ .id = (_id), .parent = (_parent), .regs = &infra_0_cg_regs, \
+ .shift = (_shift), \
+ .flags = (_flags), \
+ }
+#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+
+#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \
+ { \
+ .id = (_id), .parent = (_parent), .regs = &infra_1_cg_regs, \
+ .shift = (_shift), \
+ .flags = (_flags), \
+ }
+#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+
+#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \
+ { \
+ .id = (_id), .parent = (_parent), .regs = &infra_2_cg_regs, \
+ .shift = (_shift), \
+ .flags = (_flags), \
+ }
+#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+
+#define GATE_INFRA3(_id, _name, _parent, _shift, _flags) \
+ { \
+ .id = (_id), .parent = (_parent), .regs = &infra_3_cg_regs, \
+ .shift = (_shift), \
+ .flags = (_flags), \
+ }
+#define GATE_INFRA3_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+#define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \
+ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
+
+/* INFRA GATE */
+static const struct mtk_gate infracfg_mtk_gates[] = {
+ GATE_INFRA1_TOP(CLK_INFRA_66M_GPT_BCK,
+ "infra_hf_66m_gpt_bck", CLK_TOP_SYSAXI_SEL, 0),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_PWM_HCK,
+ "infra_hf_66m_pwm_hck", CLK_TOP_SYSAXI_SEL, 1),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_BCK,
+ "infra_hf_66m_pwm_bck", CLK_INFRA_PWM_BCK_SEL, 2),
+ GATE_INFRA1_TOP(CLK_INFRA_133M_CQDMA_BCK,
+ "infra_hf_133m_cqdma_bck", CLK_TOP_SYSAXI_SEL, 12),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_AUD_SLV_BCK,
+ "infra_66m_aud_slv_bck", CLK_TOP_SYSAXI_SEL, 13),
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_26M, "infra_f_faud_26m",
+ CLK_TOP_INFRA_F26M_SEL, 14),
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_L, "infra_f_faud_l", CLK_TOP_AUD_L_SEL, 15),
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", CLK_TOP_A1SYS_SEL, 16),
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2",
+ CLK_TOP_A_TUNER_SEL, 18),
+ GATE_INFRA1_TOP(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
+ CLK_TOP_INFRA_F26M_SEL, 19),
+ GATE_INFRA1_TOP(CLK_INFRA_133M_DBG_ACKM,
+ "infra_hf_133m_dbg_ackm", CLK_TOP_SYSAXI_SEL, 20),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_AP_DMA_BCK,
+ "infra_66m_ap_dma_bck", CLK_TOP_SYSAXI_SEL, 21),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC200_SRC, "infra_f_fmsdc200_src",
+ CLK_TOP_EMMC_200M_SEL, 28),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_SEJ_BCK,
+ "infra_hf_66m_sej_bck", CLK_TOP_SYSAXI_SEL, 29),
+ GATE_INFRA1_TOP(CLK_INFRA_PRE_CK_SEJ_F13M,
+ "infra_pre_ck_sej_f13m", CLK_TOP_INFRA_F26M_SEL, 30),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_TRNG, "infra_hf_66m_trng",
+ CLK_TOP_SYSAXI_SEL, 31),
+ GATE_INFRA2_TOP(CLK_INFRA_26M_THERM_SYSTEM,
+ "infra_hf_26m_therm_system", CLK_TOP_INFRA_F26M_SEL, 0),
+ GATE_INFRA2_TOP(CLK_INFRA_I2C_BCK, "infra_i2c_bck", CLK_TOP_I2C_SEL, 1),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_UART0_PCK,
+ "infra_hf_66m_uart0_pck", CLK_TOP_SYSAXI_SEL, 3),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_UART1_PCK,
+ "infra_hf_66m_uart1_pck", CLK_TOP_SYSAXI_SEL, 4),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_UART2_PCK,
+ "infra_hf_66m_uart2_pck", CLK_TOP_SYSAXI_SEL, 5),
+ GATE_INFRA2_INFRA(CLK_INFRA_52M_UART0_CK,
+ "infra_f_52m_uart0", CLK_INFRA_MUX_UART0_SEL, 3),
+ GATE_INFRA2_INFRA(CLK_INFRA_52M_UART1_CK,
+ "infra_f_52m_uart1", CLK_INFRA_MUX_UART1_SEL, 4),
+ GATE_INFRA2_INFRA(CLK_INFRA_52M_UART2_CK,
+ "infra_f_52m_uart2", CLK_INFRA_MUX_UART2_SEL, 5),
+ GATE_INFRA2_TOP(CLK_INFRA_NFI, "infra_f_fnfi", CLK_TOP_NFI_SEL, 9),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_NFI_HCK,
+ "infra_hf_66m_nfi_hck", CLK_TOP_SYSAXI_SEL, 11),
+ GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
+ CLK_INFRA_MUX_SPI0_SEL, 12),
+ GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
+ CLK_INFRA_MUX_SPI1_SEL, 13),
+ GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI2_BCK,
+ "infra_hf_104m_spi2_bck", CLK_INFRA_MUX_SPI2_BCK_SEL, 14),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_SPI0_HCK,
+ "infra_hf_66m_spi0_hck", CLK_TOP_SYSAXI_SEL, 15),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_SPI1_HCK,
+ "infra_hf_66m_spi1_hck", CLK_TOP_SYSAXI_SEL, 16),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_SPI2_HCK,
+ "infra_hf_66m_spi2_hck", CLK_TOP_SYSAXI_SEL, 17),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_FLASHIF_AXI,
+ "infra_hf_66m_flashif_axi", CLK_TOP_SYSAXI_SEL, 18),
+ GATE_INFRA2_TOP(CLK_INFRA_RTC, "infra_f_frtc", CLK_TOP_CB_RTC_32K, 19),
+ GATE_INFRA2_TOP(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
+ CLK_TOP_INFRA_F26M_SEL, 20),
+ GATE_INFRA2_INFRA(CLK_INFRA_RC_ADC, "infra_f_frc_adc",
+ CLK_INFRA_26M_ADC_BCK, 21),
+ GATE_INFRA2_TOP(CLK_INFRA_MSDC400, "infra_f_fmsdc400",
+ CLK_TOP_EMMC_400M_SEL, 22),
+ GATE_INFRA2_TOP(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
+ CLK_TOP_EMMC_250M_SEL, 23),
+ GATE_INFRA2_TOP(CLK_INFRA_133M_MSDC_0_HCK,
+ "infra_hf_133m_msdc_0_hck", CLK_TOP_SYSAXI_SEL, 24),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_MSDC_0_HCK,
+ "infra_66m_msdc_0_hck", CLK_TOP_SYSAXI_SEL, 25),
+ GATE_INFRA2_TOP(CLK_INFRA_133M_CPUM_BCK,
+ "infra_hf_133m_cpum_bck", CLK_TOP_SYSAXI_SEL, 26),
+ GATE_INFRA2_TOP(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc",
+ CLK_TOP_NFI_SEL, 27),
+ GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_MCK_CK_P1,
+ "infra_hf_i2c_x16w_mck_ck_p1", CLK_TOP_SYSAXI_SEL, 29),
+ GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_PCK_CK_P1,
+ "infra_hf_i2c_x16w_pck_ck_p1", CLK_TOP_SYSAXI_SEL, 31),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK,
+ "infra_133m_usb_hck", CLK_TOP_SYSAXI_SEL, 0),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK_CK_P1,
+ "infra_133m_usb_hck_ck_p1", CLK_TOP_SYSAXI_SEL, 1),
+ GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
+ CLK_TOP_SYSAXI_SEL, 2),
+ GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK_CK_P1,
+ "infra_66m_usb_hck_ck_p1", CLK_TOP_SYSAXI_SEL, 3),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_SYS_CK_P1,
+ "infra_usb_sys_ck_p1", CLK_TOP_USB_SYS_P1_SEL, 5),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1",
+ CLK_TOP_CB_CKSQ_40M, 7),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1,
+ "infra_usb_frmcnt_ck_p1", CLK_TOP_CKSQ_40M_D2, 9),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1,
+ "infra_usb_pipe_ck_p1", CLK_XTAL, 11),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1,
+ "infra_usb_utmi_ck_p1", CLK_XTAL, 13),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1,
+ "infra_usb_xhci_ck_p1", CLK_TOP_USB_XHCI_P1_SEL, 15),
+ GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P0,
+ "infra_pcie_gfmux_tl_ck_p0", CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
+ GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P1,
+ "infra_pcie_gfmux_tl_ck_p1", CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
+ GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0,
+ "infra_pcie_pipe_ck_p0", CLK_XTAL, 24),
+ GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1,
+ "infra_pcie_pipe_ck_p1", CLK_XTAL, 25),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0,
+ "infra_133m_pcie_ck_p0", CLK_TOP_SYSAXI_SEL, 28),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1,
+ "infra_133m_pcie_ck_p1", CLK_TOP_SYSAXI_SEL, 29),
+ GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P0,
+ "infra_pcie_peri_ck_26m_ck_p0", CLK_TOP_INFRA_F26M_SEL, 7),
+ GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P1,
+ "infra_pcie_peri_ck_26m_ck_p1", CLK_TOP_INFRA_F26M_SEL, 8),
+};
+
+static const struct mtk_clk_tree mt7987_infracfg_clk_tree = {
+ .muxes_offs = CLK_INFRA_MUX_UART0_SEL,
+ .gates_offs = CLK_INFRA_66M_GPT_BCK,
+ .muxes = infracfg_mtk_mux,
+ .gates = infracfg_mtk_gates,
+ .flags = CLK_BYPASS_XTAL,
+ .xtal_rate = MT7987_XTAL_RATE,
+};
+
+static const struct udevice_id mt7987_infracfg_compat[] = {
+ { .compatible = "mediatek,mt7987-infracfg_ao" },
+ { .compatible = "mediatek,mt7987-infracfg" },
+ {}
+};
+
+static int mt7987_infracfg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_infrasys_init(dev, &mt7987_infracfg_clk_tree);
+}
+
+U_BOOT_DRIVER(mtk_clk_infracfg) = {
+ .name = "mt7987-clock-infracfg",
+ .id = UCLASS_CLK,
+ .of_match = mt7987_infracfg_compat,
+ .probe = mt7987_infracfg_probe,
+ .priv_auto = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_infrasys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+/* ethsys */
+static const struct mtk_gate_regs eth_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+#define GATE_ETH_TOP(_id, _name, _parent, _shift) \
+ { \
+ .id = (_id), .parent = (_parent), .regs = &eth_cg_regs, \
+ .shift = (_shift), \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate eth_cgs[] = {
+ GATE_ETH_TOP(CLK_ETHDMA_FE_EN, "ethdma_fe_en", CLK_TOP_NETSYS_2X_SEL, 6),
+ GATE_ETH_TOP(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", CLK_TOP_NETSYS_500M_SEL, 7),
+ GATE_ETH_TOP(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", CLK_TOP_NETSYS_500M_SEL, 8),
+ GATE_ETH_TOP(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", CLK_TOP_NETSYS_500M_SEL, 10),
+};
+
+static int mt7987_ethsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7987_topckgen_clk_tree,
+ eth_cgs);
+}
+
+static int mt7987_ethsys_bind(struct udevice *dev)
+{
+ int ret = 0;
+
+ if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
+ ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
+ if (ret)
+ debug("Warning: failed to bind reset controller\n");
+ }
+
+ return ret;
+}
+
+static const struct udevice_id mt7987_ethsys_compat[] = {
+ {
+ .compatible = "mediatek,mt7987-ethsys",
+ },
+ {}
+};
+
+U_BOOT_DRIVER(mtk_clk_ethsys) = {
+ .name = "mt7987-clock-ethsys",
+ .id = UCLASS_CLK,
+ .of_match = mt7987_ethsys_compat,
+ .probe = mt7987_ethsys_probe,
+ .bind = mt7987_ethsys_bind,
+ .priv_auto = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 8f4e8f4e8c9..73fd9c6bea6 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -485,6 +485,7 @@ static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
.id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \
.mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \
.mux_mask = BIT(_width) - 1, .parent = _parents, \
+ .gate_shift = -1, .upd_shift = -1, \
.num_parents = ARRAY_SIZE(_parents), \
.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \
}
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index d76fca5dba4..cb867acc48c 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -47,6 +47,14 @@ config CLK_QCOM_QCS404
on the Snapdragon QCS404 SoC. This driver supports the clocks
and resets exposed by the GCC hardware block.
+config CLK_QCOM_SA8775P
+ bool "Qualcomm SA8775 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon SA8775 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
config CLK_QCOM_SDM845
bool "Qualcomm SDM845 GCC"
select CLK_QCOM
@@ -103,6 +111,14 @@ config CLK_QCOM_SC7280
on the Snapdragon SC7280 SoC. This driver supports the clocks
and resets exposed by the GCC hardware block.
+config CLK_QCOM_X1E80100
+ bool "Qualcomm X1E80100 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon X1E80100 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
endmenu
endif
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index ab33f1c5faf..1bc0f15005b 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -9,9 +9,11 @@ obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
+obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o
obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o
obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o
obj-$(CONFIG_CLK_QCOM_SM8250) += clock-sm8250.o
obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o
obj-$(CONFIG_CLK_QCOM_SM8650) += clock-sm8650.o
+obj-$(CONFIG_CLK_QCOM_X1E80100) += clock-x1e80100.o
diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
index 25ca67e537d..7687bbe6a23 100644
--- a/drivers/clk/qcom/clock-qcom.c
+++ b/drivers/clk/qcom/clock-qcom.c
@@ -166,6 +166,25 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
clk_bcr_update(base + cmd_rcgr);
}
+#define PHY_MUX_MASK GENMASK(1, 0)
+#define PHY_MUX_PHY_SRC 0
+#define PHY_MUX_REF_SRC 2
+
+void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled)
+{
+ u32 cfg;
+
+ /* setup src select and divider */
+ cfg = readl(base + cmd_rcgr);
+ cfg &= ~(PHY_MUX_MASK);
+ if (enabled)
+ cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC);
+ else
+ cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC);
+
+ writel(cfg, base + cmd_rcgr);
+}
+
const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
{
if (!f)
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index 78d9b1d81ec..ff336dea39c 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -6,6 +6,7 @@
#define _CLOCK_QCOM_H
#include <asm/io.h>
+#include <linux/bitfield.h>
#define CFG_CLK_SRC_CXO (0 << 8)
#define CFG_CLK_SRC_GPLL0 (1 << 8)
@@ -102,6 +103,7 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr,
int div, int m, int n, int source, u8 mnd_width);
void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
int source);
+void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
{
diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c
new file mode 100644
index 00000000000..e31f24ed4f0
--- /dev/null
+++ b/drivers/clk/qcom/clock-sa8775p.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Clock drivers for Qualcomm sa8775p
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ */
+
+#include <linux/types.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+#include "clock-qcom.h"
+
+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
+#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
+
+static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id < priv->data->num_clks)
+ debug("%s: %s, requested rate=%ld\n", __func__,
+ priv->data->clks[clk->id].name, rate);
+
+ switch (clk->id) {
+ case GCC_USB30_PRIM_MOCK_UTMI_CLK:
+ WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate);
+ clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
+ return rate;
+ case GCC_USB30_PRIM_MASTER_CLK:
+ WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
+ clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
+ 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
+ clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
+ return rate;
+ default:
+ return 0;
+ }
+}
+
+static const struct gate_clk sa8775p_clks[] = {
+ GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, 1),
+ GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, 1),
+ GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, 1),
+ GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, 1),
+ GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1),
+ GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1),
+ GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1),
+};
+
+static int sa8775p_enable(struct clk *clk)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (priv->data->num_clks < clk->id) {
+ debug("%s: unknown clk id %lu\n", __func__, clk->id);
+ return 0;
+ }
+
+ debug("%s: clk %ld: %s\n", __func__, clk->id, sa8775p_clks[clk->id].name);
+
+ switch (clk->id) {
+ case GCC_AGGRE_USB3_PRIM_AXI_CLK:
+ qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK);
+ fallthrough;
+ case GCC_USB30_PRIM_MASTER_CLK:
+ qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
+ qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
+ break;
+ }
+
+ qcom_gate_clk_en(priv, clk->id);
+
+ return 0;
+}
+
+static const struct qcom_reset_map sa8775p_gcc_resets[] = {
+ [GCC_CAMERA_BCR] = { 0x32000 },
+ [GCC_DISPLAY1_BCR] = { 0xC7000 },
+ [GCC_DISPLAY_BCR] = { 0x33000 },
+ [GCC_EMAC0_BCR] = { 0xB6000 },
+ [GCC_EMAC1_BCR] = { 0xB4000 },
+ [GCC_GPU_BCR] = { 0x7D000 },
+ [GCC_MMSS_BCR] = { 0x17000 },
+ [GCC_PCIE_0_BCR] = { 0xa9000 },
+ [GCC_PCIE_0_LINK_DOWN_BCR] = { 0xBF000 },
+ [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xBF008 },
+ [GCC_PCIE_0_PHY_BCR] = { 0xAD144 },
+ [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xBF00C },
+ [GCC_PCIE_1_BCR] = { 0x77000 },
+ [GCC_PCIE_1_LINK_DOWN_BCR] = { 0xAE084 },
+ [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xAE090 },
+ [GCC_PCIE_1_PHY_BCR] = { 0xAE08C },
+ [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xAE094 },
+ [GCC_PDM_BCR] = { 0x3F000 },
+ [GCC_QUPV3_WRAPPER_0_BCR] = { 0x23000 },
+ [GCC_QUPV3_WRAPPER_1_BCR] = { 0x24000 },
+ [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2A000 },
+ [GCC_QUPV3_WRAPPER_3_BCR] = { 0xC4000 },
+ [GCC_SDCC1_BCR] = { 0x20000 },
+ [GCC_TSCSS_BCR] = { 0x21000 },
+ [GCC_UFS_CARD_BCR] = { 0x81000 },
+ [GCC_UFS_PHY_BCR] = { 0x83000 },
+};
+
+static const struct qcom_power_map sa8775p_gdscs[] = {
+ [UFS_PHY_GDSC] = { 0x83004 },
+ [USB30_PRIM_GDSC] = { 0x1B004 },
+};
+
+static struct msm_clk_data sa8775_gcc_data = {
+ .resets = sa8775p_gcc_resets,
+ .num_resets = ARRAY_SIZE(sa8775p_gcc_resets),
+ .clks = sa8775p_clks,
+ .num_clks = ARRAY_SIZE(sa8775p_clks),
+
+ .power_domains = sa8775p_gdscs,
+ .num_power_domains = ARRAY_SIZE(sa8775p_gdscs),
+
+ .enable = sa8775p_enable,
+ .set_rate = sa8775p_set_rate,
+};
+
+static const struct udevice_id gcc_sa8775p_of_match[] = {
+ {
+ .compatible = "qcom,sa8775p-gcc",
+ .data = (ulong)&sa8775_gcc_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(gcc_sa8775p) = {
+ .name = "gcc_sa8775p",
+ .id = UCLASS_NOP,
+ .of_match = gcc_sa8775p_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c
index c0249925cc7..62b5a409e8e 100644
--- a/drivers/clk/qcom/clock-sm8550.c
+++ b/drivers/clk/qcom/clock-sm8550.c
@@ -57,6 +57,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
{ }
};
+static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
+ F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
+ F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+ { }
+};
+
static ulong sm8550_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -84,6 +94,24 @@ static ulong sm8550_set_rate(struct clk *clk, ulong rate)
case GCC_USB3_PRIM_PHY_AUX_CLK_SRC:
clk_rcg_set_rate(priv->base, 0x39070, 0, 0);
return TCXO_DIV2_RATE;
+ case GCC_PCIE_0_AUX_CLK:
+ freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x6b074,
+ freq->pre_div, freq->m, freq->n, freq->src, 16);
+ return freq->freq;
+ case GCC_PCIE_1_AUX_CLK:
+ freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x8d07c,
+ freq->pre_div, freq->m, freq->n, freq->src, 16);
+ return freq->freq;
+ case GCC_PCIE_0_PHY_RCHNG_CLK:
+ freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
+ clk_rcg_set_rate(priv->base, 0x6b058, freq->pre_div, freq->src);
+ return freq->freq;
+ case GCC_PCIE_1_PHY_RCHNG_CLK:
+ freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
+ clk_rcg_set_rate(priv->base, 0x8d060, freq->pre_div, freq->src);
+ return freq->freq;
default:
return 0;
}
@@ -182,6 +210,14 @@ static int sm8550_enable(struct clk *clk)
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
break;
+ case GCC_PCIE_0_PIPE_CLK:
+ // GCC_PCIE_0_PIPE_CLK_SRC
+ clk_phy_mux_enable(priv->base, 0x6b070, true);
+ break;
+ case GCC_PCIE_1_PIPE_CLK:
+ // GCC_PCIE_1_PIPE_CLK_SRC
+ clk_phy_mux_enable(priv->base, 0x8d078, true);
+ break;
}
qcom_gate_clk_en(priv, clk->id);
diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c
index 0ce83e9b243..9baaecb571f 100644
--- a/drivers/clk/qcom/clock-sm8650.c
+++ b/drivers/clk/qcom/clock-sm8650.c
@@ -54,6 +54,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
{ }
};
+static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
+ F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
+ F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+ { }
+};
+
static ulong sm8650_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -81,6 +91,24 @@ static ulong sm8650_set_rate(struct clk *clk, ulong rate)
case GCC_USB3_PRIM_PHY_AUX_CLK_SRC:
clk_rcg_set_rate(priv->base, 0x39070, 0, 0);
return TCXO_DIV2_RATE;
+ case GCC_PCIE_0_AUX_CLK:
+ freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x6b074,
+ freq->pre_div, freq->m, freq->n, freq->src, 16);
+ return freq->freq;
+ case GCC_PCIE_1_AUX_CLK:
+ freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x8d07c,
+ freq->pre_div, freq->m, freq->n, freq->src, 16);
+ return freq->freq;
+ case GCC_PCIE_0_PHY_RCHNG_CLK:
+ freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
+ clk_rcg_set_rate(priv->base, 0x6b058, freq->pre_div, freq->src);
+ return freq->freq;
+ case GCC_PCIE_1_PHY_RCHNG_CLK:
+ freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
+ clk_rcg_set_rate(priv->base, 0x8d060, freq->pre_div, freq->src);
+ return freq->freq;
default:
return 0;
}
@@ -179,6 +207,14 @@ static int sm8650_enable(struct clk *clk)
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
break;
+ case GCC_PCIE_0_PIPE_CLK:
+ // GCC_PCIE_0_PIPE_CLK_SRC
+ clk_phy_mux_enable(priv->base, 0x6b070, true);
+ break;
+ case GCC_PCIE_1_PIPE_CLK:
+ // GCC_PCIE_1_PIPE_CLK_SRC
+ clk_phy_mux_enable(priv->base, 0x8d078, true);
+ break;
}
qcom_gate_clk_en(priv, clk->id);
diff --git a/drivers/clk/qcom/clock-x1e80100.c b/drivers/clk/qcom/clock-x1e80100.c
new file mode 100644
index 00000000000..bd9c6ed1c8a
--- /dev/null
+++ b/drivers/clk/qcom/clock-x1e80100.c
@@ -0,0 +1,402 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm x1e80100
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
+#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
+
+#include "clock-qcom.h"
+
+/* On-board TCXO, TOFIX get from DT */
+#define TCXO_RATE 38400000
+
+/* bi_tcxo_div2 divided after RPMh output */
+#define TCXO_DIV2_RATE (TCXO_RATE / 2)
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = {
+ F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+ F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+ F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+ F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+ F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+ F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
+ F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+ F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+ F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+ F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+ F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+ F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
+ F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
+ F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+ /* TOFIX F(202000000, CFG_CLK_SRC_GPLL9, 4, 0, 0), */
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+ F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
+ F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
+ F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0),
+ F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
+ F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
+ F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+ { }
+};
+
+static ulong x1e80100_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct freq_tbl *freq;
+
+ switch (clk->id) {
+ case GCC_QUPV3_WRAP2_S5_CLK: /* UART21 */
+ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s4_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x1e500,
+ freq->pre_div, freq->m, freq->n, freq->src, 16);
+ return freq->freq;
+ case GCC_SDCC2_APPS_CLK:
+ freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x14018,
+ freq->pre_div, freq->m, freq->n, freq->src, 8);
+ return freq->freq;
+ case GCC_USB30_PRIM_MASTER_CLK:
+ freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x3902c,
+ freq->pre_div, freq->m, freq->n, freq->src, 8);
+ return freq->freq;
+ case GCC_USB30_PRIM_MOCK_UTMI_CLK:
+ clk_rcg_set_rate(priv->base, 0x39044, 0, 0);
+ return TCXO_DIV2_RATE;
+ case GCC_PCIE_4_AUX_CLK:
+ freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x6b080,
+ freq->pre_div, freq->m, freq->n, freq->src, 16);
+ return freq->freq;
+ case GCC_PCIE_4_PHY_RCHNG_CLK:
+ freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
+ clk_rcg_set_rate(priv->base, 0x6b064, freq->pre_div, freq->src);
+ return freq->freq;
+ case GCC_PCIE_6A_AUX_CLK:
+ freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, 0x3108c,
+ freq->pre_div, freq->m, freq->n, freq->src, 16);
+ return freq->freq;
+ case GCC_PCIE_6A_PHY_RCHNG_CLK:
+ freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
+ clk_rcg_set_rate(priv->base, 0x31070, freq->pre_div, freq->src);
+ return freq->freq;
+ default:
+ return 0;
+ }
+}
+
+static const struct gate_clk x1e80100_clks[] = {
+ GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770e4, BIT(0)),
+ GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x3908c, BIT(0)),
+ GATE_CLK(GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK, 0x52000, BIT(20)),
+ GATE_CLK(GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK, 0x52028, BIT(22)),
+ GATE_CLK(GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK, 0x52028, BIT(12)),
+ GATE_CLK(GCC_CNOC_PCIE_NORTH_SF_AXI_CLK, 0x52008, BIT(6)),
+ GATE_CLK(GCC_PCIE_4_AUX_CLK, 0x52008, BIT(3)),
+ GATE_CLK(GCC_PCIE_4_CFG_AHB_CLK, 0x52008, BIT(2)),
+ GATE_CLK(GCC_PCIE_4_MSTR_AXI_CLK, 0x52008, BIT(1)),
+ GATE_CLK(GCC_PCIE_4_PHY_RCHNG_CLK, 0x52000, BIT(22)),
+ GATE_CLK(GCC_PCIE_4_PIPE_CLK, 0x52008, BIT(4)),
+ GATE_CLK(GCC_PCIE_4_SLV_AXI_CLK, 0x52008, BIT(0)),
+ GATE_CLK(GCC_PCIE_4_SLV_Q2A_AXI_CLK, 0x52008, BIT(5)),
+ GATE_CLK(GCC_PCIE_6A_AUX_CLK, 0x52018, BIT(24)),
+ GATE_CLK(GCC_PCIE_6A_CFG_AHB_CLK, 0x52018, BIT(23)),
+ GATE_CLK(GCC_PCIE_6A_MSTR_AXI_CLK, 0x52018, BIT(22)),
+ GATE_CLK(GCC_PCIE_6A_PHY_RCHNG_CLK, 0x52018, BIT(27)),
+ GATE_CLK(GCC_PCIE_6A_PIPE_CLK, 0x52018, BIT(26)),
+ GATE_CLK(GCC_PCIE_6A_SLV_AXI_CLK, 0x52018, BIT(21)),
+ GATE_CLK(GCC_PCIE_6A_SLV_Q2A_AXI_CLK, 0x52018, BIT(20)),
+ GATE_CLK(GCC_QUPV3_WRAP2_CORE_2X_CLK, 0x52010, BIT(3)),
+ GATE_CLK(GCC_QUPV3_WRAP2_CORE_CLK, 0x52010, BIT(0)),
+ GATE_CLK(GCC_QUPV3_WRAP2_S0_CLK, 0x52010, BIT(4)),
+ GATE_CLK(GCC_QUPV3_WRAP2_S1_CLK, 0x52010, BIT(5)),
+ GATE_CLK(GCC_QUPV3_WRAP2_S2_CLK, 0x52010, BIT(6)),
+ GATE_CLK(GCC_QUPV3_WRAP2_S3_CLK, 0x52010, BIT(7)),
+ GATE_CLK(GCC_QUPV3_WRAP2_S4_CLK, 0x52010, BIT(8)),
+ GATE_CLK(GCC_QUPV3_WRAP2_S5_CLK, 0x52010, BIT(9)),
+ GATE_CLK(GCC_QUPV3_WRAP2_S6_CLK, 0x52010, BIT(10)),
+ GATE_CLK(GCC_QUPV3_WRAP2_S7_CLK, 0x52010, BIT(17)),
+ GATE_CLK(GCC_QUPV3_WRAP_2_M_AHB_CLK, 0x52010, BIT(2)),
+ GATE_CLK(GCC_QUPV3_WRAP_2_S_AHB_CLK, 0x52010, BIT(1)),
+ GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x39018, BIT(0)),
+ GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x39028, BIT(0)),
+ GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x39024, BIT(0)),
+ GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x39060, BIT(0)),
+ GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x39064, BIT(0)),
+ GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x39068, BIT(0)),
+};
+
+static int x1e80100_enable(struct clk *clk)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case GCC_AGGRE_USB3_PRIM_AXI_CLK:
+ qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK);
+ fallthrough;
+ case GCC_USB30_PRIM_MASTER_CLK:
+ qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
+ qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
+ break;
+ case GCC_PCIE_4_PIPE_CLK:
+ // GCC_PCIE_4_PIPE_CLK_SRC
+ clk_phy_mux_enable(priv->base, 0x6b07c, true);
+ break;
+ case GCC_PCIE_6A_PIPE_CLK:
+ // GCC_PCIE_6A_PIPE_CLK_SRC
+ clk_phy_mux_enable(priv->base, 0x31088, true);
+ break;
+ }
+
+ qcom_gate_clk_en(priv, clk->id);
+
+ return 0;
+}
+
+static const struct qcom_reset_map x1e80100_gcc_resets[] = {
+ [GCC_AV1E_BCR] = { 0x4a000 },
+ [GCC_CAMERA_BCR] = { 0x26000 },
+ [GCC_DISPLAY_BCR] = { 0x27000 },
+ [GCC_GPU_BCR] = { 0x71000 },
+ [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
+ [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
+ [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
+ [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
+ [GCC_PCIE_0_TUNNEL_BCR] = { 0xa0000 },
+ [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
+ [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
+ [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
+ [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
+ [GCC_PCIE_1_TUNNEL_BCR] = { 0x2c000 },
+ [GCC_PCIE_2_LINK_DOWN_BCR] = { 0xa5014 },
+ [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0xa5020 },
+ [GCC_PCIE_2_PHY_BCR] = { 0xa501c },
+ [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0xa5028 },
+ [GCC_PCIE_2_TUNNEL_BCR] = { 0x13000 },
+ [GCC_PCIE_3_BCR] = { 0x58000 },
+ [GCC_PCIE_3_LINK_DOWN_BCR] = { 0xab014 },
+ [GCC_PCIE_3_NOCSR_COM_PHY_BCR] = { 0xab020 },
+ [GCC_PCIE_3_PHY_BCR] = { 0xab01c },
+ [GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR] = { 0xab024 },
+ [GCC_PCIE_4_BCR] = { 0x6b000 },
+ [GCC_PCIE_4_LINK_DOWN_BCR] = { 0xb3014 },
+ [GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0xb3020 },
+ [GCC_PCIE_4_PHY_BCR] = { 0xb301c },
+ [GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0xb3028 },
+ [GCC_PCIE_5_BCR] = { 0x2f000 },
+ [GCC_PCIE_5_LINK_DOWN_BCR] = { 0xaa014 },
+ [GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0xaa020 },
+ [GCC_PCIE_5_PHY_BCR] = { 0xaa01c },
+ [GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0xaa028 },
+ [GCC_PCIE_6A_BCR] = { 0x31000 },
+ [GCC_PCIE_6A_LINK_DOWN_BCR] = { 0xac014 },
+ [GCC_PCIE_6A_NOCSR_COM_PHY_BCR] = { 0xac020 },
+ [GCC_PCIE_6A_PHY_BCR] = { 0xac01c },
+ [GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR] = { 0xac024 },
+ [GCC_PCIE_6B_BCR] = { 0x8d000 },
+ [GCC_PCIE_6B_LINK_DOWN_BCR] = { 0xb5014 },
+ [GCC_PCIE_6B_NOCSR_COM_PHY_BCR] = { 0xb5020 },
+ [GCC_PCIE_6B_PHY_BCR] = { 0xb501c },
+ [GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR] = { 0xb5024 },
+ [GCC_PCIE_PHY_BCR] = { 0x6f000 },
+ [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
+ [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
+ [GCC_PCIE_RSCC_BCR] = { 0xa4000 },
+ [GCC_PDM_BCR] = { 0x33000 },
+ [GCC_QUPV3_WRAPPER_0_BCR] = { 0x42000 },
+ [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
+ [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
+ [GCC_QUSB2PHY_HS0_MP_BCR] = { 0x1200c },
+ [GCC_QUSB2PHY_HS1_MP_BCR] = { 0x12010 },
+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
+ [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
+ [GCC_QUSB2PHY_TERT_BCR] = { 0x12008 },
+ [GCC_QUSB2PHY_USB20_HS_BCR] = { 0x12014 },
+ [GCC_SDCC2_BCR] = { 0x14000 },
+ [GCC_SDCC4_BCR] = { 0x16000 },
+ [GCC_UFS_PHY_BCR] = { 0x77000 },
+ [GCC_USB20_PRIM_BCR] = { 0x29000 },
+ [GCC_USB30_MP_BCR] = { 0x17000 },
+ [GCC_USB30_PRIM_BCR] = { 0x39000 },
+ [GCC_USB30_SEC_BCR] = { 0xa1000 },
+ [GCC_USB30_TERT_BCR] = { 0xa2000 },
+ [GCC_USB3_MP_SS0_PHY_BCR] = { 0x19008 },
+ [GCC_USB3_MP_SS1_PHY_BCR] = { 0x54008 },
+ [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
+ [GCC_USB3_PHY_SEC_BCR] = { 0x2a000 },
+ [GCC_USB3_PHY_TERT_BCR] = { 0xa3000 },
+ [GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 },
+ [GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 },
+ [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
+ [GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 },
+ [GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 },
+ [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 },
+ [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 },
+ [GCC_USB4_0_BCR] = { 0x9f000 },
+ [GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 },
+ [GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
+ [GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
+ [GCC_USB4_1_BCR] = { 0x2b000 },
+ [GCC_USB4_2_BCR] = { 0x11000 },
+ [GCC_USB_0_PHY_BCR] = { 0x50020 },
+ [GCC_USB_1_PHY_BCR] = { 0x2a020 },
+ [GCC_USB_2_PHY_BCR] = { 0xa3020 },
+ [GCC_VIDEO_BCR] = { 0x32000 },
+};
+
+static const struct qcom_power_map x1e80100_gdscs[] = {
+ [GCC_PCIE_0_TUNNEL_GDSC] = { 0xa0004 },
+ [GCC_PCIE_1_TUNNEL_GDSC] = { 0x2c004 },
+ [GCC_PCIE_2_TUNNEL_GDSC] = { 0x13004 },
+ [GCC_PCIE_3_GDSC] = { 0x58004 },
+ [GCC_PCIE_3_PHY_GDSC] = { 0x3e000 },
+ [GCC_PCIE_4_GDSC] = { 0x6b004 },
+ [GCC_PCIE_4_PHY_GDSC] = { 0x6c000 },
+ [GCC_PCIE_5_GDSC] = { 0x2f004 },
+ [GCC_PCIE_5_PHY_GDSC] = { 0x30000 },
+ [GCC_PCIE_6_PHY_GDSC] = { 0x8e000 },
+ [GCC_PCIE_6A_GDSC] = { 0x31004 },
+ [GCC_PCIE_6B_GDSC] = { 0x8d004 },
+ [GCC_UFS_MEM_PHY_GDSC] = { 0x9e000 },
+ [GCC_UFS_PHY_GDSC] = { 0x77004 },
+ [GCC_USB20_PRIM_GDSC] = { 0x29004 },
+ [GCC_USB30_MP_GDSC] = { 0x17004 },
+ [GCC_USB30_PRIM_GDSC] = { 0x39004 },
+ [GCC_USB30_SEC_GDSC] = { 0xa1004 },
+ [GCC_USB30_TERT_GDSC] = { 0xa2004 },
+ [GCC_USB3_MP_SS0_PHY_GDSC] = { 0x1900c },
+ [GCC_USB3_MP_SS1_PHY_GDSC] = { 0x5400c },
+ [GCC_USB4_0_GDSC] = { 0x9f004 },
+ [GCC_USB4_1_GDSC] = { 0x2b004 },
+ [GCC_USB4_2_GDSC] = { 0x11004 },
+ [GCC_USB_0_PHY_GDSC] = { 0x50024 },
+ [GCC_USB_1_PHY_GDSC] = { 0x2a024 },
+ [GCC_USB_2_PHY_GDSC] = { 0xa3024 },
+};
+
+static struct msm_clk_data x1e80100_gcc_data = {
+ .resets = x1e80100_gcc_resets,
+ .num_resets = ARRAY_SIZE(x1e80100_gcc_resets),
+ .clks = x1e80100_clks,
+ .num_clks = ARRAY_SIZE(x1e80100_clks),
+ .power_domains = x1e80100_gdscs,
+ .num_power_domains = ARRAY_SIZE(x1e80100_gdscs),
+
+ .enable = x1e80100_enable,
+ .set_rate = x1e80100_set_rate,
+};
+
+static const struct udevice_id gcc_x1e80100_of_match[] = {
+ {
+ .compatible = "qcom,x1e80100-gcc",
+ .data = (ulong)&x1e80100_gcc_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(gcc_x1e80100) = {
+ .name = "gcc_x1e80100",
+ .id = UCLASS_NOP,
+ .of_match = gcc_x1e80100_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
+
+/* TCSRCC */
+
+static const struct gate_clk x1e80100_tcsr_clks[] = {
+ GATE_CLK(TCSR_PCIE_2L_4_CLKREF_EN, 0x15100, BIT(0)),
+ GATE_CLK(TCSR_PCIE_2L_5_CLKREF_EN, 0x15104, BIT(0)),
+ GATE_CLK(TCSR_PCIE_8L_CLKREF_EN, 0x15108, BIT(0)),
+ GATE_CLK(TCSR_USB3_MP0_CLKREF_EN, 0x1510c, BIT(0)),
+ GATE_CLK(TCSR_USB3_MP1_CLKREF_EN, 0x15110, BIT(0)),
+ GATE_CLK(TCSR_USB2_1_CLKREF_EN, 0x15114, BIT(0)),
+ GATE_CLK(TCSR_UFS_PHY_CLKREF_EN, 0x15118, BIT(0)),
+ GATE_CLK(TCSR_USB4_1_CLKREF_EN, 0x15120, BIT(0)),
+ GATE_CLK(TCSR_USB4_2_CLKREF_EN, 0x15124, BIT(0)),
+ GATE_CLK(TCSR_USB2_2_CLKREF_EN, 0x15128, BIT(0)),
+ GATE_CLK(TCSR_PCIE_4L_CLKREF_EN, 0x1512c, BIT(0)),
+ GATE_CLK(TCSR_EDP_CLKREF_EN, 0x15130, BIT(0)),
+};
+
+static struct msm_clk_data x1e80100_tcsrcc_data = {
+ .clks = x1e80100_tcsr_clks,
+ .num_clks = ARRAY_SIZE(x1e80100_tcsr_clks),
+};
+
+static int tcsrcc_x1e80100_clk_enable(struct clk *clk)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ qcom_gate_clk_en(priv, clk->id);
+
+ return 0;
+}
+
+static ulong tcsrcc_x1e80100_clk_get_rate(struct clk *clk)
+{
+ return TCXO_RATE;
+}
+
+static int tcsrcc_x1e80100_clk_probe(struct udevice *dev)
+{
+ struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev);
+ struct msm_clk_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->data = data;
+
+ return 0;
+}
+
+static struct clk_ops tcsrcc_x1e80100_clk_ops = {
+ .enable = tcsrcc_x1e80100_clk_enable,
+ .get_rate = tcsrcc_x1e80100_clk_get_rate,
+};
+
+static const struct udevice_id tcsrcc_x1e80100_of_match[] = {
+ {
+ .compatible = "qcom,x1e80100-tcsr",
+ .data = (ulong)&x1e80100_tcsrcc_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(tcsrcc_x1e80100) = {
+ .name = "tcsrcc_x1e80100",
+ .id = UCLASS_CLK,
+ .of_match = tcsrcc_x1e80100_of_match,
+ .ops = &tcsrcc_x1e80100_clk_ops,
+ .priv_auto = sizeof(struct msm_clk_priv),
+ .probe = tcsrcc_x1e80100_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 43c44fadbe7..a4ff1c41abb 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -903,11 +903,11 @@ static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *pa
int ret;
/*
- * If the requested parent is in the same clock-controller and
- * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal
- * clock.
+ * If the requested parent is in the same clock-controller the
+ * likely parent is the unexported SCLK_MAC_PLL ("mac_pll_src"),
+ * switch to the internal clock.
*/
- if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) {
+ if (parent->dev == clk->dev) {
debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__);
rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0);
return 0;
diff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c
index a554eda504d..6acf2ff0a8f 100644
--- a/drivers/clk/stm32/clk-stm32h7.c
+++ b/drivers/clk/stm32/clk-stm32h7.c
@@ -18,6 +18,9 @@
#include <dt-bindings/clock/stm32h7-clks.h>
+/* must be equal to last peripheral clock index */
+#define LAST_PERIF_BANK SYSCFG_CK
+
/* RCC CR specific definitions */
#define RCC_CR_HSION BIT(0)
#define RCC_CR_HSIRDY BIT(2)
generated by cgit v1.2.3 (git 2.0.4) at 2025-09-21 02:54:36 +0000