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-rw-r--r--drivers/clk/mpc83xx_clk.h2
-rw-r--r--drivers/clk/renesas/Kconfig12
-rw-r--r--drivers/clk/renesas/clk-rcar-gen2.c2
-rw-r--r--drivers/clk/renesas/clk-rcar-gen3.c2
-rw-r--r--drivers/clk/renesas/r8a779h0-cpg-mssr.c10
-rw-r--r--drivers/clk/renesas/rcar-cpg-lib.c2
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.h2
-rw-r--r--drivers/clk/tegra/tegra-car-clk.c50
9 files changed, 57 insertions, 27 deletions
diff --git a/drivers/clk/mpc83xx_clk.h b/drivers/clk/mpc83xx_clk.h
index c06a51ecd43..6b74fc5f16b 100644
--- a/drivers/clk/mpc83xx_clk.h
+++ b/drivers/clk/mpc83xx_clk.h
@@ -321,7 +321,7 @@ static inline u32 get_pci_sync_in(immap_t *im)
}
/**
- * get_csb_clk() - Read the CSB (Coheren System Bus) clock speed
+ * get_csb_clk() - Read the CSB (Coherent System Bus) clock speed
* @im: Pointer to the MPC83xx main register map in question
*
* Return: The CSB clock speed value as a 32-bit number.
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index a093027eb0e..12966d02a22 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -5,20 +5,20 @@ config CLK_RENESAS
Enable support for clock present on Renesas SoCs.
config CLK_RCAR
- bool "Renesas RCar clock driver support"
+ bool "Renesas R-Car clock driver support"
help
- Enable common code for clocks on Renesas RCar SoCs.
+ Enable common code for clocks on Renesas R-Car SoCs.
config CLK_RCAR_CPG_LIB
bool "CPG/MSSR library functions"
config CLK_RCAR_GEN2
- bool "Renesas RCar Gen2 clock driver"
+ bool "Renesas R-Car Gen2 clock driver"
def_bool y if RCAR_32
depends on CLK_RENESAS
select CLK_RCAR
help
- Enable this to support the clocks on Renesas RCar Gen2 SoC.
+ Enable this to support the clocks on Renesas R-Car Gen2 SoC.
config CLK_R8A7790
bool "Renesas R8A7790 clock driver"
@@ -51,14 +51,14 @@ config CLK_R8A7794
Enable this to support the clocks on Renesas R8A7794 SoC.
config CLK_RCAR_GEN3
- bool "Renesas RCar Gen3 and Gen4 clock driver"
+ bool "Renesas R-Car Gen3 and Gen4 clock driver"
def_bool y if RCAR_64
depends on CLK_RENESAS
select CLK_RCAR
select CLK_RCAR_CPG_LIB
select DM_RESET
help
- Enable this to support the clocks on Renesas RCar Gen3 and Gen4 SoCs.
+ Enable this to support the clocks on Renesas R-Car Gen3 and Gen4 SoCs.
config CLK_R8A774A1
bool "Renesas R8A774A1 clock driver"
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
index 89f2d966746..9b6fce4675c 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Renesas RCar Gen2 CPG MSSR driver
+ * Renesas R-Car Gen2 CPG MSSR driver
*
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
*
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index aa38c0f7dd0..375cc4a4930 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Renesas RCar Gen3 CPG MSSR driver
+ * Renesas R-Car Gen3 CPG MSSR driver
*
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
*
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index 2e98e262fb0..70fa8ff2871 100644
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -39,7 +39,6 @@ enum clk_ids {
CLK_PLL6,
CLK_PLL7,
CLK_PLL1_DIV2,
- CLK_PLL2_DIV2,
CLK_PLL3_DIV2,
CLK_PLL4_DIV2,
CLK_PLL4_DIV5,
@@ -82,7 +81,6 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = {
DEF_BASE(".pll7", CLK_PLL7, CLK_TYPE_GEN4_PLL7, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
- DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1),
DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5, CLK_PLL4, 5, 1),
@@ -106,10 +104,10 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = {
DEF_RATE(".oco", CLK_OCO, 32768),
/* Core Clock Outputs */
- DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 0),
- DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 8),
- DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 32),
- DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 40),
+ DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 0),
+ DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 8),
+ DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 32),
+ DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 40),
DEF_FIXED("s0d2", R8A779H0_CLK_S0D2, CLK_S0, 2, 1),
DEF_FIXED("s0d3", R8A779H0_CLK_S0D3, CLK_S0, 3, 1),
DEF_FIXED("s0d4", R8A779H0_CLK_S0D4, CLK_S0, 4, 1),
diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c
index 8862fbc7579..ea33bfd3239 100644
--- a/drivers/clk/renesas/rcar-cpg-lib.c
+++ b/drivers/clk/renesas/rcar-cpg-lib.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Renesas RCar Gen3 CPG MSSR driver
+ * Renesas R-Car Gen3 CPG MSSR driver
*
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
*
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 35bad7f5f73..39ff4541c1e 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Renesas RCar Gen3 CPG MSSR driver
+ * Renesas R-Car Gen3 CPG MSSR driver
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 71e409f3eb0..d5db14baf06 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Renesas RCar Gen3 CPG MSSR driver
+ * Renesas R-Car Gen3 CPG MSSR driver
*
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
*
diff --git a/drivers/clk/tegra/tegra-car-clk.c b/drivers/clk/tegra/tegra-car-clk.c
index 1d61f8dc378..880dd4f6ece 100644
--- a/drivers/clk/tegra/tegra-car-clk.c
+++ b/drivers/clk/tegra/tegra-car-clk.c
@@ -10,6 +10,9 @@
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
+#define TEGRA_CAR_CLK_PLL BIT(0)
+#define TEGRA_CAR_CLK_PERIPH BIT(1)
+
static int tegra_car_clk_request(struct clk *clk)
{
debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
@@ -20,24 +23,41 @@ static int tegra_car_clk_request(struct clk *clk)
* varies per SoC) are the peripheral clocks, which use a numbering
* scheme that matches HW registers 1:1. There are other clock IDs
* beyond this that are assigned arbitrarily by the Tegra CAR DT
- * binding. Due to the implementation of this driver, it currently
- * only supports the peripheral IDs.
+ * binding.
*/
- if (clk->id >= PERIPH_ID_COUNT)
- return -EINVAL;
+ if (clk->id < PERIPH_ID_COUNT) {
+ clk->data |= TEGRA_CAR_CLK_PERIPH;
+ return 0;
+ }
- return 0;
+ /* If check for periph failed, then check for PLL clock id */
+ int id = clk_id_to_pll_id(clk->id);
+
+ if (clock_id_is_pll(id)) {
+ clk->id = id;
+ clk->data |= TEGRA_CAR_CLK_PLL;
+ return 0;
+ }
+
+ return -EINVAL;
}
static ulong tegra_car_clk_get_rate(struct clk *clk)
{
- enum clock_id parent;
-
debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
clk->id);
- parent = clock_get_periph_parent(clk->id);
- return clock_get_periph_rate(clk->id, parent);
+ if (clk->data & TEGRA_CAR_CLK_PLL)
+ return clock_get_rate(clk->id);
+
+ if (clk->data & TEGRA_CAR_CLK_PERIPH) {
+ enum clock_id parent;
+
+ parent = clock_get_periph_parent(clk->id);
+ return clock_get_periph_rate(clk->id, parent);
+ }
+
+ return -1U;
}
static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
@@ -47,6 +67,9 @@ static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
clk->dev, clk->id);
+ if (clk->data & TEGRA_CAR_CLK_PLL)
+ return 0;
+
parent = clock_get_periph_parent(clk->id);
return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
}
@@ -56,6 +79,9 @@ static int tegra_car_clk_enable(struct clk *clk)
debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
clk->id);
+ if (clk->data & TEGRA_CAR_CLK_PLL)
+ return 0;
+
clock_enable(clk->id);
return 0;
@@ -66,6 +92,9 @@ static int tegra_car_clk_disable(struct clk *clk)
debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
clk->id);
+ if (clk->data & TEGRA_CAR_CLK_PLL)
+ return 0;
+
clock_disable(clk->id);
return 0;
@@ -83,6 +112,9 @@ static int tegra_car_clk_probe(struct udevice *dev)
{
debug("%s(dev=%p)\n", __func__, dev);
+ clock_init();
+ clock_verify();
+
return 0;
}