diff options
Diffstat (limited to 'drivers/clk')
32 files changed, 244 insertions, 119 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f9b90a38b00..7f84f22d4b1 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -4,13 +4,13 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # -obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o -obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o -obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o -obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o -obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o -obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o -obj-$(CONFIG_$(SPL_TPL_)CLK_GPIO) += clk-gpio.o +obj-$(CONFIG_$(PHASE_)CLK) += clk-uclass.o +obj-$(CONFIG_$(PHASE_)CLK) += clk_fixed_rate.o +obj-$(CONFIG_$(PHASE_)CLK) += clk_fixed_factor.o +obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o +obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk-fixed-factor.o +obj-$(CONFIG_$(PHASE_)CLK_COMPOSITE_CCF) += clk-composite.o +obj-$(CONFIG_$(PHASE_)CLK_GPIO) += clk-gpio.o obj-y += adi/ obj-y += analogbits/ @@ -18,7 +18,7 @@ obj-y += imx/ obj-$(CONFIG_CLK_JH7110) += starfive/ obj-y += tegra/ obj-y += ti/ -obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ +obj-$(CONFIG_$(PHASE_)CLK_INTEL) += intel/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_ARCH_MESON) += meson/ @@ -42,7 +42,7 @@ obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_QCOM) += qcom/ obj-$(CONFIG_CLK_RENESAS) += renesas/ -obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o +obj-$(CONFIG_$(PHASE_)CLK_SCMI) += clk_scmi.o obj-$(CONFIG_CLK_SIFIVE) += sifive/ obj-$(CONFIG_CLK_SOPHGO) += sophgo/ obj-$(CONFIG_CLK_SUNXI) += sunxi/ diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index bdc7be0fb5d..e1ddd02f356 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -242,7 +242,7 @@ static void clk_basic_init(struct udevice *dev, if (!cfg) return; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* Always force clock manager into boot mode before any configuration */ clk_write_ctrl(plat, CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE); diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c index 72b923465df..716c71598bc 100644 --- a/drivers/clk/altera/clk-agilex5.c +++ b/drivers/clk/altera/clk-agilex5.c @@ -263,7 +263,7 @@ static void clk_basic_init(struct udevice *dev, clk_write_ctrl(plat, CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE); } else { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* Always force clock manager into boot mode before any configuration */ clk_write_ctrl(plat, CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE); diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c index 3e256101a94..09db250ab6d 100644 --- a/drivers/clk/altera/clk-n5x.c +++ b/drivers/clk/altera/clk-n5x.c @@ -52,7 +52,7 @@ static void clk_basic_init(struct udevice *dev, if (!cfg) return; -#if IS_ENABLED(CONFIG_SPL_BUILD) +#if IS_ENABLED(CONFIG_XPL_BUILD) /* Always force clock manager into boot mode before any configuration */ clk_write_ctrl(plat, CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE); diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 16169dac234..a9937c22dcb 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -378,7 +378,7 @@ int clk_set_defaults(struct udevice *dev, enum clk_defaults_stage stage) * However, still set them for SPL. And still set them if explicitly * asked. */ - if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC))) + if (!(IS_ENABLED(CONFIG_XPL_BUILD) || (gd->flags & GD_FLG_RELOC))) if (stage != CLK_DEFAULTS_POST_FORCE) return 0; diff --git a/drivers/clk/clk_vexpress_osc.c b/drivers/clk/clk_vexpress_osc.c index 2e0e7bbe68f..85ac92c908a 100644 --- a/drivers/clk/clk_vexpress_osc.c +++ b/drivers/clk/clk_vexpress_osc.c @@ -37,7 +37,7 @@ static ulong vexpress_osc_clk_get_rate(struct clk *clk) return data; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong vexpress_osc_clk_set_rate(struct clk *clk, ulong rate) { int err; @@ -64,7 +64,7 @@ static ulong vexpress_osc_clk_set_rate(struct clk *clk, ulong rate) static struct clk_ops vexpress_osc_clk_ops = { .get_rate = vexpress_osc_clk_get_rate, -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD .set_rate = vexpress_osc_clk_set_rate, #endif }; diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c index b62b4646f4e..a8505f62bba 100644 --- a/drivers/clk/clk_zynq.c +++ b/drivers/clk/clk_zynq.c @@ -43,13 +43,13 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD enum zynq_clk_rclk {mio_clk, emio_clk}; #endif struct zynq_clk_priv { ulong ps_clk_freq; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD struct clk gem_emio_clk[2]; #endif }; @@ -75,7 +75,7 @@ static void *zynq_clk_get_register(enum zynq_clk id) return &slcr_base->uart_clk_ctrl; case spi0_clk ... spi1_clk: return &slcr_base->spi_clk_ctrl; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case dci_clk: return &slcr_base->dci_clk_ctrl; case gem0_clk: @@ -150,7 +150,7 @@ static ulong zynq_clk_get_pll_rate(struct zynq_clk_priv *priv, enum zynq_clk id) return priv->ps_clk_freq * mul; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static enum zynq_clk_rclk zynq_clk_get_gem_rclk(enum zynq_clk id) { u32 clk_ctrl, srcsel; @@ -199,7 +199,7 @@ static ulong zynq_clk_get_cpu_rate(struct zynq_clk_priv *priv, enum zynq_clk id) return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, pll), div); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong zynq_clk_get_ddr2x_rate(struct zynq_clk_priv *priv) { u32 clk_ctrl, div; @@ -223,7 +223,7 @@ static ulong zynq_clk_get_ddr3x_rate(struct zynq_clk_priv *priv) return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, ddrpll_clk), div); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong zynq_clk_get_dci_rate(struct zynq_clk_priv *priv) { u32 clk_ctrl, div0, div1; @@ -251,7 +251,7 @@ static ulong zynq_clk_get_peripheral_rate(struct zynq_clk_priv *priv, if (!div0) div0 = 1; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD if (two_divs) { div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; if (!div1) @@ -268,7 +268,7 @@ static ulong zynq_clk_get_peripheral_rate(struct zynq_clk_priv *priv, div1); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong zynq_clk_get_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id) { struct clk *parent; @@ -366,7 +366,7 @@ static ulong zynq_clk_set_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id, } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong zynq_clk_get_rate(struct clk *clk) { struct zynq_clk_priv *priv = dev_get_priv(clk->dev); @@ -502,7 +502,7 @@ static void zynq_clk_dump(struct udevice *dev) static struct clk_ops zynq_clk_ops = { .get_rate = zynq_clk_get_rate, -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD .set_rate = zynq_clk_set_rate, #endif .enable = dummy_enable, @@ -514,7 +514,7 @@ static struct clk_ops zynq_clk_ops = { static int zynq_clk_probe(struct udevice *dev) { struct zynq_clk_priv *priv = dev_get_priv(dev); -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD unsigned int i; char name[16]; int ret; diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile index 734100e2bff..77385864fef 100644 --- a/drivers/clk/exynos/Makefile +++ b/drivers/clk/exynos/Makefile @@ -7,6 +7,6 @@ # Thomas Abraham <thomas.ab@samsung.com> # Sam Protsenko <semen.protsenko@linaro.org> -obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-pll.o +obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk.o clk-pll.o obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o obj-$(CONFIG_CLK_EXYNOS850) += clk-exynos850.o diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 6d4bcd35714..a89ee7acb12 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -2,25 +2,25 @@ # # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-gate2.o clk-pllv3.o clk-pfd.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMX6Q) += clk-imx6q.o +obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk-gate2.o clk-pllv3.o clk-pfd.o +obj-$(CONFIG_$(PHASE_)CLK_IMX6Q) += clk-imx6q.o obj-$(CONFIG_CLK_IMX8) += clk-imx8.o ifdef CONFIG_CLK_IMX8 obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o obj-$(CONFIG_IMX8QM) += clk-imx8qm.o endif -obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \ +obj-$(CONFIG_$(PHASE_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \ clk-composite-8m.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \ +obj-$(CONFIG_$(PHASE_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \ clk-composite-8m.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \ +obj-$(CONFIG_$(PHASE_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \ clk-composite-8m.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \ +obj-$(CONFIG_$(PHASE_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \ clk-composite-8m.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMX93) += clk-imx93.o clk-fracn-gppll.o \ +obj-$(CONFIG_$(PHASE_)CLK_IMX93) += clk-imx93.o clk-fracn-gppll.o \ clk-gate-93.o clk-composite-93.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o -obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1170) += clk-imxrt1170.o +obj-$(CONFIG_$(PHASE_)CLK_IMXRT1020) += clk-imxrt1020.o +obj-$(CONFIG_$(PHASE_)CLK_IMXRT1050) += clk-imxrt1050.o +obj-$(CONFIG_$(PHASE_)CLK_IMXRT1170) += clk-imxrt1170.o diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index a91c6767fac..bb6958f0ec2 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -31,7 +31,7 @@ static const char * const imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static const char * const imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; @@ -95,7 +95,7 @@ static const char * const imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_ "sys_pll1_160m", "sys_pll1_200m", }; #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static const char * const imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; @@ -357,7 +357,7 @@ static int imx8mm_clk_probe(struct udevice *dev) imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); /* clks not needed in SPL stage */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD clk_dm(IMX8MM_CLK_ENET_AXI, imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels, base + 0x8880)); diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 125215e84f4..be15ebd0e25 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -37,7 +37,7 @@ static const char * const imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_2 "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", }; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static const char * const imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", }; @@ -97,7 +97,7 @@ static const char * const imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m" "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static const char * const imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; @@ -359,7 +359,7 @@ static int imx8mn_clk_probe(struct udevice *dev) imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); /* clks not needed in SPL stage */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD clk_dm(IMX8MN_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels, base + 0xa980)); diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 34d91cd6880..1d04090ca00 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -197,6 +197,8 @@ static int imx8mp_clk_probe(struct udevice *dev) base = (void *)ANATOP_BASE_ADDR; + clk_dm(IMX8MP_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0)); + clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c index c80b02975aa..752434cb0ad 100644 --- a/drivers/clk/imx/clk-imxrt1020.c +++ b/drivers/clk/imx/clk-imxrt1020.c @@ -124,7 +124,7 @@ static int imxrt1020_clk_probe(struct udevice *dev) clk_dm(IMXRT1020_CLK_SEMC, imx_clk_gate2("semc", "semc_podf", base + 0x74, 4)); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct clk *clk, *clk1; clk_get_by_id(IMXRT1020_CLK_SEMC_SEL, &clk1); diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index 754f3948427..788e0650a92 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -180,7 +180,7 @@ static int imxrt1050_clk_probe(struct udevice *dev) struct clk *clk, *clk1; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* bypass pll1 before setting its rate */ clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk); clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1); diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 72ad4fd0e85..51f124869c9 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -66,6 +66,8 @@ #define CLKID_VDEC_HEVC_SEL 154 #define CLKID_VDEC_HEVC_DIV 155 +#define CLKID_XTAL 0x10000000 + #define XTAL_RATE 24000000 struct meson_clk { @@ -192,6 +194,7 @@ static struct meson_gate gates[] = { MESON_GATE(CLKID_VAPB_0, HHI_VAPBCLK_CNTL, 8), MESON_GATE(CLKID_VAPB_1, HHI_VAPBCLK_CNTL, 24), MESON_GATE(CLKID_VAPB, HHI_VAPBCLK_CNTL, 30), + MESON_GATE(CLKID_HDMI, HHI_HDMI_CLK_CNTL, 8), }; static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on) @@ -267,6 +270,12 @@ static struct parm meson_vapb_1_div_parm = { int meson_vapb_1_div_parent = CLKID_VAPB_1_SEL; +static struct parm meson_hdmi_div_parm = { + HHI_HDMI_CLK_CNTL, 0, 7, +}; + +int meson_hdmi_div_parent = CLKID_HDMI_SEL; + static ulong meson_div_get_rate(struct clk *clk, unsigned long id) { struct meson_clk *priv = dev_get_priv(clk->dev); @@ -292,6 +301,10 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id) parm = &meson_vapb_1_div_parm; parent = meson_vapb_1_div_parent; break; + case CLKID_HDMI_DIV: + parm = &meson_hdmi_div_parm; + parent = meson_hdmi_div_parent; + break; default: return -ENOENT; } @@ -347,6 +360,10 @@ static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate, parm = &meson_vapb_1_div_parm; parent = meson_vapb_1_div_parent; break; + case CLKID_HDMI_DIV: + parm = &meson_hdmi_div_parm; + parent = meson_hdmi_div_parent; + break; default: return -ENOENT; } @@ -443,6 +460,17 @@ static int meson_vapb_0_1_mux_parents[] = { CLKID_FCLK_DIV7, }; +static struct parm meson_hdmi_mux_parm = { + HHI_HDMI_CLK_CNTL, 9, 2, +}; + +static int meson_hdmi_mux_parents[] = { + CLKID_XTAL, + CLKID_FCLK_DIV4, + CLKID_FCLK_DIV3, + CLKID_FCLK_DIV5, +}; + static ulong meson_mux_get_parent(struct clk *clk, unsigned long id) { struct meson_clk *priv = dev_get_priv(clk->dev); @@ -475,6 +503,10 @@ static ulong meson_mux_get_parent(struct clk *clk, unsigned long id) parm = &meson_vapb_1_mux_parm; parents = meson_vapb_0_1_mux_parents; break; + case CLKID_HDMI_SEL: + parm = &meson_hdmi_mux_parm; + parents = meson_hdmi_mux_parents; + break; default: return -ENOENT; } @@ -532,6 +564,10 @@ static ulong meson_mux_set_parent(struct clk *clk, unsigned long id, parm = &meson_vapb_1_mux_parm; parents = meson_vapb_0_1_mux_parents; break; + case CLKID_HDMI_SEL: + parm = &meson_hdmi_mux_parm; + parents = meson_hdmi_mux_parents; + break; default: /* Not a mux */ return -ENOENT; @@ -572,7 +608,7 @@ static unsigned long meson_clk81_get_rate(struct clk *clk) unsigned long parent_rate; uint reg; int parents[] = { - -1, + CLKID_XTAL, -1, CLKID_FCLK_DIV7, CLKID_MPLL1, @@ -727,6 +763,9 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id) ulong rate; switch (id) { + case CLKID_XTAL: + rate = XTAL_RATE; + break; case CLKID_FIXED_PLL: case CLKID_SYS_PLL: rate = meson_pll_get_rate(clk, id); @@ -769,10 +808,14 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id) case CLKID_VAPB_1: rate = meson_div_get_rate(clk, CLKID_VAPB_1_DIV); break; + case CLKID_HDMI: + rate = meson_div_get_rate(clk, CLKID_HDMI_DIV); + break; case CLKID_VPU_0_DIV: case CLKID_VPU_1_DIV: case CLKID_VAPB_0_DIV: case CLKID_VAPB_1_DIV: + case CLKID_HDMI_DIV: rate = meson_div_get_rate(clk, id); break; case CLKID_VPU: @@ -781,6 +824,7 @@ static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id) case CLKID_VAPB_SEL: case CLKID_VAPB_0_SEL: case CLKID_VAPB_1_SEL: + case CLKID_HDMI_SEL: rate = meson_mux_get_rate(clk, id); break; default: @@ -851,7 +895,11 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id, case CLKID_VPU_1_DIV: case CLKID_VAPB_0_DIV: case CLKID_VAPB_1_DIV: + case CLKID_HDMI_DIV: return meson_div_set_rate(clk, id, rate, current_rate); + case CLKID_HDMI: + return meson_clk_set_rate_by_id(clk, CLKID_HDMI_DIV, + rate, current_rate); default: return -ENOENT; } diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index b44d5603edd..7875a990c2f 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -55,6 +55,17 @@ enum clk_ids { DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \ .offset = _offset) +#define CPG_PLL20CR 0x0834 /* PLL20 Control Register */ +#define CPG_PLL21CR 0x0838 /* PLL21 Control Register */ +#define CPG_PLL30CR 0x083c /* PLL30 Control Register */ +#define CPG_PLL31CR 0x0840 /* PLL31 Control Register */ + +#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */ +#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */ +#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */ +#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */ +#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */ + static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -64,10 +75,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), - DEF_PLL(".pll20", CLK_PLL20, 0x0834), - DEF_PLL(".pll21", CLK_PLL21, 0x0838), - DEF_PLL(".pll30", CLK_PLL30, 0x083c), - DEF_PLL(".pll31", CLK_PLL31, 0x0840), + DEF_PLL(".pll20", CLK_PLL20, CPG_PLL20CR), + DEF_PLL(".pll21", CLK_PLL21, CPG_PLL21CR), + DEF_PLL(".pll30", CLK_PLL30, CPG_PLL30CR), + DEF_PLL(".pll31", CLK_PLL31, CPG_PLL31CR), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1), @@ -110,17 +121,17 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1), - DEF_GEN4_SDH("sd0h", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870), - DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870), + DEF_GEN4_SDH("sd0h", R8A779A0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR), + DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, CPG_SD0CKCR), DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779A0_CLK_RPC), - DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), - DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), - DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880), - DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884), + DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR), + DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, CPG_CANFDCKCR), + DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, CPG_CSICKCR), + DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, CPG_DSIEXTCKCR), DEF_GEN4_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8), DEF_GEN4_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index ea98bc6e50c..fdca63a3e8e 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -15,6 +15,12 @@ #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" +#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */ +#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */ +#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */ +#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */ +#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */ + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A779F0_CLK_R, @@ -110,13 +116,13 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1), DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1), - DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, 0x870), - DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, 0x870), + DEF_GEN4_SDH("sd0h", R8A779F0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR), + DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, R8A779F0_CLK_SD0H, CPG_SD0CKCR), DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC), - DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), + DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR), DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8), DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index 4df0a69cfe1..9fb672a5369 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -15,6 +15,12 @@ #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" +#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */ +#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */ +#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */ +#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */ +#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */ + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A779G0_CLK_CP, @@ -141,14 +147,14 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1), DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1), DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1), - DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), - DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, 0x880), + DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, CPG_CANFDCKCR), + DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, CPG_CSICKCR), DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1), - DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884), + DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, CPG_DSIEXTCKCR), - DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870), - DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870), - DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), + DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR), + DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, CPG_SD0CKCR), + DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR), DEF_BASE("rpc", R8A779G0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), DEF_BASE("rpcd2", R8A779G0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC), diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index b20d559bee2..2e98e262fb0 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -15,6 +15,12 @@ #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" +#define CPG_SD0CKCR 0x870 /* SD-IF0 Clock Frequency Control Register */ +#define CPG_CANFDCKCR 0x878 /* CAN-FD Clock Frequency Control Register */ +#define CPG_MSOCKCR 0x87c /* MSIOF Clock Frequency Control Register */ +#define CPG_CSICKCR 0x880 /* CSI Clock Frequency Control Register */ +#define CPG_DSIEXTCKCR 0x884 /* DSI Clock Frequency Control Register */ + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A779H0_CLK_R, @@ -155,14 +161,14 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { DEF_FIXED("viobusd2", R8A779H0_CLK_VIOBUSD2, CLK_VIOSRC, 2, 1), DEF_FIXED("vcbusd1", R8A779H0_CLK_VCBUSD1, CLK_VCSRC, 1, 1), DEF_FIXED("vcbusd2", R8A779H0_CLK_VCBUSD2, CLK_VCSRC, 2, 1), - DEF_DIV6P1("canfd", R8A779H0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), - DEF_DIV6P1("csi", R8A779H0_CLK_CSI, CLK_PLL5_DIV4, 0x880), + DEF_DIV6P1("canfd", R8A779H0_CLK_CANFD, CLK_PLL5_DIV4, CPG_CANFDCKCR), + DEF_DIV6P1("csi", R8A779H0_CLK_CSI, CLK_PLL5_DIV4, CPG_CSICKCR), DEF_FIXED("dsiref", R8A779H0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1), - DEF_DIV6P1("dsiext", R8A779H0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884), - DEF_DIV6P1("mso", R8A779H0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), + DEF_DIV6P1("dsiext", R8A779H0_CLK_DSIEXT, CLK_PLL5_DIV4, CPG_DSIEXTCKCR), + DEF_DIV6P1("mso", R8A779H0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR), - DEF_GEN4_SDH("sd0h", R8A779H0_CLK_SD0H, CLK_SDSRC, 0x870), - DEF_GEN4_SD("sd0", R8A779H0_CLK_SD0, R8A779H0_CLK_SD0H, 0x870), + DEF_GEN4_SDH("sd0h", R8A779H0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR), + DEF_GEN4_SD("sd0", R8A779H0_CLK_SD0, R8A779H0_CLK_SD0H, CPG_SD0CKCR), DEF_BASE("rpc", R8A779H0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), DEF_BASE("rpcd2", R8A779H0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779H0_CLK_RPC), @@ -175,6 +181,9 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC), DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC), DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC), + DEF_MOD("canfd0", 328, R8A779H0_CLK_SASYNCPERD2), + DEF_MOD("csi40", 331, R8A779H0_CLK_CSI), + DEF_MOD("csi41", 400, R8A779H0_CLK_CSI), DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), @@ -183,14 +192,57 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER), DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER), DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER), + DEF_MOD("irqc", 611, R8A779H0_CLK_CL16M), + DEF_MOD("ispcs0", 612, R8A779H0_CLK_S0D2_VIO), + DEF_MOD("ispcs1", 613, R8A779H0_CLK_S0D2_VIO), + DEF_MOD("msi0", 618, R8A779H0_CLK_MSO), + DEF_MOD("msi1", 619, R8A779H0_CLK_MSO), + DEF_MOD("msi2", 620, R8A779H0_CLK_MSO), + DEF_MOD("msi3", 621, R8A779H0_CLK_MSO), + DEF_MOD("msi4", 622, R8A779H0_CLK_MSO), + DEF_MOD("msi5", 623, R8A779H0_CLK_MSO), + DEF_MOD("pcie0", 624, R8A779H0_CLK_S0D2_HSC), + DEF_MOD("pwm", 628, R8A779H0_CLK_SASYNCPERD4), DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2), + DEF_MOD("scif0", 702, R8A779H0_CLK_SASYNCPERD4), + DEF_MOD("scif1", 703, R8A779H0_CLK_SASYNCPERD4), + DEF_MOD("scif3", 704, R8A779H0_CLK_SASYNCPERD4), + DEF_MOD("scif4", 705, R8A779H0_CLK_SASYNCPERD4), DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0), DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER), DEF_MOD("sydm2", 710, R8A779H0_CLK_S0D6_PER), + DEF_MOD("tmu0", 713, R8A779H0_CLK_SASYNCRT), + DEF_MOD("tmu1", 714, R8A779H0_CLK_SASYNCPERD2), + DEF_MOD("tmu2", 715, R8A779H0_CLK_SASYNCPERD2), + DEF_MOD("tmu3", 716, R8A779H0_CLK_SASYNCPERD2), + DEF_MOD("tmu4", 717, R8A779H0_CLK_SASYNCPERD2), + DEF_MOD("vin00", 730, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin01", 731, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin02", 800, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin03", 801, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin04", 802, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin05", 803, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin06", 804, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin07", 805, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin10", 806, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin11", 807, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin12", 808, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin13", 809, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin14", 810, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO), + DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO), DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R), + DEF_MOD("cmt0", 910, R8A779H0_CLK_R), + DEF_MOD("cmt1", 911, R8A779H0_CLK_R), + DEF_MOD("cmt2", 912, R8A779H0_CLK_R), + DEF_MOD("cmt3", 913, R8A779H0_CLK_R), DEF_MOD("pfc0", 915, R8A779H0_CLK_CP), DEF_MOD("pfc1", 916, R8A779H0_CLK_CP), DEF_MOD("pfc2", 917, R8A779H0_CLK_CP), + DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M), + DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER), + DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER), }; /* diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index d7825c66493..22ede1c38a8 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -989,7 +989,7 @@ static ulong px30_peri_set_clk(struct px30_clk_priv *priv, ulong clk_id, return px30_peri_get_clk(priv, clk_id); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong px30_crypto_get_clk(struct px30_clk_priv *priv, ulong clk_id) { struct px30_cru *cru = priv->cru; @@ -1261,7 +1261,7 @@ static ulong px30_clk_get_rate(struct clk *clk) case HCLK_PERI_PRE: rate = px30_peri_get_clk(priv, clk->id); break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case SCLK_CRYPTO: case SCLK_CRYPTO_APK: rate = px30_crypto_get_clk(priv, clk->id); @@ -1345,7 +1345,7 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate) case HCLK_PERI_PRE: ret = px30_peri_set_clk(priv, clk->id, rate); break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case SCLK_CRYPTO: case SCLK_CRYPTO_APK: ret = px30_crypto_set_clk(priv, clk->id, rate); diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index f569a100f22..d8b03e1d7ab 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -80,7 +80,7 @@ enum { "divisors on line " __stringify(__LINE__)); /* Keep divisors as low as possible to reduce jitter and power usage */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); #endif @@ -371,7 +371,7 @@ static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate, return rockchip_spi_get_clk(cru, gclk_rate, periph); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf, bool has_bwadj) { @@ -557,7 +557,7 @@ static int rk3188_clk_probe(struct udevice *dev) return PTR_ERR(priv->grf); priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3188_clk_plat *plat = dev_get_plat(dev); diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 432a79291c8..43c44fadbe7 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -223,7 +223,7 @@ static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf, return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define VCO_MAX_KHZ 2200000 #define VCO_MIN_KHZ 440000 #define FREF_MAX_KHZ 2200000 @@ -421,7 +421,7 @@ static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate, return rockchip_i2s_get_clk(cru, gclk_rate); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf) { @@ -819,7 +819,7 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SPI2: new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate); break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case SCLK_I2S0: new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate); break; @@ -973,7 +973,7 @@ static int rk3288_clk_probe(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); if (IS_ERR(priv->grf)) return PTR_ERR(priv->grf); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3288_clk_plat *plat = dev_get_plat(dev); diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 9137dbe69ce..7701a9734ee 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -582,7 +582,7 @@ static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz) return rk3328_spi_get_clk(cru); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong rk3328_vop_get_clk(struct rk3328_clk_priv *priv, ulong clk_id) { struct rk3328_cru *cru = priv->cru; @@ -746,7 +746,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SPI: ret = rk3328_spi_set_clk(priv->cru, rate); break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case DCLK_LCDC: case ACLK_VOP_PRE: case ACLK_VIO_PRE: diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index d8943980521..630253fbb1d 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -50,7 +50,7 @@ struct pll_div { (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \ "divisors on line " __stringify(__LINE__)); -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) +#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2); #if !defined(CONFIG_TPL_BUILD) @@ -88,7 +88,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, } } -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) +#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, const struct pll_div *div) { @@ -130,7 +130,7 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, } #endif -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) +#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) static void rkclk_init(struct rk3368_cru *cru) { u32 apllb, aplll, dpll, cpll, gpll; @@ -157,7 +157,7 @@ static void rkclk_init(struct rk3368_cru *cru) } #endif -#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC) +#if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC) static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id) { u32 div, con, con_id, rate; @@ -469,7 +469,7 @@ static ulong rk3368_clk_get_rate(struct clk *clk) case SCLK_SPI0 ... SCLK_SPI2: rate = rk3368_spi_get_clk(priv->cru, clk->id); break; -#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC) +#if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC) case HCLK_SDMMC: case HCLK_EMMC: rate = rk3368_mmc_get_clk(priv->cru, clk->id); @@ -500,7 +500,7 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) ret = rk3368_ddr_set_clk(priv->cru, rate); break; #endif -#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC) +#if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC) case HCLK_SDMMC: case HCLK_EMMC: ret = rk3368_mmc_set_clk(clk, rate); @@ -586,7 +586,7 @@ static int rk3368_clk_probe(struct udevice *dev) priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); #endif -#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) +#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD) rkclk_init(priv->cru); #endif diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 89924041299..155ea8d6353 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -56,7 +56,7 @@ struct pll_div { static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); #endif @@ -1464,7 +1464,7 @@ static int rk3399_clk_probe(struct udevice *dev) priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); #endif -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) init_clocks = true; #elif CONFIG_IS_ENABLED(HANDOFF) if (!(gd->flags & GD_FLG_RELOC)) { @@ -1658,7 +1658,7 @@ static struct clk_ops rk3399_pmuclk_ops = { .set_rate = rk3399_pmuclk_set_rate, }; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static void pmuclk_init(struct rk3399_pmucru *pmucru) { u32 pclk_div; @@ -1676,7 +1676,7 @@ static void pmuclk_init(struct rk3399_pmucru *pmucru) static int rk3399_pmuclk_probe(struct udevice *dev) { -#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD) +#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_XPL_BUILD) struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); #endif @@ -1686,7 +1686,7 @@ static int rk3399_pmuclk_probe(struct udevice *dev) priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD pmuclk_init(priv->pmucru); #endif return 0; diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 35563509d61..977699d509d 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -91,7 +91,7 @@ static struct rockchip_pll_clock rk3568_pll_clks[] = { RK3568_PMU_MODE, 2, 10, 0, rk3568_pll_rates), }; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong rk3568_pmu_pll_set_rate(struct rk3568_clk_priv *priv, ulong pll_id, ulong rate) @@ -1707,7 +1707,7 @@ static ulong rk3568_emmc_set_bclk(struct rk3568_clk_priv *priv, ulong rate) return rk3568_emmc_get_bclk(priv); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong rk3568_aclk_vop_get_clk(struct rk3568_clk_priv *priv) { struct rk3568_cru *cru = priv->cru; @@ -2413,7 +2413,7 @@ static ulong rk3568_clk_get_rate(struct clk *clk) case TCLK_EMMC: rate = OSC_HZ; break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case ACLK_VOP: rate = rk3568_aclk_vop_get_clk(priv); break; @@ -2594,7 +2594,7 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) case TCLK_EMMC: ret = OSC_HZ; break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case ACLK_VOP: ret = rk3568_aclk_vop_set_clk(priv, rate); break; @@ -2894,7 +2894,7 @@ static void rk3568_clk_init(struct rk3568_clk_priv *priv) priv->gpll_hz = GPLL_HZ; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD ret = rk3568_bus_set_clk(priv, ACLK_BUS, 150000000); if (ret < 0) printf("Fail to set the ACLK_BUS clock.\n"); diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index db1384dacd2..6042fc10cdb 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -65,7 +65,7 @@ static struct rockchip_pll_clock rk3588_pll_clks[] = { RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates), [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128), RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates), -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * The SPLL is part of the SBUSCRU, not the main CRU and as * such only directly accessible during the SPL stage. @@ -76,7 +76,7 @@ static struct rockchip_pll_clock rk3588_pll_clks[] = { }; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * * rational_best_approximation(31415, 10000, @@ -875,7 +875,7 @@ static ulong rk3588_mmc_set_clk(struct rk3588_clk_priv *priv, return rk3588_mmc_get_clk(priv, clk_id); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong rk3588_aux16m_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) { struct rk3588_cru *cru = priv->cru; @@ -1600,7 +1600,7 @@ static ulong rk3588_clk_get_rate(struct clk *clk) case CLK_GPU: rate = 200000000; break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case CLK_AUX16M_0: case CLK_AUX16M_1: rate = rk3588_aux16m_get_clk(priv, clk->id); @@ -1760,7 +1760,7 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate) case CLK_150M_SRC: ret = 0; break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case CLK_AUX16M_0: case CLK_AUX16M_1: ret = rk3588_aux16m_set_clk(priv, clk->id, rate); @@ -1965,7 +1965,7 @@ static int rk3588_clk_probe(struct udevice *dev) priv->sync_kernel = false; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD rockchip_pll_set_rate(&rk3588_pll_clks[B0PLL], priv->cru, B0PLL, LPLL_HZ); rockchip_pll_set_rate(&rk3588_pll_clks[B1PLL], priv->cru, @@ -2051,7 +2051,7 @@ U_BOOT_DRIVER(rockchip_rk3588_cru) = { .probe = rk3588_clk_probe, }; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define SCRU_BASE 0xfd7d0000 #define SBUSCRU_BASE 0xfd7d8000 diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index aa26d3a109b..de55504b5c9 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -670,7 +670,7 @@ static int sifive_prci_probe(struct udevice *dev) __prci_wrpll_read_cfg0(pd, pc->pwd); } - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { if (device_is_compatible(dev, "sifive,fu740-c000-prci")) { u32 prci_pll_reg; unsigned long parent_rate; diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c index 581035842fc..6d2bfb3ecb7 100644 --- a/drivers/clk/starfive/clk-jh7110-pll.c +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -348,10 +348,10 @@ struct clk *starfive_jh7110_pll(const char *name, const char *parent_name, return ERR_PTR(ret); } - if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL0) + if (IS_ENABLED(CONFIG_XPL_BUILD) && pll->type == PLL0) jh7110_pllx_set_rate(clk, 1000000000); - if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL2) + if (IS_ENABLED(CONFIG_XPL_BUILD) && pll->type == PLL2) jh7110_pllx_set_rate(clk, 1188000000); return clk; diff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c index 204ac170531..4044edfb768 100644 --- a/drivers/clk/stm32/clk-stm32mp1.c +++ b/drivers/clk/stm32/clk-stm32mp1.c @@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) /* activate clock tree initialization in the driver */ #define STM32MP1_CLOCK_TREE_INIT #endif @@ -2279,7 +2279,7 @@ static int stm32mp1_clk_probe(struct udevice *dev) dev_err(dev, "clock tree initialization failed (%d)\n", result); #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #if defined(VERBOSE_DEBUG) /* display debug information for probe after relocation */ if (gd->flags & GD_FLG_RELOC) @@ -2314,7 +2314,7 @@ static const struct clk_ops stm32mp1_clk_ops = { .disable = stm32mp1_clk_disable, .get_rate = stm32mp1_clk_get_rate, .set_rate = stm32mp1_clk_set_rate, -#if IS_ENABLED(CONFIG_CMD_CLK) && !IS_ENABLED(CONFIG_SPL_BUILD) +#if IS_ENABLED(CONFIG_CMD_CLK) && !IS_ENABLED(CONFIG_XPL_BUILD) .dump = stm32mp1_clk_dump, #endif }; diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index 6751af8a803..091aaeee987 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -75,10 +75,10 @@ static const struct ccu_clk_gate a80_mmc_gates[] = { }; static const struct ccu_reset a80_mmc_resets[] = { - [0] = GATE(0x0, BIT(18)), - [1] = GATE(0x4, BIT(18)), - [2] = GATE(0x8, BIT(18)), - [3] = GATE(0xc, BIT(18)), + [0] = RESET(0x0, BIT(18)), + [1] = RESET(0x4, BIT(18)), + [2] = RESET(0x8, BIT(18)), + [3] = RESET(0xc, BIT(18)), }; const struct ccu_desc a80_ccu_desc = { diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 07aa9a53e08..a58f19f46d9 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -11,5 +11,5 @@ obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o -obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o -obj-$(CONFIG_$(SPL_TPL_)CLK_K3) += clk-k3.o +obj-$(CONFIG_$(PHASE_)CLK_K3_PLL) += clk-k3-pll.o +obj-$(CONFIG_$(PHASE_)CLK_K3) += clk-k3.o |