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-rw-r--r--drivers/clk/rockchip/clk_rk3399.c66
-rw-r--r--drivers/clk/sifive/fu740-prci.c18
-rw-r--r--drivers/clk/sifive/sifive-prci.c4
3 files changed, 54 insertions, 34 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 7d31a9f22a8..97bf1c6e15b 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -728,6 +728,12 @@ static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
u32 div, con;
switch (clk_id) {
+ case HCLK_SDIO:
+ case SCLK_SDIO:
+ con = readl(&cru->clksel_con[15]);
+ /* dwmmc controller have internal div 2 */
+ div = 2;
+ break;
case HCLK_SDMMC:
case SCLK_SDMMC:
con = readl(&cru->clksel_con[16]);
@@ -750,37 +756,46 @@ static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
return DIV_TO_RATE(GPLL_HZ, div);
}
+static void rk3399_dwmmc_set_clk(struct rockchip_cru *cru,
+ unsigned int con, ulong set_rate)
+{
+ /* Select clk_sdmmc source from GPLL by default */
+ /* mmc clock defaulg div 2 internal, provide double in cru */
+ int src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
+
+ if (src_clk_div > 128) {
+ /* use 24MHz source for 400KHz clock */
+ src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
+ assert(src_clk_div - 1 < 128);
+ rk_clrsetreg(&cru->clksel_con[con],
+ CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
+ CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
+ (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
+ } else {
+ rk_clrsetreg(&cru->clksel_con[con],
+ CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
+ CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
+ (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
+ }
+}
+
static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
ulong clk_id, ulong set_rate)
{
- int src_clk_div;
- int aclk_emmc = 198 * MHz;
-
switch (clk_id) {
+ case HCLK_SDIO:
+ case SCLK_SDIO:
+ rk3399_dwmmc_set_clk(cru, 15, set_rate);
+ break;
case HCLK_SDMMC:
case SCLK_SDMMC:
- /* Select clk_sdmmc source from GPLL by default */
- /* mmc clock defaulg div 2 internal, provide double in cru */
- src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
-
- if (src_clk_div > 128) {
- /* use 24MHz source for 400KHz clock */
- src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
- assert(src_clk_div - 1 < 128);
- rk_clrsetreg(&cru->clksel_con[16],
- CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
- CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
- (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
- } else {
- rk_clrsetreg(&cru->clksel_con[16],
- CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
- CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
- (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
- }
+ rk3399_dwmmc_set_clk(cru, 16, set_rate);
break;
- case SCLK_EMMC:
+ case SCLK_EMMC: {
+ int aclk_emmc = 198 * MHz;
/* Select aclk_emmc source from GPLL */
- src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
+ int src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
+
assert(src_clk_div - 1 < 32);
rk_clrsetreg(&cru->clksel_con[21],
@@ -797,6 +812,7 @@ static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
(src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
break;
+ }
default:
return -EINVAL;
}
@@ -918,6 +934,8 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
switch (clk->id) {
case 0 ... 63:
return 0;
+ case HCLK_SDIO:
+ case SCLK_SDIO:
case HCLK_SDMMC:
case SCLK_SDMMC:
case SCLK_EMMC:
@@ -992,6 +1010,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
case PCLK_PERILP1:
return 0;
+ case HCLK_SDIO:
+ case SCLK_SDIO:
case HCLK_SDMMC:
case SCLK_SDMMC:
case SCLK_EMMC:
diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c
index b025050e224..5edc864e4bd 100644
--- a/drivers/clk/sifive/fu740-prci.c
+++ b/drivers/clk/sifive/fu740-prci.c
@@ -103,53 +103,53 @@ static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = {
/* List of clock controls provided by the PRCI */
struct __prci_clock __prci_init_clocks_fu740[] = {
- [PRCI_CLK_COREPLL] = {
+ [FU740_PRCI_CLK_COREPLL] = {
.name = "corepll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_corepll_data,
},
- [PRCI_CLK_DDRPLL] = {
+ [FU740_PRCI_CLK_DDRPLL] = {
.name = "ddrpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_ddrpll_data,
},
- [PRCI_CLK_GEMGXLPLL] = {
+ [FU740_PRCI_CLK_GEMGXLPLL] = {
.name = "gemgxlpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_gemgxlpll_data,
},
- [PRCI_CLK_DVFSCOREPLL] = {
+ [FU740_PRCI_CLK_DVFSCOREPLL] = {
.name = "dvfscorepll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_dvfscorepll_data,
},
- [PRCI_CLK_HFPCLKPLL] = {
+ [FU740_PRCI_CLK_HFPCLKPLL] = {
.name = "hfpclkpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_hfpclkpll_data,
},
- [PRCI_CLK_CLTXPLL] = {
+ [FU740_PRCI_CLK_CLTXPLL] = {
.name = "cltxpll",
.parent_name = "hfclk",
.ops = &sifive_fu740_prci_wrpll_clk_ops,
.pwd = &__prci_cltxpll_data,
},
- [PRCI_CLK_TLCLK] = {
+ [FU740_PRCI_CLK_TLCLK] = {
.name = "tlclk",
.parent_name = "corepll",
.ops = &sifive_fu740_prci_tlclksel_clk_ops,
},
- [PRCI_CLK_PCLK] = {
+ [FU740_PRCI_CLK_PCLK] = {
.name = "pclk",
.parent_name = "hfpclkpll",
.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
},
- [PRCI_CLK_PCIEAUX] {
+ [FU740_PRCI_CLK_PCIE_AUX] {
.name = "pcieaux",
.parent_name = "",
.ops = &sifive_fu740_prci_pcieaux_clk_ops,
diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c
index 52ae268e0c8..c8fb6002907 100644
--- a/drivers/clk/sifive/sifive-prci.c
+++ b/drivers/clk/sifive/sifive-prci.c
@@ -685,14 +685,14 @@ static int sifive_prci_probe(struct udevice *dev)
* case the design uses hfpclk to drive
* Chiplink
*/
- pc = &data->clks[PRCI_CLK_HFPCLKPLL];
+ pc = &data->clks[FU740_PRCI_CLK_HFPCLKPLL];
parent_rate = sifive_prci_parent_rate(pc, data);
sifive_prci_wrpll_set_rate(pc, 260000000,
parent_rate);
pc->ops->enable_clk(pc, 1);
} else if (prci_pll_reg & PRCI_PRCIPLL_CLTXPLL) {
/* CLTX pll init */
- pc = &data->clks[PRCI_CLK_CLTXPLL];
+ pc = &data->clks[FU740_PRCI_CLK_CLTXPLL];
parent_rate = sifive_prci_parent_rate(pc, data);
sifive_prci_wrpll_set_rate(pc, 260000000,
parent_rate);
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-18 13:39:50 +0000