5 files changed, 526 insertions, 0 deletions

diff --git a/drivers/ddr/imx/phy/Kconfig b/drivers/ddr/imx/phy/Kconfig
new file mode 100644
index 00000000000..d3e589b23c4
--- /dev/null
+++ b/drivers/ddr/imx/phy/Kconfig
@@ -0,0 +1,4 @@
+config IMX_SNPS_DDR_PHY
+	bool "i.MX Snopsys DDR PHY"
+	help
+	  Select the DDR PHY driver support on i.MX8M and i.MX9 SOC.
diff --git a/drivers/ddr/imx/phy/Makefile b/drivers/ddr/imx/phy/Makefile
new file mode 100644
index 00000000000..95c93ba16d5
--- /dev/null
+++ b/drivers/ddr/imx/phy/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifdef CONFIG_XPL_BUILD
+obj-$(CONFIG_IMX_SNPS_DDR_PHY) += helper.o ddrphy_utils.o ddrphy_train.o
+endif
diff --git a/drivers/ddr/imx/phy/ddrphy_train.c b/drivers/ddr/imx/phy/ddrphy_train.c
new file mode 100644
index 00000000000..1a2d071d6f1
--- /dev/null
+++ b/drivers/ddr/imx/phy/ddrphy_train.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <log.h>
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/sys_proto.h>
+
+int ddr_cfg_phy(struct dram_timing_info *dram_timing)
+{
+	struct dram_cfg_param *dram_cfg;
+	struct dram_fsp_msg *fsp_msg;
+	unsigned int num;
+	int i = 0;
+	int j = 0;
+	int ret;
+
+	/* initialize PHY configuration */
+	dram_cfg = dram_timing->ddrphy_cfg;
+	num  = dram_timing->ddrphy_cfg_num;
+	for (i = 0; i < num; i++) {
+		/* config phy reg */
+		dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
+		dram_cfg++;
+	}
+
+	/* load the frequency setpoint message block config */
+	fsp_msg = dram_timing->fsp_msg;
+	for (i = 0; i < dram_timing->fsp_msg_num; i++) {
+		debug("DRAM PHY training for %dMTS\n", fsp_msg->drate);
+		/* set dram PHY input clocks to desired frequency */
+		ddrphy_init_set_dfi_clk(fsp_msg->drate);
+
+		/* load the dram training firmware image */
+		dwc_ddrphy_apb_wr(0xd0000, 0x0);
+		ddr_load_train_firmware(fsp_msg->fw_type);
+
+		/* load the frequency set point message block parameter */
+		dram_cfg = fsp_msg->fsp_cfg;
+		num = fsp_msg->fsp_cfg_num;
+		for (j = 0; j < num; j++) {
+			dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
+			dram_cfg++;
+		}
+
+		/*
+		 * -------------------- excute the firmware --------------------
+		 * Running the firmware is a simply process to taking the
+		 * PMU out of reset and stall, then the firwmare will be run
+		 * 1. reset the PMU;
+		 * 2. begin the excution;
+		 * 3. wait for the training done;
+		 * 4. read the message block result.
+		 * -------------------------------------------------------------
+		 */
+		dwc_ddrphy_apb_wr(0xd0000, 0x1);
+		dwc_ddrphy_apb_wr(0xd0099, 0x9);
+		dwc_ddrphy_apb_wr(0xd0099, 0x1);
+		dwc_ddrphy_apb_wr(0xd0099, 0x0);
+
+		/* Wait for the training firmware to complete */
+		ret = wait_ddrphy_training_complete();
+		if (ret)
+			return ret;
+
+		/* Halt the microcontroller. */
+		dwc_ddrphy_apb_wr(0xd0099, 0x1);
+
+		/* Read the Message Block results */
+		dwc_ddrphy_apb_wr(0xd0000, 0x0);
+
+		ddrphy_init_read_msg_block(fsp_msg->fw_type);
+
+		if(fsp_msg->fw_type != FW_2D_IMAGE)
+			get_trained_CDD(i);
+
+		dwc_ddrphy_apb_wr(0xd0000, 0x1);
+
+		fsp_msg++;
+	}
+
+	/* Load PHY Init Engine Image */
+	dram_cfg = dram_timing->ddrphy_pie;
+	num = dram_timing->ddrphy_pie_num;
+	for (i = 0; i < num; i++) {
+		dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
+		dram_cfg++;
+	}
+
+	/* save the ddr PHY trained CSR in memory for low power use */
+	ddrphy_trained_csr_save(dram_timing->ddrphy_trained_csr,
+				dram_timing->ddrphy_trained_csr_num);
+
+	return 0;
+}
diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c
new file mode 100644
index 00000000000..8e350de8315
--- /dev/null
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <errno.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/sys_proto.h>
+
+static inline void poll_pmu_message_ready(void)
+{
+	unsigned int reg;
+
+	do {
+		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004));
+	} while (reg & 0x1);
+}
+
+static inline void ack_pmu_message_receive(void)
+{
+	unsigned int reg;
+
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x0);
+
+	do {
+		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004));
+	} while (!(reg & 0x1));
+
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x1);
+}
+
+static inline unsigned int get_mail(void)
+{
+	unsigned int reg;
+
+	poll_pmu_message_ready();
+
+	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032));
+
+	ack_pmu_message_receive();
+
+	return reg;
+}
+
+static inline unsigned int get_stream_message(void)
+{
+	unsigned int reg, reg2;
+
+	poll_pmu_message_ready();
+
+	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032));
+
+	reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0034));
+
+	reg2 = (reg2 << 16) | reg;
+
+	ack_pmu_message_receive();
+
+	return reg2;
+}
+
+static inline void decode_major_message(unsigned int mail)
+{
+	debug("[PMU Major message = 0x%08x]\n", mail);
+}
+
+static inline void decode_streaming_message(void)
+{
+	unsigned int string_index, arg __maybe_unused;
+	int i = 0;
+
+	string_index = get_stream_message();
+	debug("PMU String index = 0x%08x\n", string_index);
+	while (i < (string_index & 0xffff)) {
+		arg = get_stream_message();
+		debug("arg[%d] = 0x%08x\n", i, arg);
+		i++;
+	}
+
+	debug("\n");
+}
+
+int wait_ddrphy_training_complete(void)
+{
+	unsigned int mail;
+
+	while (1) {
+		mail = get_mail();
+		decode_major_message(mail);
+		if (mail == 0x08) {
+			decode_streaming_message();
+		} else if (mail == 0x07) {
+			debug("Training PASS\n");
+			return 0;
+		} else if (mail == 0xff) {
+			printf("Training FAILED\n");
+			return -1;
+		}
+	}
+}
+
+void ddrphy_init_set_dfi_clk(unsigned int drate)
+{
+	switch (drate) {
+	case 4000:
+		dram_pll_init(MHZ(1000));
+		dram_disable_bypass();
+		break;
+	case 3734:
+	case 3733:
+	case 3732:
+		dram_pll_init(MHZ(933));
+		dram_disable_bypass();
+		break;
+	case 3600:
+		dram_pll_init(MHZ(900));
+		dram_disable_bypass();
+		break;
+	case 3200:
+		dram_pll_init(MHZ(800));
+		dram_disable_bypass();
+		break;
+	case 3000:
+		dram_pll_init(MHZ(750));
+		dram_disable_bypass();
+		break;
+	case 2800:
+		dram_pll_init(MHZ(700));
+		dram_disable_bypass();
+		break;
+	case 2400:
+		dram_pll_init(MHZ(600));
+		dram_disable_bypass();
+		break;
+	case 1866:
+		dram_pll_init(MHZ(466));
+		dram_disable_bypass();
+		break;
+	case 1600:
+		dram_pll_init(MHZ(400));
+		dram_disable_bypass();
+		break;
+	case 1200:
+		dram_pll_init(MHZ(300));
+		dram_disable_bypass();
+		break;
+	case 1066:
+		dram_pll_init(MHZ(266));
+		dram_disable_bypass();
+		break;
+	case 933:
+		dram_pll_init(MHZ(233));
+		dram_disable_bypass();
+		break;
+	case 800:
+		dram_pll_init(MHZ(200));
+		dram_disable_bypass();
+		break;
+	case 667:
+		dram_pll_init(MHZ(167));
+		dram_disable_bypass();
+		break;
+	case 625:
+		dram_enable_bypass(MHZ(625));
+		break;
+	case 400:
+		dram_enable_bypass(MHZ(400));
+		break;
+	case 333:
+		dram_enable_bypass(MHZ(333));
+		break;
+	case 200:
+		dram_enable_bypass(MHZ(200));
+		break;
+	case 100:
+		dram_enable_bypass(MHZ(100));
+		break;
+	default:
+		return;
+	}
+}
+
+void ddrphy_init_read_msg_block(enum fw_type type)
+{
+}
diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c
new file mode 100644
index 00000000000..b0dfc3a0b4f
--- /dev/null
+++ b/drivers/ddr/imx/phy/helper.c
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <binman_sym.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/ddr.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMEM_LEN 32768 /* byte */
+#define DMEM_LEN 16384 /* byte */
+#define IMEM_2D_OFFSET	49152
+
+#define IMEM_OFFSET_ADDR 0x00050000
+#define DMEM_OFFSET_ADDR 0x00054000
+#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
+
+binman_sym_declare(ulong, ddr_1d_imem_fw, image_pos);
+binman_sym_declare(ulong, ddr_1d_imem_fw, size);
+
+binman_sym_declare(ulong, ddr_1d_dmem_fw, image_pos);
+binman_sym_declare(ulong, ddr_1d_dmem_fw, size);
+
+#if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
+binman_sym_declare(ulong, ddr_2d_imem_fw, image_pos);
+binman_sym_declare(ulong, ddr_2d_imem_fw, size);
+
+binman_sym_declare(ulong, ddr_2d_dmem_fw, image_pos);
+binman_sym_declare(ulong, ddr_2d_dmem_fw, size);
+#endif
+
+/* We need PHY iMEM PHY is 32KB padded */
+void ddr_load_train_firmware(enum fw_type type)
+{
+	u32 tmp32, i;
+	u32 error = 0;
+	unsigned long pr_to32, pr_from32;
+	uint32_t fw_offset = type ? IMEM_2D_OFFSET : 0;
+	unsigned long imem_start = (unsigned long)_end + fw_offset;
+	unsigned long dmem_start;
+	unsigned long imem_len = IMEM_LEN, dmem_len = DMEM_LEN;
+	static enum fw_type last_type = -1;
+
+	/* If FW doesn't change, we can save the loading. */
+	if (last_type == type)
+		return;
+
+	last_type = type;
+
+#ifdef CONFIG_SPL_OF_CONTROL
+	if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
+		imem_start = roundup((unsigned long)_end +
+				     fdt_totalsize(gd->fdt_blob), 4) +
+			fw_offset;
+	}
+#endif
+
+	dmem_start = imem_start + imem_len;
+
+	if (BINMAN_SYMS_OK) {
+		switch (type) {
+		case FW_1D_IMAGE:
+			imem_start = binman_sym(ulong, ddr_1d_imem_fw, image_pos);
+			imem_len = binman_sym(ulong, ddr_1d_imem_fw, size);
+			dmem_start = binman_sym(ulong, ddr_1d_dmem_fw, image_pos);
+			dmem_len = binman_sym(ulong, ddr_1d_dmem_fw, size);
+			break;
+		case FW_2D_IMAGE:
+#if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
+			imem_start = binman_sym(ulong, ddr_2d_imem_fw, image_pos);
+			imem_len = binman_sym(ulong, ddr_2d_imem_fw, size);
+			dmem_start = binman_sym(ulong, ddr_2d_dmem_fw, image_pos);
+			dmem_len = binman_sym(ulong, ddr_2d_dmem_fw, size);
+#endif
+			break;
+		}
+	}
+
+	pr_from32 = imem_start;
+	pr_to32 = IMEM_OFFSET_ADDR;
+	for (i = 0x0; i < imem_len; ) {
+		tmp32 = readl(pr_from32);
+		writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
+		pr_to32 += 1;
+		writew((tmp32 >> 16) & 0x0000ffff,
+		       DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
+		pr_to32 += 1;
+		pr_from32 += 4;
+		i += 4;
+	}
+
+	pr_from32 = dmem_start;
+	pr_to32 = DMEM_OFFSET_ADDR;
+	for (i = 0x0; i < dmem_len; ) {
+		tmp32 = readl(pr_from32);
+		writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
+		pr_to32 += 1;
+		writew((tmp32 >> 16) & 0x0000ffff,
+		       DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
+		pr_to32 += 1;
+		pr_from32 += 4;
+		i += 4;
+	}
+
+	debug("check ddr_pmu_train_imem code\n");
+	pr_from32 = imem_start;
+	pr_to32 = IMEM_OFFSET_ADDR;
+	for (i = 0x0; i < imem_len; ) {
+		tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff);
+		pr_to32 += 1;
+		tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR +
+			  ddrphy_addr_remap(pr_to32)) & 0x0000ffff) << 16);
+
+		if (tmp32 != readl(pr_from32)) {
+			debug("%lx %lx\n", pr_from32, pr_to32);
+			error++;
+		}
+		pr_from32 += 4;
+		pr_to32 += 1;
+		i += 4;
+	}
+	if (error)
+		printf("check ddr_pmu_train_imem code fail=%d\n", error);
+	else
+		debug("check ddr_pmu_train_imem code pass\n");
+
+	debug("check ddr4_pmu_train_dmem code\n");
+	pr_from32 = dmem_start;
+	pr_to32 = DMEM_OFFSET_ADDR;
+	for (i = 0x0; i < dmem_len;) {
+		tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff);
+		pr_to32 += 1;
+		tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR +
+			  ddrphy_addr_remap(pr_to32)) & 0x0000ffff) << 16);
+		if (tmp32 != readl(pr_from32)) {
+			debug("%lx %lx\n", pr_from32, pr_to32);
+			error++;
+		}
+		pr_from32 += 4;
+		pr_to32 += 1;
+		i += 4;
+	}
+
+	if (error)
+		printf("check ddr_pmu_train_dmem code fail=%d", error);
+	else
+		debug("check ddr_pmu_train_dmem code pass\n");
+}
+
+void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr,
+			     unsigned int num)
+{
+	int i = 0;
+
+	/* enable the ddrphy apb */
+	dwc_ddrphy_apb_wr(0xd0000, 0x0);
+	dwc_ddrphy_apb_wr(0xc0080, 0x3);
+	for (i = 0; i < num; i++) {
+		ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg);
+		ddrphy_csr++;
+	}
+	/* disable the ddrphy apb */
+	dwc_ddrphy_apb_wr(0xc0080, 0x2);
+	dwc_ddrphy_apb_wr(0xd0000, 0x1);
+}
+
+void *dram_config_save(struct dram_timing_info *timing_info, unsigned long saved_timing_base)
+{
+	int i = 0;
+	struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base;
+	struct dram_cfg_param *cfg;
+
+	saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num;
+	saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num;
+	saved_timing->ddrphy_trained_csr_num = timing_info->ddrphy_trained_csr_num;
+	saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num;
+
+	/* save the fsp table */
+	for (i = 0; i < 4; i++)
+		saved_timing->fsp_table[i] = timing_info->fsp_table[i];
+
+	cfg = (struct dram_cfg_param *)(saved_timing_base +
+					sizeof(*timing_info));
+
+	/* save ddrc config */
+	saved_timing->ddrc_cfg = cfg;
+	for (i = 0; i < timing_info->ddrc_cfg_num; i++) {
+		cfg->reg = timing_info->ddrc_cfg[i].reg;
+		cfg->val = timing_info->ddrc_cfg[i].val;
+		cfg++;
+	}
+
+	/* save ddrphy config */
+	saved_timing->ddrphy_cfg = cfg;
+	for (i = 0; i < timing_info->ddrphy_cfg_num; i++) {
+		cfg->reg = timing_info->ddrphy_cfg[i].reg;
+		cfg->val = timing_info->ddrphy_cfg[i].val;
+		cfg++;
+	}
+
+	/* save the ddrphy csr */
+	saved_timing->ddrphy_trained_csr = cfg;
+	for (i = 0; i < timing_info->ddrphy_trained_csr_num; i++) {
+		cfg->reg = timing_info->ddrphy_trained_csr[i].reg;
+		cfg->val = timing_info->ddrphy_trained_csr[i].val;
+		cfg++;
+	}
+
+	/* save the ddrphy pie */
+	saved_timing->ddrphy_pie = cfg;
+	for (i = 0; i < timing_info->ddrphy_pie_num; i++) {
+		cfg->reg = timing_info->ddrphy_pie[i].reg;
+		cfg->val = timing_info->ddrphy_pie[i].val;
+		cfg++;
+	}
+
+	return (void *)cfg;
+}