8 files changed, 0 insertions, 12 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c
index 7c5147f4745..b28b2c73a8b 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -75,7 +75,6 @@ int ddr3_init(void)
 #endif
 	}
 
-
 	status = ddr3_silicon_post_init();
 	if (MV_OK != status) {
 		printf("DDR3 Post Init - FAILED 0x%x\n", status);
@@ -89,7 +88,6 @@ int ddr3_init(void)
 		return status;
 	}
 
-
 	/* Post MC/PHY initializations */
 	mv_ddr_post_training_soc_config(ddr_type);
 
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
index 790b01d031d..5b8747cc681 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -285,7 +285,6 @@ int ddr3_tip_tune_training_params(u32 dev_num,
 	if (params->g_rtt_park != PARAM_UNDEFINED)
 		g_rtt_park = params->g_rtt_park;
 
-
 	DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
 			  ("DGL parameters: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n",
 			   g_zpri_data, g_znri_data, g_zpri_ctrl, g_znri_ctrl, g_zpodt_data, g_znodt_data,
@@ -870,7 +869,6 @@ int ddr3_tip_validate_algo_components(u8 dev_num)
 	return (status == 1) ? MV_OK : MV_NOT_INITIALIZED;
 }
 
-
 int ddr3_pre_algo_config(void)
 {
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
@@ -1114,7 +1112,6 @@ int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type interface_access,
 		mv_ddr_phy_write(phy_access, phy_id, phy_type, reg_addr, data_value, OPERATION_WRITE);
 }
 
-
 /*
  * Phy read-modify-write
  */
@@ -1406,7 +1403,6 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
 			t2t = (cs_num == 1) ? 0 : 1;
 		}
 
-
 		if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_INTERLEAVE_WA) == 1) {
 			/* Use 1T mode if 1:1 ratio configured */
 			if (config_func_info[dev_num].tip_get_clock_ratio(frequency) == 1) {
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
index 8765df7cfbb..bdd7836b844 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
@@ -82,7 +82,6 @@
 #define ADDR_SIZE_8GB			0x40000000
 #define ADDR_SIZE_16GB			0x80000000
 
-
 enum hws_edge_compare {
 	EDGE_PF,
 	EDGE_FP,
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
index 55abbad5a7a..bc58f55170c 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
@@ -1677,7 +1677,6 @@ static int mpr_rd_frmt_config(
 	u32 val, mask;
 	u8 cs_bitmask_inv;
 
-
 	if (dis_auto_refresh == 1) {
 		ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_CTRL_CTRL_REG,
 			  ODPG_CTRL_AUTO_REFRESH_DIS << ODPG_CTRL_AUTO_REFRESH_OFFS,
diff --git a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
index dff56338b19..e6b7cc5985e 100644
--- a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
+++ b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
@@ -79,7 +79,6 @@
 #define MV_DEBUG_WL_FULL
 #endif
 
-
 /* The following is a list of Marvell status */
 #define MV_ERROR	(-1)
 #define MV_OK		(0x00)	/* Operation succeeded                   */
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
index 8ec9fb0874e..fb69539ef4c 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
@@ -1144,7 +1144,6 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
 	uint64_t cs_mem_size = 0;
 	uint64_t mem_total_size_c, cs_mem_size_c;
 
-
 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
 	u32 physical_mem_size;
 	u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.h b/drivers/ddr/marvell/a38x/mv_ddr_plat.h
index 01894f652cb..23f3dd62877 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.h
@@ -55,7 +55,6 @@
 
 #define MARVELL_BOARD				MARVELL_BOARD_ID_BASE
 
-
 #define REG_DEVICE_SAR1_ADDR			0xe4204
 #define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET	17
 #define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK	0x1f
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_regs.h b/drivers/ddr/marvell/a38x/mv_ddr_regs.h
index a19000dbdd8..6a8a921e534 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_regs.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_regs.h
@@ -520,5 +520,4 @@ enum {
 #define RESULT_PHY_RX_OFFS			5
 #define RESULT_PHY_TX_OFFS			0
 
-
 #endif /* _MV_DDR_REGS_H */