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-rw-r--r--drivers/ddr/altera/sdram_soc64.h1
-rw-r--r--drivers/ddr/imx/phy/ddrphy_utils.c5
-rw-r--r--drivers/ddr/marvell/a38x/ddr_ml_wrapper.h1
-rw-r--r--drivers/ddr/marvell/axp/ddr3_axp.h2
4 files changed, 7 insertions, 2 deletions
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
index 07a0f9f2ae9..87a70a861ba 100644
--- a/drivers/ddr/altera/sdram_soc64.h
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -6,7 +6,6 @@
#ifndef _SDRAM_SOC64_H_
#define _SDRAM_SOC64_H_
-#include <common.h>
#include <linux/sizes.h>
struct altera_sdram_priv {
diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c
index fd8b4113b7b..45e1a70dbd4 100644
--- a/drivers/ddr/imx/phy/ddrphy_utils.c
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -111,11 +111,16 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
dram_pll_init(MHZ(1000));
dram_disable_bypass();
break;
+ case 3734:
case 3733:
case 3732:
dram_pll_init(MHZ(933));
dram_disable_bypass();
break;
+ case 3600:
+ dram_pll_init(MHZ(900));
+ dram_disable_bypass();
+ break;
case 3200:
dram_pll_init(MHZ(800));
dram_disable_bypass();
diff --git a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
index 73573119658..dff56338b19 100644
--- a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
+++ b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
@@ -6,7 +6,6 @@
#ifndef _DDR_ML_WRAPPER_H
#define _DDR_ML_WRAPPER_H
-#include <common.h>
#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h
index c40cd768abf..c3d282477f5 100644
--- a/drivers/ddr/marvell/axp/ddr3_axp.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp.h
@@ -6,6 +6,8 @@
#ifndef __DDR3_AXP_H
#define __DDR3_AXP_H
+#include <config.h>
+
#define MV_78XX0_Z1_REV 0x0
#define MV_78XX0_A0_REV 0x1
#define MV_78XX0_B0_REV 0x2