diff options
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/fsl/fsl_ddr_gen4.c | 27 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_init.c | 29 |
2 files changed, 33 insertions, 23 deletions
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 608810d4e29..5039f5de0a9 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -56,7 +56,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */ u32 *vref_seq = vref_seq1; #endif -#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 +#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) | \ + defined(CONFIG_SYS_FSL_ERRATUM_A010165) ulong ddr_freq; u32 tmp; #endif @@ -240,8 +241,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, /* Disable DRAM VRef training */ ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); - /* Disable deskew */ - ddr_out32(&ddr->debug[28], 0x400); + /* disable transmit bit deskew */ + temp32 = ddr_in32(&ddr->debug[28]); + temp32 |= DDR_TX_BD_DIS; + ddr_out32(&ddr->debug[28], temp32); /* Disable D_INIT */ ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); @@ -249,6 +252,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009801 + temp32 = ddr_in32(&ddr->debug[25]); + temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK; + temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT; + ddr_out32(&ddr->debug[25], temp32); +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; tmp = ddr_in32(&ddr->debug[28]); @@ -262,6 +272,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->debug[28], tmp | 0x0060007b); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A010165 + ddr_freq = get_ddr_freq(ctrl_num) / 1000000; + if ((ddr_freq > 1900) && (ddr_freq < 2300)) { + tmp = ddr_in32(&ddr->debug[28]); + ddr_out32(&ddr->debug[28], tmp | 0x000a0000); + } +#endif /* * For RDIMMs, JEDEC spec requires clocks to be stable before reset is * deasserted. Clocks start when any chip select is enabled and clock @@ -358,7 +375,9 @@ step2: debug("MR6 = 0x%08x\n", temp32); } ddr_out32(&ddr->sdram_md_cntl, 0); - ddr_out32(&ddr->debug[28], 0); /* Enable deskew */ + temp32 = ddr_in32(&ddr->debug[28]); + temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */ + ddr_out32(&ddr->debug[28], temp32); ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */ /* wait for idle */ timeout = 40; diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c index ee05f57f436..55baad498ae 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.c +++ b/drivers/ddr/marvell/a38x/ddr3_init.c @@ -678,7 +678,7 @@ u32 ddr3_get_device_width(u32 cs) return (device_width == 0) ? 8 : 16; } -float ddr3_get_device_size(u32 cs) +static int ddr3_get_device_size(u32 cs) { u32 device_size_low, device_size_high, device_size; u32 data, cs_low_offset, cs_high_offset; @@ -695,15 +695,15 @@ float ddr3_get_device_size(u32 cs) switch (device_size) { case 0: - return 2; + return 2048; case 2: - return 0.5; + return 512; case 3: - return 1; + return 1024; case 4: - return 4; + return 4096; case 5: - return 8; + return 8192; case 1: default: DEBUG_INIT_C("Error: Wrong device size of Cs: ", cs, 1); @@ -711,13 +711,13 @@ float ddr3_get_device_size(u32 cs) * Small value will give wrong emem size in * ddr3_calc_mem_cs_size */ - return 0.01; + return 0; } } int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size) { - float cs_mem_size; + int cs_mem_size; /* Calculate in GiB */ cs_mem_size = ((ddr3_get_bus_width() / ddr3_get_device_width(cs)) * @@ -731,21 +731,12 @@ int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size) */ cs_mem_size *= DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER; - if (cs_mem_size == 0.125) { - *cs_size = 128 << 20; - } else if (cs_mem_size == 0.25) { - *cs_size = 256 << 20; - } else if (cs_mem_size == 0.5) { - *cs_size = 512 << 20; - } else if (cs_mem_size == 1) { - *cs_size = 1 << 30; - } else if (cs_mem_size == 2) { - *cs_size = 2 << 30; - } else { + if (!cs_mem_size || (cs_mem_size == 64) || (cs_mem_size == 4096)) { DEBUG_INIT_C("Error: Wrong Memory size of Cs: ", cs, 1); return MV_BAD_VALUE; } + *cs_size = cs_mem_size << 20; return MV_OK; } |