diff options
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 13 | ||||
| -rw-r--r-- | drivers/ddr/imx/imx8m/ddr_init.c | 6 |
2 files changed, 9 insertions, 10 deletions
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index a9b085db8c2..952b296dd8f 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -370,6 +370,8 @@ step2: debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); #endif /* part 1 of the workaound */ + /* Always start in self-refresh, clear after MEM_EN */ + setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); /* * 500 painful micro-seconds must elapse between @@ -382,8 +384,6 @@ step2: #ifdef CONFIG_DEEP_SLEEP if (is_warm_boot()) { - /* enter self-refresh */ - setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); /* do board specific memory setup */ board_mem_sleep_setup(); temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI); @@ -395,6 +395,10 @@ step2: out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); asm volatile("sync;isync"); + /* Exit self-refresh after DDR conf as some ddr memories can fail. */ + clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); + asm volatile("sync;isync"); + total_gb_size_per_controller = 0; for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (!(regs->cs[i].config & 0x80000000)) @@ -544,9 +548,4 @@ step2: clrbits_be32(&ddr->sdram_cfg, 0x2); } #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ -#ifdef CONFIG_DEEP_SLEEP - if (is_warm_boot()) - /* exit self-refresh */ - clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); -#endif } diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c index d6e915c9b9c..21af66e4e7f 100644 --- a/drivers/ddr/imx/imx8m/ddr_init.c +++ b/drivers/ddr/imx/imx8m/ddr_init.c @@ -24,7 +24,7 @@ void ddr_init(struct dram_timing_info *dram_timing) { unsigned int tmp, initial_drate, target_freq; - printf("DDRINFO: start DRAM init\n"); + debug("DDRINFO: start DRAM init\n"); /* Step1: Follow the power up procedure */ if (is_imx8mq()) { @@ -109,7 +109,7 @@ void ddr_init(struct dram_timing_info *dram_timing) tmp = reg32_read(DDRPHY_CalBusy(0)); } while ((tmp & 0x1)); - printf("DDRINFO:ddrphy calibration done\n"); + debug("DDRINFO:ddrphy calibration done\n"); /* Step15: Set SWCTL.sw_done to 0 */ reg32_write(DDRC_SWCTL(0), 0x00000000); @@ -161,7 +161,7 @@ void ddr_init(struct dram_timing_info *dram_timing) /* enable port 0 */ reg32_write(DDRC_PCTRL_0(0), 0x00000001); - printf("DDRINFO: ddrmix config done\n"); + debug("DDRINFO: ddrmix config done\n"); /* save the dram timing config into memory */ dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); |