4 files changed, 35 insertions, 12 deletions
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index e43c6801546..89cb4d352ee 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014-2020 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -57,7 +58,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	struct ccsr_ddr __iomem *ddr;
 	u32 temp32;
 	u32 total_gb_size_per_controller;
-	int timeout;
+	int timeout = 0;
+	int ddr_freq_for_timeout = 0;
 	int mod_bnds = 0;
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
@@ -511,8 +513,14 @@ step2:
 	 */
 	bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 			>> SDRAM_CFG_DBW_SHIFT);
-	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
-		(get_ddr_freq(ctrl_num) >> 20)) << 2;
+	ddr_freq_for_timeout = (get_ddr_freq(ctrl_num) >> 20) << 2;
+	if (ddr_freq_for_timeout) {
+		timeout = ((total_gb_size_per_controller <<
+				       (6 - bus_width)) * 100 /
+				ddr_freq_for_timeout);
+	} else {
+		debug("Error in getting timeout.\n");
+	}
 	total_gb_size_per_controller >>= 4;	/* shift down to gb size */
 	debug("total %d GB\n", total_gb_size_per_controller);
 	debug("Need to wait up to %d * 10ms\n", timeout);
diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c
index d299d763db1..d738ae3a7c6 100644
--- a/drivers/ddr/fsl/lc_common_dimm_params.c
+++ b/drivers/ddr/fsl/lc_common_dimm_params.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright 2008-2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP Semiconductor
+ * Copyright 2017-2021 NXP Semiconductor
  */
 
 #include <common.h>
@@ -23,7 +23,7 @@ compute_cas_latency(const unsigned int ctrl_num,
 	unsigned int caslat_actual;
 	unsigned int retry = 16;
 	unsigned int tmp = ~0;
-	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
+	unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 #ifdef CONFIG_SYS_FSL_DDR3
 	const unsigned int taamax = 20000;
 #else
@@ -37,6 +37,12 @@ compute_cas_latency(const unsigned int ctrl_num,
 	}
 	common_caslat = tmp;
 
+	if (!mclk_ps) {
+		printf("DDR clock (MCLK cycle was 0 ps), So setting it to slowest DIMM(s) (tCKmin %u ps).\n",
+		       outpdimm->tckmin_x_ps);
+		mclk_ps = outpdimm->tckmin_x_ps;
+	}
+
 	/* validate if the memory clk is in the range of dimms */
 	if (mclk_ps < outpdimm->tckmin_x_ps) {
 		printf("DDR clock (MCLK cycle %u ps) is faster than "
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 8e147160b9f..f389e5ef952 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 /*
@@ -297,9 +298,13 @@ const char * step_to_string(unsigned int step) {
 
 	unsigned int s = __ilog2(step);
 
-	if ((1 << s) != step)
-		return step_string_tbl[7];
-
+	if (s <= 31) {
+		if ((1 << s) != step)
+			return step_string_tbl[7];
+	} else {
+		if ((1 << (s - 32)) != step)
+			return step_string_tbl[7];
+	}
 	if (s >= ARRAY_SIZE(step_string_tbl)) {
 		printf("Error for the step in %s\n", __func__);
 		s = 0;
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index ac4f8d2732d..43cb01804b7 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -75,10 +76,13 @@ unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
 
 	/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
 	unsigned long long rem, mclk_ps = ULL_2E12;
-
-	/* Now perform the big divide, the result fits in 32-bits */
-	rem = do_div(mclk_ps, data_rate);
-	result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
+	if (data_rate) {
+		/* Now perform the big divide, the result fits in 32-bits */
+		rem = do_div(mclk_ps, data_rate);
+		result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
+	} else {
+		result = 0;
+	}
 
 	return result;
 }