summaryrefslogtreecommitdiff
path: root/drivers/ddr
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/ddr')
-rw-r--r--drivers/ddr/fsl/Kconfig16
-rw-r--r--drivers/ddr/fsl/Makefile1
-rw-r--r--drivers/ddr/fsl/ctrl_regs.c20
-rw-r--r--drivers/ddr/fsl/mpc85xx_ddr_gen1.c3
-rw-r--r--drivers/ddr/fsl/mpc86xx_ddr.c84
5 files changed, 7 insertions, 117 deletions
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 8b480dfd690..8246f627982 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -2,8 +2,8 @@ config SYS_FSL_DDR
bool
help
Select Freescale General DDR driver, shared between most Freescale
- PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
- based Layerscape SoCs (such as ls2080a).
+ PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
+ Layerscape SoCs (such as ls2080a).
config SYS_FSL_MMDC
bool
@@ -41,13 +41,10 @@ config SYS_NUM_DDR_CTLRS
ARCH_T4240
default 2 if ARCH_B4860 || \
ARCH_BSC9132 || \
- ARCH_MPC8572 || \
- ARCH_MPC8641 || \
ARCH_P4080 || \
ARCH_P5040 || \
ARCH_LX2160A || \
- ARCH_LX2162A || \
- ARCH_T4160
+ ARCH_LX2162A
default 1
config SYS_FSL_DDR_VER
@@ -80,12 +77,6 @@ config SYS_FSL_DDRC_GEN2
help
Enable Freescale DDR2 controller.
-config SYS_FSL_DDRC_86XX_GEN2
- bool
- depends on MPC86xx
- help
- Enable Freescale DDR2 controller for MPC86xx SoCs.
-
config SYS_FSL_DDRC_GEN3
bool
depends on PPC
@@ -137,7 +128,6 @@ config SYS_FSL_DDR2
bool "Freescale DDR2 controller"
depends on SYS_FSL_HAS_DDR2
select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
- select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx
config SYS_FSL_DDR1
bool "Freescale DDR1 controller"
diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
index c675f44ab00..8081d0cd82f 100644
--- a/drivers/ddr/fsl/Makefile
+++ b/drivers/ddr/fsl/Makefile
@@ -28,7 +28,6 @@ obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
-obj-$(CONFIG_SYS_FSL_DDRC_86XX_GEN2) += mpc86xx_ddr.o
obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index c849ef3a4c7..b5122d1a1c3 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1863,25 +1863,13 @@ static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts)
{
- unsigned int clk_adjust; /* Clock adjust */
- unsigned int ss_en = 0; /* Source synchronous enable */
-
-#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
- /* Per FSL Application Note: AN2805 */
- ss_en = 1;
-#endif
- if (fsl_ddr_get_version(0) >= 0x40701) {
+ if (fsl_ddr_get_version(0) >= 0x40701)
/* clk_adjust in 5-bits on T-series and LS-series */
- clk_adjust = (popts->clk_adjust & 0x1F) << 22;
- } else {
+ ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0x1F) << 22;
+ else
/* clk_adjust in 4-bits on earlier MPC85xx and P-series */
- clk_adjust = (popts->clk_adjust & 0xF) << 23;
- }
+ ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0xF) << 23;
- ddr->ddr_sdram_clk_cntl = (0
- | ((ss_en & 0x1) << 31)
- | clk_adjust
- );
debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
}
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
index 572f3703d51..9c2ddeaf932 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
@@ -48,9 +48,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
-#if defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8541)
- out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-#endif
/*
* 200 painful micro-seconds must elapse between
diff --git a/drivers/ddr/fsl/mpc86xx_ddr.c b/drivers/ddr/fsl/mpc86xx_ddr.c
deleted file mode 100644
index 43ed1ba432d..00000000000
--- a/drivers/ddr/fsl/mpc86xx_ddr.c
+++ /dev/null
@@ -1,84 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <fsl_ddr_sdram.h>
-#include <linux/delay.h>
-
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
-#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
-#endif
-
-void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
- unsigned int ctrl_num, int step)
-{
- unsigned int i;
- struct ccsr_ddr __iomem *ddr;
-
- switch (ctrl_num) {
- case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
- break;
- case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
- break;
- default:
- printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
- return;
- }
-
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- if (i == 0) {
- out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
- out_be32(&ddr->cs0_config, regs->cs[i].config);
-
- } else if (i == 1) {
- out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
- out_be32(&ddr->cs1_config, regs->cs[i].config);
-
- } else if (i == 2) {
- out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
- out_be32(&ddr->cs2_config, regs->cs[i].config);
-
- } else if (i == 3) {
- out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
- out_be32(&ddr->cs3_config, regs->cs[i].config);
- }
- }
-
- out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
- out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
- out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
- out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
- out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
- out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
- out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
- out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
- out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
- out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
- out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
- out_be32(&ddr->init_addr, regs->ddr_init_addr);
- out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
-
- debug("before go\n");
-
- /*
- * 200 painful micro-seconds must elapse between
- * the DDR clock setup and the DDR config enable.
- */
- udelay(200);
- asm volatile("sync;isync");
-
- out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
-
- /*
- * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
- */
- while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
- udelay(10000); /* throttle polling rate */
- }
-}
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-23 13:26:53 +0000