diff options
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/altera/sequencer.c | 8 | ||||
| -rw-r--r-- | drivers/ddr/microchip/ddr2.c | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 6c6bd90e941..42e87b50d3e 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -3534,7 +3534,7 @@ static void debug_mem_calibrate(int pass) u32 debug_info; if (pass) { - printf("%s: CALIBRATION PASSED\n", __FILE__); + debug("%s: CALIBRATION PASSED\n", __FILE__); gbl->fom_in /= 2; gbl->fom_out /= 2; @@ -3553,7 +3553,7 @@ static void debug_mem_calibrate(int pass) writel(debug_info, &phy_mgr_cfg->cal_debug_info); writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status); } else { - printf("%s: CALIBRATION FAILED\n", __FILE__); + debug("%s: CALIBRATION FAILED\n", __FILE__); debug_info = gbl->error_stage; debug_info |= gbl->error_substage << 8; @@ -3570,7 +3570,7 @@ static void debug_mem_calibrate(int pass) writel(debug_info, &sdr_reg_file->failing_stage); } - printf("%s: Calibration complete\n", __FILE__); + debug("%s: Calibration complete\n", __FILE__); } /** @@ -3741,7 +3741,7 @@ int sdram_calibration_full(void) initialize_tracking(); - printf("%s: Preparing to start memory calibration\n", __FILE__); + debug("%s: Preparing to start memory calibration\n", __FILE__); debug("%s:%d\n", __func__, __LINE__); debug_cond(DLEVEL >= 1, diff --git a/drivers/ddr/microchip/ddr2.c b/drivers/ddr/microchip/ddr2.c index 6056418588c..a52427c3d61 100644 --- a/drivers/ddr/microchip/ddr2.c +++ b/drivers/ddr/microchip/ddr2.c @@ -57,8 +57,8 @@ static int ddr2_phy_calib_start(void) writel(SCL_START | SCL_EN, &ddr2_phy->scl_start); /* Wait for SCL for data byte to pass */ - return wait_for_bit(__func__, &ddr2_phy->scl_start, SCL_LUBPASS, - true, CONFIG_SYS_HZ, false); + return wait_for_bit_le32(&ddr2_phy->scl_start, SCL_LUBPASS, + true, CONFIG_SYS_HZ, false); } /* DDR2 Controller initialization */ @@ -256,8 +256,8 @@ void ddr2_ctrl_init(void) writel(INIT_START, &ctrl->memcon); /* wait for all host cmds to be transmitted */ - wait_for_bit(__func__, &ctrl->cmdissue, CMD_VALID, false, - CONFIG_SYS_HZ, false); + wait_for_bit_le32(&ctrl->cmdissue, CMD_VALID, false, + CONFIG_SYS_HZ, false); /* inform all cmds issued, ready for normal operation */ writel(INIT_START | INIT_DONE, &ctrl->memcon); |