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-rw-r--r--drivers/fpga/Kconfig2
-rw-r--r--drivers/fpga/zynqmppl.c12
2 files changed, 10 insertions, 4 deletions
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 61490d6d8de..62cb77b098c 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -75,7 +75,7 @@ config FPGA_XILINX
config FPGA_ZYNQMPPL
bool "Enable Xilinx FPGA driver for ZynqMP"
- depends on FPGA_XILINX
+ depends on FPGA_XILINX && ZYNQMP_FIRMWARE
help
Enable FPGA driver for loading bitstream in BIT and BIN format
on Xilinx Zynq UltraScale+ (ZynqMP) device.
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index d1491da02c3..7b5128fe27a 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -332,10 +332,16 @@ static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
buf_lo = lower_32_bits((ulong)buf);
buf_hi = upper_32_bits((ulong)buf);
- ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
+ if ((u32)(uintptr_t)fpga_sec_info->userkey_addr)
+ ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
buf_hi,
- (u32)(uintptr_t)fpga_sec_info->userkey_addr,
- flag, ret_payload);
+ (u32)(uintptr_t)fpga_sec_info->userkey_addr,
+ flag, ret_payload);
+ else
+ ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
+ buf_hi, (u32)bsize,
+ flag, ret_payload);
+
if (ret)
puts("PL FPGA LOAD fail\n");
else