2 files changed, 24 insertions, 35 deletions
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index a1a0602ab27..4fcdf40fd0e 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -5,40 +5,18 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)libfpga.o
-
 ifdef CONFIG_FPGA
-COBJS-y += fpga.o
-COBJS-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
-COBJS-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
-COBJS-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
-COBJS-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
-COBJS-$(CONFIG_FPGA_XILINX) += xilinx.o
-COBJS-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
+obj-y += fpga.o
+obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
+obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
+obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
+obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
+obj-$(CONFIG_FPGA_XILINX) += xilinx.o
+obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
 ifdef CONFIG_FPGA_ALTERA
-COBJS-y += altera.o
-COBJS-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
-COBJS-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
-COBJS-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
+obj-y += altera.o
+obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
+obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
+obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
 endif
 endif
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(LIB)
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 717c0394ca4..1effbadda90 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -10,6 +10,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <zynqpl.h>
+#include <asm/sizes.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 
@@ -177,8 +178,14 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		return FPGA_FAIL;
 	}
 
-	if ((u32)buf_start & 0x3) {
-		u32 *new_buf = (u32 *)((u32)buf & ~0x3);
+	if ((u32)buf < SZ_1M) {
+		printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
+		       __func__, (u32)buf);
+		return FPGA_FAIL;
+	}
+
+	if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
+		u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
 
 		printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
 		       (u32)buf_start, (u32)new_buf, swap);
@@ -284,6 +291,10 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
 	debug("%s: Size = %zu\n", __func__, bsize);
 
+	/* flush(clean & invalidate) d-cache range buf */
+	flush_dcache_range((u32)buf, (u32)buf +
+			   roundup(bsize, ARCH_DMA_MINALIGN));
+
 	/* Set up the transfer */
 	writel((u32)buf | 1, &devcfg_base->dma_src_addr);
 	writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);