diff options
Diffstat (limited to 'drivers/fpga')
| -rw-r--r-- | drivers/fpga/fpga.c | 21 | ||||
| -rw-r--r-- | drivers/fpga/zynqmppl.c | 28 | ||||
| -rw-r--r-- | drivers/fpga/zynqpl.c | 16 |
3 files changed, 48 insertions, 17 deletions
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 6aead27f162..ac01612d751 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -148,20 +148,21 @@ int fpga_add(fpga_type devtype, void *desc) { int devnum = FPGA_INVALID_DEVICE; + if (!desc) { + printf("%s: NULL device descriptor\n", __func__); + return devnum; + } + if (next_desc < 0) { printf("%s: FPGA support not initialized!\n", __func__); } else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) { - if (desc) { - if (next_desc < CONFIG_MAX_FPGA_DEVICES) { - devnum = next_desc; - desc_table[next_desc].devtype = devtype; - desc_table[next_desc++].devdesc = desc; - } else { - printf("%s: Exceeded Max FPGA device count\n", - __func__); - } + if (next_desc < CONFIG_MAX_FPGA_DEVICES) { + devnum = next_desc; + desc_table[next_desc].devtype = devtype; + desc_table[next_desc++].devdesc = desc; } else { - printf("%s: NULL device descriptor\n", __func__); + printf("%s: Exceeded Max FPGA device count\n", + __func__); } } else { printf("%s: Unsupported FPGA type %d\n", __func__, devtype); diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 57a4e6c88e7..43e8b2520e3 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -11,6 +11,7 @@ #include <zynqmppl.h> #include <linux/sizes.h> #include <asm/arch/sys_proto.h> +#include <memalign.h> #define DUMMY_WORD 0xffffffff @@ -195,6 +196,7 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf, static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, bitstream_type bstype) { + ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1); u32 swap; ulong bin_buf; int ret; @@ -205,25 +207,37 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, return FPGA_FAIL; bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap); + bsizeptr = (u32 *)&bsize; debug("%s called!\n", __func__); flush_dcache_range(bin_buf, bin_buf + bsize); - - if (bsize % 4) - bsize = bsize / 4 + 1; - else - bsize = bsize / 4; + flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t)); buf_lo = (u32)bin_buf; buf_hi = upper_32_bits(bin_buf); - ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize, - bstype, ret_payload); + bstype |= BIT(ZYNQMP_FPGA_BIT_NS); + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, + (u32)(uintptr_t)bsizeptr, bstype, ret_payload); if (ret) debug("PL FPGA LOAD fail\n"); return ret; } +static int zynqmp_pcap_info(xilinx_desc *desc) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0, + 0, ret_payload); + if (!ret) + printf("PCAP status\t0x%x\n", ret_payload[1]); + + return ret; +} + struct xilinx_fpga_op zynqmp_op = { .load = zynqmp_load, + .info = zynqmp_pcap_info, }; diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 2ff716c2522..db9bd12992f 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -17,6 +17,7 @@ #include <asm/arch/sys_proto.h> #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000 +#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000 @@ -205,9 +206,24 @@ static int zynq_dma_xfer_init(bitstream_type bstype) /* Setting PCFG_PROG_B signal to high */ control = readl(&devcfg_base->ctrl); writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); + + /* + * Delay is required if AES efuse is selected as + * key source. + */ + if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK) + mdelay(5); + /* Setting PCFG_PROG_B signal to low */ writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); + /* + * Delay is required if AES efuse is selected as + * key source. + */ + if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK) + mdelay(5); + /* Polling the PCAP_INIT status for Reset */ ts = get_timer(0); while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { |