diff options
Diffstat (limited to 'drivers/gpio')
| -rw-r--r-- | drivers/gpio/Kconfig | 13 | ||||
| -rw-r--r-- | drivers/gpio/Makefile | 19 | ||||
| -rw-r--r-- | drivers/gpio/dwapb_gpio.c | 4 | ||||
| -rw-r--r-- | drivers/gpio/gpio-aspeed-sgpio.c | 310 | ||||
| -rw-r--r-- | drivers/gpio/gpio-uclass.c | 4 | ||||
| -rw-r--r-- | drivers/gpio/mcp230xx_gpio.c | 1 | ||||
| -rw-r--r-- | drivers/gpio/msm_gpio.c | 97 | ||||
| -rw-r--r-- | drivers/gpio/pca953x.c | 2 | ||||
| -rw-r--r-- | drivers/gpio/qcom_pmic_gpio.c | 27 | ||||
| -rw-r--r-- | drivers/gpio/rk_gpio.c | 4 | ||||
| -rw-r--r-- | drivers/gpio/s5p_gpio.c | 10 | ||||
| -rw-r--r-- | drivers/gpio/sunxi_gpio.c | 2 | ||||
| -rw-r--r-- | drivers/gpio/tca642x.c | 2 | ||||
| -rw-r--r-- | drivers/gpio/tegra_gpio.c | 52 |
14 files changed, 494 insertions, 53 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 3996333fe8d..92a8597420a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -157,6 +157,13 @@ config ASPEED_GPIO is found in the AST2400, AST2500 and AST2600 BMC SoCs and provides access to over 200 GPIOs on each chip. +config ASPEED_SGPIO + bool "Aspeed SGPIO Driver" + help + Say yes here to support the Aspeed serial GPIO driver. The controller + is found in the AST2400, AST2500 and AST2600 BMC SoCs and + provides access to generate serial GPIO signal. + config ASPEED_G7_GPIO bool "Aspeed G7 GPIO Driver" help @@ -700,4 +707,10 @@ config RZG2L_GPIO Support the gpio functionality of the pin function controller (PFC) on the Renesas RZ/G2L SoC family. +config SPL_ADP5585_GPIO + bool "ADP5585 GPIO driver in SPL" + depends on SPL_DM_GPIO && SPL_I2C + help + Support ADP5585 GPIO expander in SPL. + endif diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index da0faf05246..3f882c065d8 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -3,17 +3,18 @@ # Copyright 2000-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o obj-$(CONFIG_AXP_GPIO) += axp_gpio.o obj-$(CONFIG_DM_74X164) += 74x164_gpio.o endif -obj-$(CONFIG_$(SPL_TPL_)DM_GPIO) += gpio-uclass.o +obj-$(CONFIG_$(PHASE_)DM_GPIO) += gpio-uclass.o -obj-$(CONFIG_$(SPL_)DM_PCA953X) += pca953x_gpio.o +obj-$(CONFIG_$(XPL_)DM_PCA953X) += pca953x_gpio.o obj-$(CONFIG_ASPEED_GPIO) += gpio-aspeed.o obj-$(CONFIG_ASPEED_G7_GPIO) += gpio-aspeed-g7.o +obj-$(CONFIG_ASPEED_SGPIO) += gpio-aspeed-sgpio.o obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_BCM6345_GPIO) += bcm6345_gpio.o @@ -24,7 +25,7 @@ obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o obj-$(CONFIG_IPROC_GPIO) += iproc_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o -obj-$(CONFIG_$(SPL_TPL_)MCP230XX_GPIO) += mcp230xx_gpio.o +obj-$(CONFIG_$(PHASE_)MCP230XX_GPIO) += mcp230xx_gpio.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o obj-$(CONFIG_NPCM_GPIO) += npcm_gpio.o @@ -57,13 +58,13 @@ obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o -obj-$(CONFIG_$(SPL_)PALMAS_GPIO) += palmas_gpio.o +obj-$(CONFIG_$(XPL_)PALMAS_GPIO) += palmas_gpio.o obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o obj-$(CONFIG_OCTEON_GPIO) += octeon_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o obj-$(CONFIG_MSM_GPIO) += msm_gpio.o -obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o -obj-$(CONFIG_$(SPL_TPL_)QCOM_PMIC_GPIO) += qcom_pmic_gpio.o +obj-$(CONFIG_$(XPL_)PCF8575_GPIO) += pcf8575_gpio.o +obj-$(CONFIG_$(PHASE_)QCOM_PMIC_GPIO) += qcom_pmic_gpio.o obj-$(CONFIG_MT7620_GPIO) += mt7620_gpio.o obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o @@ -71,10 +72,10 @@ obj-$(CONFIG_NX_GPIO) += nx_gpio.o obj-$(CONFIG_SIFIVE_GPIO) += sifive-gpio.o obj-$(CONFIG_NOMADIK_GPIO) += nmk_gpio.o obj-$(CONFIG_MAX7320_GPIO) += max7320_gpio.o -obj-$(CONFIG_$(SPL_)MAX77663_GPIO) += max77663_gpio.o +obj-$(CONFIG_$(XPL_)MAX77663_GPIO) += max77663_gpio.o obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o obj-$(CONFIG_FTGPIO010) += ftgpio010.o -obj-$(CONFIG_ADP5585_GPIO) += adp5585_gpio.o +obj-$(CONFIG_$(SPL_)ADP5585_GPIO) += adp5585_gpio.o obj-$(CONFIG_RZG2L_GPIO) += rzg2l-gpio.o diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c index 7a6eae9ba18..04639a4cb68 100644 --- a/drivers/gpio/dwapb_gpio.c +++ b/drivers/gpio/dwapb_gpio.c @@ -177,7 +177,9 @@ static int gpio_dwapb_bind(struct udevice *dev) plat->base = (void *)base; plat->bank = bank; - plat->pins = ofnode_read_u32_default(node, "snps,nr-gpios", 0); + + if (ofnode_read_u32(node, "ngpios", &plat->pins)) + plat->pins = ofnode_read_u32_default(node, "snps,nr-gpios", 0); if (ofnode_read_string_index(node, "bank-name", 0, &plat->name)) { diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c new file mode 100644 index 00000000000..4bbdec756f3 --- /dev/null +++ b/drivers/gpio/gpio-aspeed-sgpio.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + * Billy Tsai <billy_tsai@aspeedtech.com> + */ +#include <asm/io.h> +#include <asm/gpio.h> + +#include <config.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/sizes.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> + +#define ASPEED_SGPIO_CTRL 0x54 + +#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16) +#define ASPEED_SGPIO_ENABLE BIT(0) +#define ASPEED_SGPIO_PINS_SHIFT 6 + +struct aspeed_sgpio_priv { + void *base; + struct clk pclk; + const struct aspeed_sgpio_pdata *pdata; +}; + +struct aspeed_sgpio_pdata { + const u32 pin_mask; + const struct aspeed_sgpio_llops *llops; +}; + +struct aspeed_sgpio_bank { + u16 val_regs; + u16 rdata_reg; + u16 tolerance_regs; + const char names[4][3]; +}; + +/* + * Note: The "value" register returns the input value when the GPIO is + * configured as an input. + * + * The "rdata" register returns the output value when the GPIO is + * configured as an output. + */ +static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = { + { + .val_regs = 0x0000, + .rdata_reg = 0x0070, + .tolerance_regs = 0x0018, + .names = { "A", "B", "C", "D" }, + }, + { + .val_regs = 0x001C, + .rdata_reg = 0x0074, + .tolerance_regs = 0x0034, + .names = { "E", "F", "G", "H" }, + }, + { + .val_regs = 0x0038, + .rdata_reg = 0x0078, + .tolerance_regs = 0x0050, + .names = { "I", "J", "K", "L" }, + }, + { + .val_regs = 0x0090, + .rdata_reg = 0x007C, + .tolerance_regs = 0x00A8, + .names = { "M", "N", "O", "P" }, + }, +}; + +enum aspeed_sgpio_reg { + reg_val, + reg_rdata, + reg_tolerance, +}; + +struct aspeed_sgpio_llops { + void (*reg_bit_set)(struct aspeed_sgpio_priv *gpio, unsigned int offset, + const enum aspeed_sgpio_reg reg, bool val); + bool (*reg_bit_get)(struct aspeed_sgpio_priv *gpio, unsigned int offset, + const enum aspeed_sgpio_reg reg); +}; + +#define GPIO_VAL_VALUE 0x00 + +static void __iomem *bank_reg(struct aspeed_sgpio_priv *gpio, + const struct aspeed_sgpio_bank *bank, + const enum aspeed_sgpio_reg reg) +{ + switch (reg) { + case reg_val: + return gpio->base + bank->val_regs + GPIO_VAL_VALUE; + case reg_rdata: + return gpio->base + bank->rdata_reg; + case reg_tolerance: + return gpio->base + bank->tolerance_regs; + default: + /* acturally if code runs to here, it's an error case */ + BUG(); + } +} + +#define GPIO_BANK(x) ((x) >> 6) +#define GPIO_OFFSET(x) ((x) & GENMASK(5, 0)) +#define GPIO_BIT(x) BIT(GPIO_OFFSET(x) >> 1) + +static const struct aspeed_sgpio_bank *to_bank(unsigned int offset) +{ + unsigned int bank; + + bank = GPIO_BANK(offset); + + WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks)); + return &aspeed_sgpio_banks[bank]; +} + +static bool aspeed_sgpio_is_input(unsigned int offset) +{ + return !(offset % 2); +} + +static int aspeed_sgpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct aspeed_sgpio_priv *gpio = dev_get_priv(dev); + enum aspeed_sgpio_reg reg; + + reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata; + + return gpio->pdata->llops->reg_bit_get(gpio, offset, reg); +} + +static int aspeed_sgpio_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + struct aspeed_sgpio_priv *gpio = dev_get_priv(dev); + + if (aspeed_sgpio_is_input(offset)) + return -EINVAL; + + gpio->pdata->llops->reg_bit_set(gpio, offset, reg_val, value); + + return 0; +} + +static int aspeed_sgpio_direction_input(struct udevice *dev, + unsigned int offset) +{ + return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL; +} + +static int aspeed_sgpio_set_flags(struct udevice *dev, unsigned int offset, ulong flags) +{ + int ret = -EOPNOTSUPP; + + if (flags & GPIOD_IS_OUT) { + bool value = flags & GPIOD_IS_OUT_ACTIVE; + + ret = aspeed_sgpio_set_value(dev, offset, value); + } else if (flags & GPIOD_IS_IN) { + ret = aspeed_sgpio_direction_input(dev, offset); + } + return ret; +} + +static int aspeed_sgpio_get_function(struct udevice *dev, unsigned int offset) +{ + return aspeed_sgpio_is_input(offset) ? GPIOF_INPUT : GPIOF_OUTPUT; +} + +static void aspeed_g4_reg_bit_set(struct aspeed_sgpio_priv *gpio, unsigned int offset, + const enum aspeed_sgpio_reg reg, bool val) +{ + const struct aspeed_sgpio_bank *bank = to_bank(offset); + void __iomem *addr = bank_reg(gpio, bank, reg); + u32 temp; + + if (reg == reg_val) + /* Since this is an output, read the cached value from rdata, then update val. */ + temp = readl(bank_reg(gpio, bank, reg_rdata)); + else + temp = readl(addr); + + if (val) + temp |= GPIO_BIT(offset); + else + temp &= ~GPIO_BIT(offset); + + writel(temp, addr); +} + +static bool aspeed_g4_reg_bit_get(struct aspeed_sgpio_priv *gpio, unsigned int offset, + const enum aspeed_sgpio_reg reg) +{ + const struct aspeed_sgpio_bank *bank = to_bank(offset); + void __iomem *addr = bank_reg(gpio, bank, reg); + + return !!(readl(addr) & GPIO_BIT(offset)); +} + +static const struct aspeed_sgpio_llops aspeed_g4_llops = { + .reg_bit_set = aspeed_g4_reg_bit_set, + .reg_bit_get = aspeed_g4_reg_bit_get, +}; + +static const struct dm_gpio_ops aspeed_sgpio_ops = { + .get_value = aspeed_sgpio_get_value, + .set_value = aspeed_sgpio_set_value, + .get_function = aspeed_sgpio_get_function, + .set_flags = aspeed_sgpio_set_flags, +}; + +static int aspeed_sgpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct aspeed_sgpio_priv *priv = dev_get_priv(dev); + u32 sgpio_freq, sgpio_clk_div, nr_gpios, gpio_cnt_regval, pin_mask; + ulong apb_freq; + int ret; + + priv->base = devfdt_get_addr_ptr(dev); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->pdata = (const struct aspeed_sgpio_pdata *)dev_get_driver_data(dev); + if (!priv->pdata) + return -EINVAL; + + pin_mask = priv->pdata->pin_mask; + + ret = ofnode_read_u32(dev_ofnode(dev), "ngpios", &nr_gpios); + if (ret < 0) { + dev_err(dev, "Could not read ngpios property\n"); + return -EINVAL; + } else if (nr_gpios % 8) { + dev_err(dev, "Number of GPIOs not multiple of 8: %d\n", + nr_gpios); + return -EINVAL; + } + + ret = ofnode_read_u32(dev_ofnode(dev), "bus-frequency", &sgpio_freq); + if (ret < 0) { + dev_err(dev, "Could not read bus-frequency property\n"); + return -EINVAL; + } + + ret = clk_get_by_index(dev, 0, &priv->pclk); + if (ret < 0) { + dev_err(dev, "get clock failed\n"); + return ret; + } + + apb_freq = clk_get_rate(&priv->pclk); + + /* + * From the datasheet, + * SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1) + * period = 2 * (GPIO254[31:16] + 1) / PCLK + * frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK) + * frequency = PCLK / (2 * (GPIO254[31:16] + 1)) + * frequency * 2 * (GPIO254[31:16] + 1) = PCLK + * GPIO254[31:16] = PCLK / (frequency * 2) - 1 + */ + if (sgpio_freq == 0) + return -EINVAL; + + sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1; + + if (sgpio_clk_div > (1 << 16) - 1) + return -EINVAL; + + gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask; + writel(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval | + ASPEED_SGPIO_ENABLE, priv->base + ASPEED_SGPIO_CTRL); + + uc_priv->bank_name = dev->name; + uc_priv->gpio_count = nr_gpios * 2; + + return 0; +} + +static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = { + .pin_mask = GENMASK(9, 6), + .llops = &aspeed_g4_llops, +}; + +static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = { + .pin_mask = GENMASK(10, 6), + .llops = &aspeed_g4_llops, +}; + +static const struct udevice_id aspeed_sgpio_ids[] = { + { .compatible = "aspeed,ast2400-sgpio", .data = (ulong)&ast2400_sgpio_pdata, }, + { .compatible = "aspeed,ast2500-sgpio", .data = (ulong)&ast2400_sgpio_pdata, }, + { .compatible = "aspeed,ast2600-sgpiom", .data = (ulong)&ast2600_sgpiom_pdata, }, +}; + +U_BOOT_DRIVER(sgpio_aspeed) = { + .name = "sgpio-aspeed", + .id = UCLASS_GPIO, + .of_match = aspeed_sgpio_ids, + .ops = &aspeed_sgpio_ops, + .probe = aspeed_sgpio_probe, + .priv_auto = sizeof(struct aspeed_sgpio_priv), +}; diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 92ce68dd4a1..0213271e3a6 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -412,7 +412,7 @@ int dm_gpio_request(struct gpio_desc *desc, const char *label) static int dm_gpio_requestf(struct gpio_desc *desc, const char *fmt, ...) { -#if !defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF) +#if !defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF) va_list args; char buf[40]; @@ -461,7 +461,7 @@ int gpio_request(unsigned gpio, const char *label) */ int gpio_requestf(unsigned gpio, const char *fmt, ...) { -#if !defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF) +#if !defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF) va_list args; char buf[40]; diff --git a/drivers/gpio/mcp230xx_gpio.c b/drivers/gpio/mcp230xx_gpio.c index 42e7fe9d474..b6f533b1306 100644 --- a/drivers/gpio/mcp230xx_gpio.c +++ b/drivers/gpio/mcp230xx_gpio.c @@ -14,6 +14,7 @@ #include <asm/gpio.h> #include <dm/device_compat.h> #include <dt-bindings/gpio/gpio.h> +#include <linux/delay.h> enum mcp230xx_type { UNKNOWN = 0, diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 2fb266f1285..cea073b3297 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -34,13 +34,31 @@ struct msm_gpio_bank { #define GPIO_IN_OUT_REG(dev, x) \ (GPIO_CONFIG_REG(dev, x) + 0x4) +static void msm_gpio_direction_input_special(struct msm_gpio_bank *priv, + unsigned int gpio) +{ + unsigned int offset = gpio - priv->pin_data->special_pins_start; + const struct msm_special_pin_data *data; + + if (!priv->pin_data->special_pins_data) + return; + + data = &priv->pin_data->special_pins_data[offset]; + + if (!data->ctl_reg || data->oe_bit >= 31) + return; + + /* switch direction */ + clrsetbits_le32(priv->base + data->ctl_reg, + BIT(data->oe_bit), 0); +} + static void msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); - /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(priv->pin_data, gpio)) - return; + msm_gpio_direction_input_special(priv, gpio); /* Disable OE bit */ clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio), @@ -49,13 +67,33 @@ static void msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) return; } +static int msm_gpio_set_value_special(struct msm_gpio_bank *priv, + unsigned int gpio, int value) +{ + unsigned int offset = gpio - priv->pin_data->special_pins_start; + const struct msm_special_pin_data *data; + + if (!priv->pin_data->special_pins_data) + return 0; + + data = &priv->pin_data->special_pins_data[offset]; + + if (!data->io_reg || data->out_bit >= 31) + return 0; + + value = !!value; + /* set value */ + writel(value << data->out_bit, priv->base + data->io_reg); + + return 0; +} + static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) { struct msm_gpio_bank *priv = dev_get_priv(dev); - /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(priv->pin_data, gpio)) - return 0; + return msm_gpio_set_value_special(priv, gpio, value); value = !!value; /* set value */ @@ -64,14 +102,42 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) return 0; } +static int msm_gpio_direction_output_special(struct msm_gpio_bank *priv, + unsigned int gpio, + int value) +{ + unsigned int offset = gpio - priv->pin_data->special_pins_start; + const struct msm_special_pin_data *data; + + if (!priv->pin_data->special_pins_data) + return 0; + + data = &priv->pin_data->special_pins_data[offset]; + + if (!data->io_reg || data->out_bit >= 31) + return 0; + + value = !!value; + /* set value */ + writel(value << data->out_bit, priv->base + data->io_reg); + + if (!data->ctl_reg || data->oe_bit >= 31) + return 0; + + /* switch direction */ + clrsetbits_le32(priv->base + data->ctl_reg, + BIT(data->oe_bit), BIT(data->oe_bit)); + + return 0; +} + static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio, int value) { struct msm_gpio_bank *priv = dev_get_priv(dev); - /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(priv->pin_data, gpio)) - return 0; + return msm_gpio_direction_output_special(priv, gpio, value); value = !!value; /* set value */ @@ -100,13 +166,28 @@ static int msm_gpio_set_flags(struct udevice *dev, unsigned int gpio, ulong flag return 0; } +static int msm_gpio_get_value_special(struct msm_gpio_bank *priv, unsigned int gpio) +{ + unsigned int offset = gpio - priv->pin_data->special_pins_start; + const struct msm_special_pin_data *data; + + if (!priv->pin_data->special_pins_data) + return 0; + + data = &priv->pin_data->special_pins_data[offset]; + + if (!data->io_reg || data->in_bit >= 31) + return 0; + + return !!(readl(priv->base + data->io_reg) >> data->in_bit); +} + static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev); - /* Always NOP for special pins, assume they're in the correct state */ if (qcom_is_special_pin(priv->pin_data, gpio)) - return 0; + return msm_gpio_get_value_special(priv, gpio); return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN); } diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index fc4dcf9f986..2fb14590c0f 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -143,7 +143,7 @@ int pca953x_get_val(uint8_t chip) return (int)val; } -#if defined(CONFIG_CMD_PCA953X) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_CMD_PCA953X) && !defined(CONFIG_XPL_BUILD) /* * Display pca953x information */ diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 80fee841ee3..f2ef4e5ce14 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -69,17 +69,6 @@ #define REG_EN_CTL 0x46 #define REG_EN_CTL_ENABLE (1 << 7) -/** - * pmic_gpio_match_data - platform specific configuration - * - * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them. - * This is a workaround for an unknown bug on some platforms where trying to write the - * GPIO configuration registers causes the board to hang. - */ -enum pmic_gpio_quirks { - QCOM_PMIC_QUIRK_READONLY = (1 << 0), -}; - struct qcom_pmic_gpio_data { uint32_t pid; /* Peripheral ID on SPMI bus */ bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */ @@ -128,13 +117,8 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset, { struct qcom_pmic_gpio_data *plat = dev_get_plat(dev); uint32_t gpio_base = plat->pid + REG_OFFSET(offset); - ulong quirks = dev_get_driver_data(dev); int ret = 0; - /* Some PMICs don't like their GPIOs being configured */ - if (quirks & QCOM_PMIC_QUIRK_READONLY) - return 0; - /* Disable the GPIO */ ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, REG_EN_CTL_ENABLE, 0); @@ -278,7 +262,6 @@ static int qcom_gpio_bind(struct udevice *dev) { struct qcom_pmic_gpio_data *plat = dev_get_plat(dev); - ulong quirks = dev_get_driver_data(dev); struct udevice *child; struct driver *drv; int ret; @@ -292,7 +275,7 @@ static int qcom_gpio_bind(struct udevice *dev) /* Bind the GPIO driver as a child of the PMIC. */ ret = device_bind_with_driver_data(dev, drv, dev->name, - quirks, dev_ofnode(dev), &child); + 0, dev_ofnode(dev), &child); if (ret) return log_msg_ret("bind", ret); @@ -361,11 +344,11 @@ static int qcom_gpio_probe(struct udevice *dev) static const struct udevice_id qcom_gpio_ids[] = { { .compatible = "qcom,pm8916-gpio" }, { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ - { .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, + { .compatible = "qcom,pm8998-gpio" }, { .compatible = "qcom,pms405-gpio" }, - { .compatible = "qcom,pm6125-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, - { .compatible = "qcom,pm8150-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, - { .compatible = "qcom,pm8550-gpio", .data = QCOM_PMIC_QUIRK_READONLY }, + { .compatible = "qcom,pm6125-gpio" }, + { .compatible = "qcom,pm8150-gpio" }, + { .compatible = "qcom,pm8550-gpio" }, { } }; diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index 24ba12dd820..57c49c75939 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -126,7 +126,7 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) } /* Simple SPL interface to GPIOs */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD enum { PULL_NONE_1V8 = 0, @@ -169,7 +169,7 @@ int spl_gpio_output(void *vregs, uint gpio, int value) return 0; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ static int rockchip_gpio_probe(struct udevice *dev) { diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 83e65aa4aec..53dbbe97b5a 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -92,7 +92,7 @@ static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) writel(value, &bank->dat); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* Common GPIO API - SPL does not support driver model yet */ int gpio_set_value(unsigned gpio, int value) { @@ -118,7 +118,7 @@ static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio) value = readl(&bank->dat); return !!(value & DAT_MASK(gpio)); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) { @@ -185,7 +185,7 @@ int s5p_gpio_get_pin(unsigned gpio) } /* Driver model interface */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* set GPIO pin 'gpio' as an input */ static int exynos_gpio_direction_input(struct udevice *dev, unsigned offset) { @@ -230,7 +230,7 @@ static int exynos_gpio_set_value(struct udevice *dev, unsigned offset, return 0; } -#endif /* nCONFIG_SPL_BUILD */ +#endif /* nCONFIG_XPL_BUILD */ /* * There is no common GPIO API for pull, drv, pin, rate (yet). These @@ -260,7 +260,7 @@ void gpio_set_rate(int gpio, int mode) s5p_gpio_get_pin(gpio), mode); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int exynos_gpio_get_function(struct udevice *dev, unsigned offset) { struct exynos_bank_info *state = dev_get_priv(dev); diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index 218ca2af397..2ca4960f17a 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -245,7 +245,7 @@ int sunxi_name_to_gpio(const char *name) { unsigned int gpio; int ret; -#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO +#if !defined CONFIG_XPL_BUILD && defined CONFIG_AXP_GPIO char lookup[8]; if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) { diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c index 1d45b500746..8307a07e14e 100644 --- a/drivers/gpio/tca642x.c +++ b/drivers/gpio/tca642x.c @@ -164,7 +164,7 @@ int tca642x_set_inital_state(uchar chip, struct tca642x_bank_info init_data[]) return ret; } -#if defined(CONFIG_CMD_TCA642X) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_CMD_TCA642X) && !defined(CONFIG_XPL_BUILD) /* * Display tca642x information */ diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 0c40d36c41e..b83df351e74 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -257,6 +257,56 @@ static const struct dm_gpio_ops gpio_tegra_ops = { .xlate = tegra_gpio_xlate, }; +/* + * SPL GPIO functions. + */ +int spl_gpio_output(void *regs, uint gpio, int value) +{ + /* Configure GPIO output value. */ + set_level(gpio, value); + + /* Configure GPIO direction as output. */ + set_direction(gpio, DIRECTION_OUTPUT); + + /* Enable the pin as a GPIO */ + set_config(gpio, 1); + + return 0; +} + +int spl_gpio_input(void *regs, uint gpio) +{ + /* Configure GPIO direction as input. */ + set_direction(gpio, DIRECTION_INPUT); + + /* Enable the pin as a GPIO */ + set_config(gpio, 1); + + return 0; +} + +int spl_gpio_get_value(void *regs, uint gpio) +{ + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; + int val; + + if (get_direction(gpio) == DIRECTION_INPUT) + val = readl(&bank->gpio_in[GPIO_PORT(gpio)]); + else + val = readl(&bank->gpio_out[GPIO_PORT(gpio)]); + + return (val >> GPIO_BIT(gpio)) & 1; +} + +int spl_gpio_set_value(void *regs, uint gpio, int value) +{ + /* Configure GPIO output value. */ + set_level(gpio, value); + + return 0; +} + /** * Returns the name of a GPIO port * @@ -323,7 +373,7 @@ static int gpio_tegra_bind(struct udevice *parent) return 0; /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; bank_count = TEGRA_GPIO_BANKS; #else |