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-rw-r--r--drivers/misc/Kconfig18
-rw-r--r--drivers/misc/Makefile7
-rw-r--r--drivers/misc/cbmem_console.c2
-rw-r--r--drivers/misc/cros_ec.c17
-rw-r--r--drivers/misc/cros_ec_sandbox.c4
-rw-r--r--drivers/misc/irq-uclass.c2
-rw-r--r--drivers/misc/mxc_ocotp.c2
-rw-r--r--drivers/misc/p2sb_emul.c1
-rw-r--r--drivers/misc/qfw.c243
-rw-r--r--drivers/misc/qfw_mmio.c119
-rw-r--r--drivers/misc/qfw_pio.c69
-rw-r--r--drivers/misc/qfw_sandbox.c127
-rw-r--r--drivers/misc/test_drv.c11
13 files changed, 454 insertions, 168 deletions
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 7d2a2997797..c650471ff7c 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -368,8 +368,22 @@ config WINBOND_W83627
config QFW
bool
help
- Hidden option to enable QEMU fw_cfg interface. This will be selected by
- either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
+ Hidden option to enable QEMU fw_cfg interface and uclass. This will
+ be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
+
+config QFW_PIO
+ bool
+ depends on QFW
+ help
+ Hidden option to enable PIO QEMU fw_cfg interface. This will be
+ selected by the appropriate QEMU board.
+
+config QFW_MMIO
+ bool
+ depends on QFW
+ help
+ Hidden option to enable MMIO QEMU fw_cfg interface. This will be
+ selected by the appropriate QEMU board.
config I2C_EEPROM
bool "Enable driver for generic I2C-attached EEPROMs"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 1a493960074..0c67d43a5d4 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -55,7 +55,12 @@ obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
obj-$(CONFIG_P2SB) += p2sb-uclass.o
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
-obj-$(CONFIG_QFW) += qfw.o
+ifdef CONFIG_QFW
+obj-y += qfw.o
+obj-$(CONFIG_QFW_PIO) += qfw_pio.o
+obj-$(CONFIG_QFW_MMIO) += qfw_mmio.o
+obj-$(CONFIG_SANDBOX) += qfw_sandbox.o
+endif
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
diff --git a/drivers/misc/cbmem_console.c b/drivers/misc/cbmem_console.c
index 5ba0a542060..8bbe33d414d 100644
--- a/drivers/misc/cbmem_console.c
+++ b/drivers/misc/cbmem_console.c
@@ -9,7 +9,7 @@
#error This driver requires coreboot
#endif
-#include <asm/arch/sysinfo.h>
+#include <asm/cb_sysinfo.h>
struct cbmem_console {
u32 buffer_size;
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index ebfa7c41c25..7904d5cc72d 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -1170,6 +1170,23 @@ int cros_ec_battery_cutoff(struct udevice *dev, uint8_t flags)
return 0;
}
+int cros_ec_set_pwm_duty(struct udevice *dev, uint8_t index, uint16_t duty)
+{
+ struct ec_params_pwm_set_duty p;
+ int ret;
+
+ p.duty = duty;
+ p.pwm_type = EC_PWM_TYPE_GENERIC;
+ p.index = index;
+
+ ret = ec_command(dev, EC_CMD_PWM_SET_DUTY, 0, &p, sizeof(p),
+ NULL, 0);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
int cros_ec_set_ldo(struct udevice *dev, uint8_t index, uint8_t state)
{
struct ec_params_ldo_set params;
diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c
index cb8adc4495a..bc01df0904e 100644
--- a/drivers/misc/cros_ec_sandbox.c
+++ b/drivers/misc/cros_ec_sandbox.c
@@ -153,10 +153,14 @@ static int cros_ec_write_state(void *blob, int node)
{
struct ec_state *ec = g_state;
+ if (!g_state)
+ return 0;
+
/* We are guaranteed enough space to write basic properties */
fdt_setprop_u32(blob, node, "current-image", ec->current_image);
fdt_setprop(blob, node, "vbnv-context", ec->vbnv_context,
sizeof(ec->vbnv_context));
+
return state_setprop(node, "flash-data", ec->flash_data,
ec->ec_config.flash.length);
}
diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c
index 24b27962a7d..3aa26f61d9e 100644
--- a/drivers/misc/irq-uclass.c
+++ b/drivers/misc/irq-uclass.c
@@ -69,7 +69,7 @@ int irq_get_by_driver_info(struct udevice *dev,
{
int ret;
- ret = device_get_by_driver_info_idx(cells->idx, &irq->dev);
+ ret = device_get_by_ofplat_idx(cells->idx, &irq->dev);
if (ret)
return ret;
irq->id = cells->arg[0];
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 926c62c8a14..b1893a5c7eb 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -335,7 +335,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
struct ocotp_regs *regs;
int ret;
- if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1)) {
+ if (is_imx8mq() && (soc_rev() >= CHIP_REV_2_1)) {
printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__);
return -EPERM;
}
diff --git a/drivers/misc/p2sb_emul.c b/drivers/misc/p2sb_emul.c
index 973d02d6785..51f87161d5b 100644
--- a/drivers/misc/p2sb_emul.c
+++ b/drivers/misc/p2sb_emul.c
@@ -7,7 +7,6 @@
*/
#define LOG_CATEGORY UCLASS_MISC
-#define LOG_DEBUG
#include <common.h>
#include <axi.h>
diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c
index f6eb6583ed0..ea00be88a8d 100644
--- a/drivers/misc/qfw.c
+++ b/drivers/misc/qfw.c
@@ -1,25 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ * (C) Copyright 2021 Asherah Connor <ashe@kivikakk.ee>
*/
+#define LOG_CATEGORY UCLASS_QFW
+
#include <common.h>
#include <command.h>
#include <errno.h>
#include <log.h>
#include <malloc.h>
#include <qfw.h>
-#include <asm/io.h>
+#include <dm.h>
+#include <misc.h>
#ifdef CONFIG_GENERATE_ACPI_TABLE
#include <asm/tables.h>
#endif
-#include <linux/list.h>
-
-static bool fwcfg_present;
-static bool fwcfg_dma_present;
-static struct fw_cfg_arch_ops *fwcfg_arch_ops;
-
-static LIST_HEAD(fw_list);
#ifdef CONFIG_GENERATE_ACPI_TABLE
/*
@@ -32,7 +29,8 @@ static LIST_HEAD(fw_list);
* be ignored.
* @return: 0 on success, or negative value on failure
*/
-static int bios_linker_allocate(struct bios_linker_entry *entry, ulong *addr)
+static int bios_linker_allocate(struct udevice *dev,
+ struct bios_linker_entry *entry, ulong *addr)
{
uint32_t size, align;
struct fw_file *file;
@@ -45,7 +43,7 @@ static int bios_linker_allocate(struct bios_linker_entry *entry, ulong *addr)
return -EINVAL;
}
- file = qemu_fwcfg_find_file(entry->alloc.file);
+ file = qfw_find_file(dev, entry->alloc.file);
if (!file) {
printf("error: can't find file %s\n", entry->alloc.file);
return -ENOENT;
@@ -75,8 +73,8 @@ static int bios_linker_allocate(struct bios_linker_entry *entry, ulong *addr)
debug("bios_linker_allocate: allocate file %s, size %u, zone %d, align %u, addr 0x%lx\n",
file->cfg.name, size, entry->alloc.zone, align, aligned_addr);
- qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
- size, (void *)aligned_addr);
+ qfw_read_entry(dev, be16_to_cpu(file->cfg.select), size,
+ (void *)aligned_addr);
file->addr = aligned_addr;
/* adjust address for low memory allocation */
@@ -94,16 +92,17 @@ static int bios_linker_allocate(struct bios_linker_entry *entry, ulong *addr)
* ACPI tables
* @return: 0 on success, or negative value on failure
*/
-static int bios_linker_add_pointer(struct bios_linker_entry *entry)
+static int bios_linker_add_pointer(struct udevice *dev,
+ struct bios_linker_entry *entry)
{
struct fw_file *dest, *src;
uint32_t offset = le32_to_cpu(entry->pointer.offset);
uint64_t pointer = 0;
- dest = qemu_fwcfg_find_file(entry->pointer.dest_file);
+ dest = qfw_find_file(dev, entry->pointer.dest_file);
if (!dest || !dest->addr)
return -ENOENT;
- src = qemu_fwcfg_find_file(entry->pointer.src_file);
+ src = qfw_find_file(dev, entry->pointer.src_file);
if (!src || !src->addr)
return -ENOENT;
@@ -127,13 +126,14 @@ static int bios_linker_add_pointer(struct bios_linker_entry *entry)
* checksums
* @return: 0 on success, or negative value on failure
*/
-static int bios_linker_add_checksum(struct bios_linker_entry *entry)
+static int bios_linker_add_checksum(struct udevice *dev,
+ struct bios_linker_entry *entry)
{
struct fw_file *file;
uint8_t *data, cksum = 0;
uint8_t *cksum_start;
- file = qemu_fwcfg_find_file(entry->cksum.file);
+ file = qfw_find_file(dev, entry->cksum.file);
if (!file || !file->addr)
return -ENOENT;
@@ -149,20 +149,27 @@ static int bios_linker_add_checksum(struct bios_linker_entry *entry)
/* This function loads and patches ACPI tables provided by QEMU */
ulong write_acpi_tables(ulong addr)
{
- int i, ret = 0;
+ int i, ret;
struct fw_file *file;
struct bios_linker_entry *table_loader;
struct bios_linker_entry *entry;
uint32_t size;
+ struct udevice *dev;
+
+ ret = qfw_get_dev(&dev);
+ if (ret) {
+ printf("error: no qfw\n");
+ return addr;
+ }
/* make sure fw_list is loaded */
- ret = qemu_fwcfg_read_firmware_list();
+ ret = qfw_read_firmware_list(dev);
if (ret) {
printf("error: can't read firmware file list\n");
return addr;
}
- file = qemu_fwcfg_find_file("etc/table-loader");
+ file = qfw_find_file(dev, "etc/table-loader");
if (!file) {
printf("error: can't find etc/table-loader\n");
return addr;
@@ -180,24 +187,23 @@ ulong write_acpi_tables(ulong addr)
return addr;
}
- qemu_fwcfg_read_entry(be16_to_cpu(file->cfg.select),
- size, table_loader);
+ qfw_read_entry(dev, be16_to_cpu(file->cfg.select), size, table_loader);
for (i = 0; i < (size / sizeof(*entry)); i++) {
entry = table_loader + i;
switch (le32_to_cpu(entry->command)) {
case BIOS_LINKER_LOADER_COMMAND_ALLOCATE:
- ret = bios_linker_allocate(entry, &addr);
+ ret = bios_linker_allocate(dev, entry, &addr);
if (ret)
goto out;
break;
case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER:
- ret = bios_linker_add_pointer(entry);
+ ret = bios_linker_add_pointer(dev, entry);
if (ret)
goto out;
break;
case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM:
- ret = bios_linker_add_checksum(entry);
+ ret = bios_linker_add_checksum(dev, entry);
if (ret)
goto out;
break;
@@ -209,9 +215,9 @@ ulong write_acpi_tables(ulong addr)
out:
if (ret) {
struct fw_cfg_file_iter iter;
- for (file = qemu_fwcfg_file_iter_init(&iter);
- !qemu_fwcfg_file_iter_end(&iter);
- file = qemu_fwcfg_file_iter_next(&iter)) {
+ for (file = qfw_file_iter_init(dev, &iter);
+ !qfw_file_iter_end(&iter);
+ file = qfw_file_iter_next(&iter)) {
if (file->addr) {
free((void *)file->addr);
file->addr = 0;
@@ -225,170 +231,89 @@ out:
ulong acpi_get_rsdp_addr(void)
{
+ int ret;
struct fw_file *file;
+ struct udevice *dev;
- file = qemu_fwcfg_find_file("etc/acpi/rsdp");
+ ret = qfw_get_dev(&dev);
+ if (ret) {
+ printf("error: no qfw\n");
+ return 0;
+ }
+
+ file = qfw_find_file(dev, "etc/acpi/rsdp");
return file->addr;
}
#endif
-/* Read configuration item using fw_cfg PIO interface */
-static void qemu_fwcfg_read_entry_pio(uint16_t entry,
- uint32_t size, void *address)
+static void qfw_read_entry_io(struct qfw_dev *qdev, u16 entry, u32 size,
+ void *address)
{
- debug("qemu_fwcfg_read_entry_pio: entry 0x%x, size %u address %p\n",
- entry, size, address);
+ struct dm_qfw_ops *ops = dm_qfw_get_ops(qdev->dev);
+
+ debug("%s: entry 0x%x, size %u address %p\n", __func__, entry, size,
+ address);
- return fwcfg_arch_ops->arch_read_pio(entry, size, address);
+ ops->read_entry_io(qdev->dev, entry, size, address);
}
-/* Read configuration item using fw_cfg DMA interface */
-static void qemu_fwcfg_read_entry_dma(uint16_t entry,
- uint32_t size, void *address)
+static void qfw_read_entry_dma(struct qfw_dev *qdev, u16 entry, u32 size,
+ void *address)
{
- struct fw_cfg_dma_access dma;
+ struct dm_qfw_ops *ops = dm_qfw_get_ops(qdev->dev);
- dma.length = cpu_to_be32(size);
- dma.address = cpu_to_be64((uintptr_t)address);
- dma.control = cpu_to_be32(FW_CFG_DMA_READ);
+ struct qfw_dma dma = {
+ .length = cpu_to_be32(size),
+ .address = cpu_to_be64((uintptr_t)address),
+ .control = cpu_to_be32(FW_CFG_DMA_READ),
+ };
/*
- * writting FW_CFG_INVALID will cause read operation to resume at
- * last offset, otherwise read will start at offset 0
+ * writing FW_CFG_INVALID will cause read operation to resume at last
+ * offset, otherwise read will start at offset 0
*/
if (entry != FW_CFG_INVALID)
dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
- barrier();
-
- debug("qemu_fwcfg_read_entry_dma: entry 0x%x, size %u address %p, control 0x%x\n",
+ debug("%s: entry 0x%x, size %u address %p, control 0x%x\n", __func__,
entry, size, address, be32_to_cpu(dma.control));
- fwcfg_arch_ops->arch_read_dma(&dma);
-}
+ barrier();
-bool qemu_fwcfg_present(void)
-{
- return fwcfg_present;
+ ops->read_entry_dma(qdev->dev, &dma);
}
-bool qemu_fwcfg_dma_present(void)
+void qfw_read_entry(struct udevice *dev, u16 entry, u32 size, void *address)
{
- return fwcfg_dma_present;
-}
+ struct qfw_dev *qdev = dev_get_uclass_priv(dev);
-void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address)
-{
- if (fwcfg_dma_present)
- qemu_fwcfg_read_entry_dma(entry, length, address);
+ if (qdev->dma_present)
+ qfw_read_entry_dma(qdev, entry, size, address);
else
- qemu_fwcfg_read_entry_pio(entry, length, address);
+ qfw_read_entry_io(qdev, entry, size, address);
}
-int qemu_fwcfg_online_cpus(void)
+int qfw_register(struct udevice *dev)
{
- uint16_t nb_cpus;
+ struct qfw_dev *qdev = dev_get_uclass_priv(dev);
+ u32 qemu, dma_enabled;
- if (!fwcfg_present)
- return -ENODEV;
-
- qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
-
- return le16_to_cpu(nb_cpus);
-}
+ qdev->dev = dev;
+ INIT_LIST_HEAD(&qdev->fw_list);
-int qemu_fwcfg_read_firmware_list(void)
-{
- int i;
- uint32_t count;
- struct fw_file *file;
- struct list_head *entry;
-
- /* don't read it twice */
- if (!list_empty(&fw_list))
- return 0;
+ qfw_read_entry_io(qdev, FW_CFG_SIGNATURE, 4, &qemu);
+ if (be32_to_cpu(qemu) != QEMU_FW_CFG_SIGNATURE)
+ return -ENODEV;
- qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
- if (!count)
- return 0;
-
- count = be32_to_cpu(count);
- for (i = 0; i < count; i++) {
- file = malloc(sizeof(*file));
- if (!file) {
- printf("error: allocating resource\n");
- goto err;
- }
- qemu_fwcfg_read_entry(FW_CFG_INVALID,
- sizeof(struct fw_cfg_file), &file->cfg);
- file->addr = 0;
- list_add_tail(&file->list, &fw_list);
- }
+ qfw_read_entry_io(qdev, FW_CFG_ID, 1, &dma_enabled);
+ if (dma_enabled & FW_CFG_DMA_ENABLED)
+ qdev->dma_present = true;
return 0;
-
-err:
- list_for_each(entry, &fw_list) {
- file = list_entry(entry, struct fw_file, list);
- free(file);
- }
-
- return -ENOMEM;
}
-struct fw_file *qemu_fwcfg_find_file(const char *name)
-{
- struct list_head *entry;
- struct fw_file *file;
-
- list_for_each(entry, &fw_list) {
- file = list_entry(entry, struct fw_file, list);
- if (!strcmp(file->cfg.name, name))
- return file;
- }
-
- return NULL;
-}
-
-struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter)
-{
- iter->entry = fw_list.next;
- return list_entry((struct list_head *)iter->entry,
- struct fw_file, list);
-}
-
-struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter)
-{
- iter->entry = ((struct list_head *)iter->entry)->next;
- return list_entry((struct list_head *)iter->entry,
- struct fw_file, list);
-}
-
-bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter)
-{
- return iter->entry == &fw_list;
-}
-
-void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops)
-{
- uint32_t qemu;
- uint32_t dma_enabled;
-
- fwcfg_present = false;
- fwcfg_dma_present = false;
- fwcfg_arch_ops = NULL;
-
- if (!ops || !ops->arch_read_pio || !ops->arch_read_dma)
- return;
- fwcfg_arch_ops = ops;
-
- qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
- if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE)
- fwcfg_present = true;
-
- if (fwcfg_present) {
- qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
- if (dma_enabled & FW_CFG_DMA_ENABLED)
- fwcfg_dma_present = true;
- }
-}
+UCLASS_DRIVER(qfw) = {
+ .id = UCLASS_QFW,
+ .name = "qfw",
+ .per_device_auto = sizeof(struct qfw_dev),
+};
diff --git a/drivers/misc/qfw_mmio.c b/drivers/misc/qfw_mmio.c
new file mode 100644
index 00000000000..f397384054a
--- /dev/null
+++ b/drivers/misc/qfw_mmio.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * MMIO interface for QFW
+ *
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ * (C) Copyright 2021 Asherah Connor <ashe@kivikakk.ee>
+ */
+
+#define LOG_CATEGORY UCLASS_QFW
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device.h>
+#include <qfw.h>
+
+struct qfw_mmio {
+ /*
+ * Each access to the 64-bit data register can be 8/16/32/64 bits wide.
+ */
+ union {
+ u8 data8;
+ u16 data16;
+ u32 data32;
+ u64 data64;
+ };
+ u16 selector;
+ u8 padding[6];
+ u64 dma;
+};
+
+struct qfw_mmio_plat {
+ volatile struct qfw_mmio *mmio;
+};
+
+static void qfw_mmio_read_entry_io(struct udevice *dev, u16 entry, u32 size,
+ void *address)
+{
+ struct qfw_mmio_plat *plat = dev_get_plat(dev);
+
+ /*
+ * writing FW_CFG_INVALID will cause read operation to resume at last
+ * offset, otherwise read will start at offset 0
+ *
+ * Note: on platform where the control register is MMIO, the register
+ * is big endian.
+ */
+ if (entry != FW_CFG_INVALID)
+ plat->mmio->selector = cpu_to_be16(entry);
+
+ /* the endianness of data register is string-preserving */
+ while (size >= 8) {
+ *(u64 *)address = plat->mmio->data64;
+ address += 8;
+ size -= 8;
+ }
+ while (size >= 4) {
+ *(u32 *)address = plat->mmio->data32;
+ address += 4;
+ size -= 4;
+ }
+ while (size >= 2) {
+ *(u16 *)address = plat->mmio->data16;
+ address += 2;
+ size -= 2;
+ }
+ while (size >= 1) {
+ *(u8 *)address = plat->mmio->data8;
+ address += 1;
+ size -= 1;
+ }
+}
+
+/* Read configuration item using fw_cfg DMA interface */
+static void qfw_mmio_read_entry_dma(struct udevice *dev, struct qfw_dma *dma)
+{
+ struct qfw_mmio_plat *plat = dev_get_plat(dev);
+
+ /* the DMA address register is big-endian */
+ plat->mmio->dma = cpu_to_be64((uintptr_t)dma);
+
+ while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR);
+}
+
+static int qfw_mmio_of_to_plat(struct udevice *dev)
+{
+ struct qfw_mmio_plat *plat = dev_get_plat(dev);
+
+ plat->mmio = map_physmem(dev_read_addr(dev),
+ sizeof(struct qfw_mmio),
+ MAP_NOCACHE);
+
+ return 0;
+}
+
+static int qfw_mmio_probe(struct udevice *dev)
+{
+ return qfw_register(dev);
+}
+
+static struct dm_qfw_ops qfw_mmio_ops = {
+ .read_entry_io = qfw_mmio_read_entry_io,
+ .read_entry_dma = qfw_mmio_read_entry_dma,
+};
+
+static const struct udevice_id qfw_mmio_ids[] = {
+ { .compatible = "qemu,fw-cfg-mmio" },
+ {}
+};
+
+U_BOOT_DRIVER(qfw_mmio) = {
+ .name = "qfw_mmio",
+ .id = UCLASS_QFW,
+ .of_match = qfw_mmio_ids,
+ .plat_auto = sizeof(struct qfw_mmio_plat),
+ .of_to_plat = qfw_mmio_of_to_plat,
+ .probe = qfw_mmio_probe,
+ .ops = &qfw_mmio_ops,
+};
diff --git a/drivers/misc/qfw_pio.c b/drivers/misc/qfw_pio.c
new file mode 100644
index 00000000000..e2f628d3383
--- /dev/null
+++ b/drivers/misc/qfw_pio.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PIO interface for QFW
+ *
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ * (C) Copyright 2021 Asherah Connor <ashe@kivikakk.ee>
+ */
+
+#define LOG_CATEGORY UCLASS_QFW
+
+#include <asm/io.h>
+#include <dm/device.h>
+#include <qfw.h>
+
+/*
+ * PIO ports are correct for x86, which appears to be the only arch that uses
+ * PIO.
+ */
+#define FW_CONTROL_PORT 0x510
+#define FW_DATA_PORT 0x511
+#define FW_DMA_PORT_LOW 0x514
+#define FW_DMA_PORT_HIGH 0x518
+
+static void qfw_pio_read_entry_io(struct udevice *dev, u16 entry, u32 size,
+ void *address)
+{
+ /*
+ * writing FW_CFG_INVALID will cause read operation to resume at last
+ * offset, otherwise read will start at offset 0
+ *
+ * Note: on platform where the control register is IO port, the
+ * endianness is little endian.
+ */
+ if (entry != FW_CFG_INVALID)
+ outw(cpu_to_le16(entry), FW_CONTROL_PORT);
+
+ /* the endianness of data register is string-preserving */
+ u32 i = 0;
+ u8 *data = address;
+
+ while (size--)
+ data[i++] = inb(FW_DATA_PORT);
+}
+
+/* Read configuration item using fw_cfg DMA interface */
+static void qfw_pio_read_entry_dma(struct udevice *dev, struct qfw_dma *dma)
+{
+ /* the DMA address register is big-endian */
+ outl(cpu_to_be32((uintptr_t)dma), FW_DMA_PORT_HIGH);
+
+ while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR);
+}
+
+static int qfw_pio_probe(struct udevice *dev)
+{
+ return qfw_register(dev);
+}
+
+static struct dm_qfw_ops qfw_pio_ops = {
+ .read_entry_io = qfw_pio_read_entry_io,
+ .read_entry_dma = qfw_pio_read_entry_dma,
+};
+
+U_BOOT_DRIVER(qfw_pio) = {
+ .name = "qfw_pio",
+ .id = UCLASS_QFW,
+ .probe = qfw_pio_probe,
+ .ops = &qfw_pio_ops,
+};
diff --git a/drivers/misc/qfw_sandbox.c b/drivers/misc/qfw_sandbox.c
new file mode 100644
index 00000000000..b09974d33bd
--- /dev/null
+++ b/drivers/misc/qfw_sandbox.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Sandbox interface for QFW
+ *
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ * (C) Copyright 2021 Asherah Connor <ashe@kivikakk.ee>
+ */
+
+#define LOG_CATEGORY UCLASS_QFW
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device.h>
+#include <qfw.h>
+
+struct qfw_sandbox_plat {
+ u8 file_dir_offset;
+};
+
+static void qfw_sandbox_read_entry_io(struct udevice *dev, u16 entry, u32 size,
+ void *address)
+{
+ debug("%s: entry 0x%x size %u address %p\n", __func__, entry, size,
+ address);
+
+ switch (entry) {
+ case FW_CFG_SIGNATURE:
+ if (size == 4)
+ *((u32 *)address) = cpu_to_be32(QEMU_FW_CFG_SIGNATURE);
+ break;
+ case FW_CFG_ID:
+ /* Advertise DMA support */
+ if (size == 1)
+ *((u8 *)address) = FW_CFG_DMA_ENABLED;
+ break;
+ default:
+ debug("%s got unsupported entry 0x%x\n", __func__, entry);
+ /*
+ * Sandbox driver doesn't support other entries here, assume we use DMA
+ * to read them -- the uclass driver will exclusively use it when
+ * advertised.
+ */
+ }
+}
+
+static void qfw_sandbox_read_entry_dma(struct udevice *dev, struct qfw_dma *dma)
+{
+ u16 entry;
+ u32 control = be32_to_cpu(dma->control);
+ void *address = (void *)be64_to_cpu(dma->address);
+ u32 length = be32_to_cpu(dma->length);
+ struct qfw_sandbox_plat *plat = dev_get_plat(dev);
+ struct fw_cfg_file *file;
+
+ debug("%s\n", __func__);
+
+ if (!(control & FW_CFG_DMA_READ))
+ return;
+
+ if (control & FW_CFG_DMA_SELECT) {
+ /* Start new read. */
+ entry = control >> 16;
+
+ /* Arbitrary values to be used by tests. */
+ switch (entry) {
+ case FW_CFG_NB_CPUS:
+ if (length == 2)
+ *((u16 *)address) = cpu_to_le16(5);
+ break;
+ case FW_CFG_FILE_DIR:
+ if (length == 4) {
+ *((u32 *)address) = cpu_to_be32(2);
+ plat->file_dir_offset = 1;
+ }
+ break;
+ default:
+ debug("%s got unsupported entry 0x%x\n", __func__,
+ entry);
+ }
+ } else if (plat->file_dir_offset && length == 64) {
+ file = address;
+ switch (plat->file_dir_offset) {
+ case 1:
+ file->size = cpu_to_be32(8);
+ file->select = cpu_to_be16(FW_CFG_FILE_FIRST);
+ strcpy(file->name, "test-one");
+ plat->file_dir_offset++;
+ break;
+ case 2:
+ file->size = cpu_to_be32(8);
+ file->select = cpu_to_be16(FW_CFG_FILE_FIRST + 1);
+ strcpy(file->name, "test-two");
+ plat->file_dir_offset++;
+ break;
+ }
+ }
+
+ /*
+ * Signal that we are finished. No-one checks this in sandbox --
+ * normally the platform-specific driver looks for it -- but let's
+ * replicate the behaviour in case someone relies on it later.
+ */
+ dma->control = 0;
+}
+
+static int qfw_sandbox_probe(struct udevice *dev)
+{
+ return qfw_register(dev);
+}
+
+static struct dm_qfw_ops qfw_sandbox_ops = {
+ .read_entry_io = qfw_sandbox_read_entry_io,
+ .read_entry_dma = qfw_sandbox_read_entry_dma,
+};
+
+U_BOOT_DRIVER(qfw_sandbox) = {
+ .name = "qfw_sandbox",
+ .id = UCLASS_QFW,
+ .plat_auto = sizeof(struct qfw_sandbox_plat),
+ .probe = qfw_sandbox_probe,
+ .ops = &qfw_sandbox_ops,
+};
+
+U_BOOT_DRVINFO(qfw_sandbox) = {
+ .name = "qfw_sandbox",
+};
diff --git a/drivers/misc/test_drv.c b/drivers/misc/test_drv.c
index 827a50e954f..5d72982f258 100644
--- a/drivers/misc/test_drv.c
+++ b/drivers/misc/test_drv.c
@@ -86,7 +86,7 @@ static const struct udevice_id testbus_ids[] = {
{ }
};
-U_BOOT_DRIVER(testbus_drv) = {
+U_BOOT_DRIVER(denx_u_boot_test_bus) = {
.name = "testbus_drv",
.of_match = testbus_ids,
.id = UCLASS_TEST_BUS,
@@ -98,6 +98,7 @@ U_BOOT_DRIVER(testbus_drv) = {
.per_child_plat_auto = sizeof(struct dm_test_parent_plat),
.child_pre_probe = testbus_child_pre_probe,
.child_post_remove = testbus_child_post_remove,
+ DM_HEADER(<test.h>)
};
UCLASS_DRIVER(testbus) = {
@@ -106,6 +107,9 @@ UCLASS_DRIVER(testbus) = {
.flags = DM_UC_FLAG_SEQ_ALIAS,
.child_pre_probe = testbus_child_pre_probe_uclass,
.child_post_probe = testbus_child_post_probe_uclass,
+
+ /* This is for dtoc testing only */
+ .per_device_plat_auto = sizeof(struct dm_test_uclass_priv),
};
static int testfdt_drv_ping(struct udevice *dev, int pingval, int *pingret)
@@ -160,7 +164,9 @@ static const struct udevice_id testfdt_ids[] = {
{ }
};
-U_BOOT_DRIVER(testfdt_drv) = {
+DM_DRIVER_ALIAS(denx_u_boot_fdt_test, google_another_fdt_test)
+
+U_BOOT_DRIVER(denx_u_boot_fdt_test) = {
.name = "testfdt_drv",
.of_match = testfdt_ids,
.id = UCLASS_TEST_FDT,
@@ -203,6 +209,7 @@ UCLASS_DRIVER(testfdt) = {
.name = "testfdt",
.id = UCLASS_TEST_FDT,
.flags = DM_UC_FLAG_SEQ_ALIAS,
+ .priv_auto = sizeof(struct dm_test_uc_priv),
};
static const struct udevice_id testfdtm_ids[] = {
generated by cgit v1.2.3 (git 2.0.4) at 2025-09-30 10:22:57 +0000