diff options
Diffstat (limited to 'drivers/misc')
| -rw-r--r-- | drivers/misc/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/misc/i2c_eeprom.c | 8 | ||||
| -rw-r--r-- | drivers/misc/stm32_rcc.c | 5 | ||||
| -rw-r--r-- | drivers/misc/stm32mp_fuse.c | 74 |
4 files changed, 68 insertions, 21 deletions
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index cb8b5c04dbc..8037b6ee2d7 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -88,6 +88,7 @@ config CROS_EC config SPL_CROS_EC bool "Enable Chrome OS EC in SPL" + depends on SPL help Enable access to the Chrome OS EC in SPL. This is a separate microcontroller typically available on a SPI bus on Chromebooks. It @@ -97,6 +98,7 @@ config SPL_CROS_EC config TPL_CROS_EC bool "Enable Chrome OS EC in TPL" + depends on TPL help Enable access to the Chrome OS EC in TPL. This is a separate microcontroller typically available on a SPI bus on Chromebooks. It diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c index f25d0540075..8f2349ad5a7 100644 --- a/drivers/misc/i2c_eeprom.c +++ b/drivers/misc/i2c_eeprom.c @@ -84,6 +84,14 @@ static int i2c_eeprom_std_ofdata_to_platdata(struct udevice *dev) static int i2c_eeprom_std_probe(struct udevice *dev) { + u8 test_byte; + int ret; + + /* Verify that the chip is functional */ + ret = i2c_eeprom_read(dev, 0, &test_byte, 1); + if (ret) + return -ENODEV; + return 0; } diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c index 13d70696f64..e7efcdeafa3 100644 --- a/drivers/misc/stm32_rcc.c +++ b/drivers/misc/stm32_rcc.c @@ -68,8 +68,6 @@ static int stm32_rcc_bind(struct udevice *dev) dev_ofnode(dev), &child); } -static const struct misc_ops stm32_rcc_ops = { -}; static const struct udevice_id stm32_rcc_ids[] = { {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f42x }, @@ -82,8 +80,7 @@ static const struct udevice_id stm32_rcc_ids[] = { U_BOOT_DRIVER(stm32_rcc) = { .name = "stm32-rcc", - .id = UCLASS_MISC, + .id = UCLASS_NOP, .of_match = stm32_rcc_ids, .bind = stm32_rcc_bind, - .ops = &stm32_rcc_ops, }; diff --git a/drivers/misc/stm32mp_fuse.c b/drivers/misc/stm32mp_fuse.c index 801d946b773..0eed3459734 100644 --- a/drivers/misc/stm32mp_fuse.c +++ b/drivers/misc/stm32mp_fuse.c @@ -20,7 +20,7 @@ */ int fuse_read(u32 bank, u32 word, u32 *val) { - int ret = 0; + int ret; struct udevice *dev; switch (bank) { @@ -32,15 +32,25 @@ int fuse_read(u32 bank, u32 word, u32 *val) return ret; ret = misc_read(dev, word * 4 + STM32_BSEC_SHADOW_OFFSET, val, 4); - if (ret < 0) - return ret; - ret = 0; + if (ret != 4) + ret = -EINVAL; + else + ret = 0; break; #ifdef CONFIG_PMIC_STPMIC1 case STM32MP_NVM_BANK: + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stpmic1_nvm), + &dev); + if (ret) + return ret; *val = 0; - ret = stpmic1_shadow_read_byte(word, (u8 *)val); + ret = misc_read(dev, -word, val, 1); + if (ret != 1) + ret = -EINVAL; + else + ret = 0; break; #endif /* CONFIG_PMIC_STPMIC1 */ @@ -67,14 +77,24 @@ int fuse_prog(u32 bank, u32 word, u32 val) return ret; ret = misc_write(dev, word * 4 + STM32_BSEC_OTP_OFFSET, &val, 4); - if (ret < 0) - return ret; - ret = 0; + if (ret != 4) + ret = -EINVAL; + else + ret = 0; break; #ifdef CONFIG_PMIC_STPMIC1 case STM32MP_NVM_BANK: - ret = stpmic1_nvm_write_byte(word, (u8 *)&val); + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stpmic1_nvm), + &dev); + if (ret) + return ret; + ret = misc_write(dev, word, &val, 1); + if (ret != 1) + ret = -EINVAL; + else + ret = 0; break; #endif /* CONFIG_PMIC_STPMIC1 */ @@ -100,15 +120,25 @@ int fuse_sense(u32 bank, u32 word, u32 *val) if (ret) return ret; ret = misc_read(dev, word * 4 + STM32_BSEC_OTP_OFFSET, val, 4); - if (ret < 0) - return ret; - ret = 0; + if (ret != 4) + ret = -EINVAL; + else + ret = 0; break; #ifdef CONFIG_PMIC_STPMIC1 case STM32MP_NVM_BANK: + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stpmic1_nvm), + &dev); + if (ret) + return ret; *val = 0; - ret = stpmic1_nvm_read_byte(word, (u8 *)val); + ret = misc_read(dev, word, val, 1); + if (ret != 1) + ret = -EINVAL; + else + ret = 0; break; #endif /* CONFIG_PMIC_STPMIC1 */ @@ -135,14 +165,24 @@ int fuse_override(u32 bank, u32 word, u32 val) return ret; ret = misc_write(dev, word * 4 + STM32_BSEC_SHADOW_OFFSET, &val, 4); - if (ret < 0) - return ret; - ret = 0; + if (ret != 4) + ret = -EINVAL; + else + ret = 0; break; #ifdef CONFIG_PMIC_STPMIC1 case STM32MP_NVM_BANK: - ret = stpmic1_shadow_write_byte(word, (u8 *)&val); + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stpmic1_nvm), + &dev); + if (ret) + return ret; + ret = misc_write(dev, -word, &val, 1); + if (ret != 1) + ret = -EINVAL; + else + ret = 0; break; #endif /* CONFIG_PMIC_STPMIC1 */ |