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-rw-r--r--drivers/mmc/Kconfig4
-rw-r--r--drivers/mmc/renesas-sdhi.c74
-rw-r--r--drivers/mmc/sh_mmcif.h2
3 files changed, 40 insertions, 40 deletions
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 17618c3bdcc..cef05790dd9 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -393,7 +393,7 @@ config HSMMC2_8BIT
config SH_MMCIF
bool "SuperH/Renesas ARM SoCs on-chip MMCIF host controller support"
- depends on ARCH_RMOBILE || SH
+ depends on ARCH_RENESAS || SH
help
Support for the on-chip MMCIF host controller on SuperH/Renesas ARM SoCs platform
@@ -408,7 +408,7 @@ config MMC_UNIPHIER
config RENESAS_SDHI
bool "Renesas R-Car SD/MMC Host Controller support"
- depends on ARCH_RMOBILE
+ depends on ARCH_RENESAS
depends on BLK && DM_MMC
depends on OF_CONTROL
select BOUNCE_BUFFER
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index a74559ca686..20b1e9277eb 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -92,7 +92,7 @@ static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
};
-static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
+static int rcar_is_gen3_mmc0(struct tmio_sd_priv *priv)
{
/* On R-Car Gen3, MMC0 is at 0xee140000 */
return (uintptr_t)(priv->regbase) == 0xee140000;
@@ -885,80 +885,80 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
struct tmio_sd_plat *plat = dev_get_plat(dev);
/* HS400 is not supported on H3 ES1.x, M3W ES1.[012], V3M, V3H ES1.x, D3 */
- if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
- (rmobile_get_cpu_rev_integer() <= 1)) ||
- ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
- (rmobile_get_cpu_rev_integer() == 1) &&
- (rmobile_get_cpu_rev_fraction() <= 2)) ||
- (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970) ||
- ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77980) &&
- (rmobile_get_cpu_rev_integer() <= 1)) ||
- (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
+ if (((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7795) &&
+ (renesas_get_cpu_rev_integer() <= 1)) ||
+ ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7796) &&
+ (renesas_get_cpu_rev_integer() == 1) &&
+ (renesas_get_cpu_rev_fraction() <= 2)) ||
+ (renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77970) ||
+ ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77980) &&
+ (renesas_get_cpu_rev_integer() <= 1)) ||
+ (renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77995))
plat->cfg.host_caps &= ~MMC_MODE_HS400;
/* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
- if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
- (rmobile_get_cpu_rev_integer() >= 2)) ||
- ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
- (rmobile_get_cpu_rev_integer() == 1) &&
- (rmobile_get_cpu_rev_fraction() == 2)) ||
- (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
+ if (((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7795) &&
+ (renesas_get_cpu_rev_integer() >= 2)) ||
+ ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7796) &&
+ (renesas_get_cpu_rev_integer() == 1) &&
+ (renesas_get_cpu_rev_fraction() == 2)) ||
+ (renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77965))
priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
/* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
- if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
- (rmobile_get_cpu_rev_integer() == 1) &&
- (rmobile_get_cpu_rev_fraction() > 2)) {
+ if ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7796) &&
+ (renesas_get_cpu_rev_integer() == 1) &&
+ (renesas_get_cpu_rev_fraction() > 2)) {
priv->adjust_hs400_enable = true;
priv->adjust_hs400_offset = 3;
priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
priv->adjust_hs400_calib_table =
- r8a7796_rev13_calib_table[!rmobile_is_gen3_mmc0(priv)];
+ r8a7796_rev13_calib_table[!rcar_is_gen3_mmc0(priv)];
}
/* M3W+ bad taps */
- if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
- (rmobile_get_cpu_rev_integer() == 3))
+ if ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7796) &&
+ (renesas_get_cpu_rev_integer() == 3))
priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
/* M3N can use HS400 with manual adjustment */
- if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
+ if (renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77965) {
priv->adjust_hs400_enable = true;
priv->adjust_hs400_offset = 3;
priv->adjust_hs400_calib_table =
- r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)];
+ r8a77965_calib_table[!rcar_is_gen3_mmc0(priv)];
}
/* E3 can use HS400 with manual adjustment */
- if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
+ if (renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77990) {
priv->adjust_hs400_enable = true;
priv->adjust_hs400_offset = 3;
priv->adjust_hs400_calib_table =
- r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)];
+ r8a77990_calib_table[!rcar_is_gen3_mmc0(priv)];
}
/* H3 ES1.x, ES2.0 and M3W ES1.[0123] uses 4 tuning taps */
- if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
- (rmobile_get_cpu_rev_integer() <= 2)) ||
- ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
- (rmobile_get_cpu_rev_integer() == 1) &&
- (rmobile_get_cpu_rev_fraction() <= 3)))
+ if (((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7795) &&
+ (renesas_get_cpu_rev_integer() <= 2)) ||
+ ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7796) &&
+ (renesas_get_cpu_rev_integer() == 1) &&
+ (renesas_get_cpu_rev_fraction() <= 3)))
priv->nrtaps = 4;
else
priv->nrtaps = 8;
#endif
/* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
- if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
- (rmobile_get_cpu_rev_integer() <= 1)) ||
- ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
- (rmobile_get_cpu_rev_integer() == 1) &&
- (rmobile_get_cpu_rev_fraction() == 0)))
+ if (((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7795) &&
+ (renesas_get_cpu_rev_integer() <= 1)) ||
+ ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7796) &&
+ (renesas_get_cpu_rev_integer() == 1) &&
+ (renesas_get_cpu_rev_fraction() == 0)))
priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
else
priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
/* V3M handles SD0H differently than other Gen3 SoCs */
- if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970)
+ if (renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77970)
priv->needs_clkh_fallback = true;
else
priv->needs_clkh_fallback = false;
diff --git a/drivers/mmc/sh_mmcif.h b/drivers/mmc/sh_mmcif.h
index 66341e51d26..b131b8c2833 100644
--- a/drivers/mmc/sh_mmcif.h
+++ b/drivers/mmc/sh_mmcif.h
@@ -195,7 +195,7 @@ struct sh_mmcif_regs {
#define SOFT_RST_OFF (0 << 31)
#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
-#ifdef CONFIG_ARCH_RMOBILE
+#ifdef CONFIG_ARCH_RENESAS
#define MMC_CLK_DIV_MIN(clk) (clk / (1 << 9))
#define MMC_CLK_DIV_MAX(clk) (clk / (1 << 1))
#else
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-13 22:55:56 +0000