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-rw-r--r--drivers/mmc/fsl_esdhc.c30
-rw-r--r--drivers/mmc/fsl_esdhc_imx.c47
-rw-r--r--drivers/mmc/meson_gx_mmc.c29
-rw-r--r--drivers/mmc/meson_gx_mmc.h94
-rw-r--r--drivers/mmc/mmc.c155
-rw-r--r--drivers/mmc/sti_sdhci.c2
-rw-r--r--drivers/mmc/stm32_sdmmc2.c2
7 files changed, 250 insertions, 109 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 642784e1f35..a18316eda71 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -70,7 +70,9 @@ struct fsl_esdhc {
uint sdtimingctl; /* SD timing control register */
char reserved8[20]; /* reserved */
uint dllcfg0; /* DLL config 0 register */
- char reserved9[680]; /* reserved */
+ char reserved9[12]; /* reserved */
+ uint dllstat0; /* DLL status 0 register */
+ char reserved10[664];/* reserved */
uint esdhcctl; /* eSDHC control register */
};
@@ -617,9 +619,11 @@ static void esdhc_exit_hs400(struct fsl_esdhc_priv *priv)
esdhc_tuning_block_enable(priv, false);
}
-static void esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode)
+static int esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode)
{
struct fsl_esdhc *regs = priv->esdhc_regs;
+ ulong start;
+ u32 val;
/* Exit HS400 mode before setting any other mode */
if (esdhc_read32(&regs->tbctl) & HS400_MODE &&
@@ -640,17 +644,33 @@ static void esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode)
esdhc_setbits32(&regs->dllcfg0, DLL_FREQ_SEL);
esdhc_setbits32(&regs->dllcfg0, DLL_ENABLE);
+
+ esdhc_setbits32(&regs->dllcfg0, DLL_RESET);
+ udelay(1);
+ esdhc_clrbits32(&regs->dllcfg0, DLL_RESET);
+
+ start = get_timer(0);
+ val = DLL_STS_SLV_LOCK;
+ while (!(esdhc_read32(&regs->dllstat0) & val)) {
+ if (get_timer(start) > 1000) {
+ printf("fsl_esdhc: delay chain lock timeout\n");
+ return -ETIMEDOUT;
+ }
+ }
+
esdhc_setbits32(&regs->tbctl, HS400_WNDW_ADJUST);
esdhc_clock_control(priv, false);
esdhc_flush_async_fifo(priv);
}
esdhc_clock_control(priv, true);
+ return 0;
}
static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
{
struct fsl_esdhc *regs = priv->esdhc_regs;
+ int ret;
if (priv->is_sdhc_per_clk) {
/* Select to use peripheral clock */
@@ -667,7 +687,9 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
set_sysctl(priv, mmc, mmc->clock);
/* Set timing */
- esdhc_set_timing(priv, mmc->selected_mode);
+ ret = esdhc_set_timing(priv, mmc->selected_mode);
+ if (ret)
+ return ret;
/* Set the bus width */
esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
@@ -715,7 +737,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
/* Set the initial clock speed */
- mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
+ set_sysctl(priv, mmc, 400000);
/* Disable the BRR and BWR bits in IRQSTAT */
esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 22040c67a84..e5409ade1bc 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -760,7 +760,6 @@ static int esdhc_set_timing(struct mmc *mmc)
case MMC_HS_400_ES:
mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
esdhc_write32(&regs->mixctrl, mixctrl);
- esdhc_set_strobe_dll(mmc);
break;
case MMC_HS:
case MMC_HS_52:
@@ -933,6 +932,23 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
int ret __maybe_unused;
u32 clock;
+#ifdef MMC_SUPPORTS_TUNING
+ /*
+ * call esdhc_set_timing() before update the clock rate,
+ * This is because current we support DDR and SDR mode,
+ * Once the DDR_EN bit is set, the card clock will be
+ * divide by 2 automatically. So need to do this before
+ * setting clock rate.
+ */
+ if (priv->mode != mmc->selected_mode) {
+ ret = esdhc_set_timing(mmc);
+ if (ret) {
+ printf("esdhc_set_timing error %d\n", ret);
+ return ret;
+ }
+ }
+#endif
+
/* Set the clock speed */
clock = mmc->clock;
if (clock < mmc->cfg->f_min)
@@ -957,13 +973,13 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
#endif
}
- if (priv->mode != mmc->selected_mode) {
- ret = esdhc_set_timing(mmc);
- if (ret) {
- printf("esdhc_set_timing error %d\n", ret);
- return ret;
- }
- }
+ /*
+ * For HS400/HS400ES mode, make sure set the strobe dll in the
+ * target clock rate. So call esdhc_set_strobe_dll() after the
+ * clock updated.
+ */
+ if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES)
+ esdhc_set_strobe_dll(mmc);
if (priv->signal_voltage != mmc->signal_voltage) {
ret = esdhc_set_voltage(mmc);
@@ -1646,6 +1662,20 @@ static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
}
#endif
+static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
+ int timeout_us)
+{
+ int ret;
+ u32 tmp;
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+
+ ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp,
+ !!(tmp & PRSSTAT_DAT0) == !!state,
+ timeout_us);
+ return ret;
+}
+
static const struct dm_mmc_ops fsl_esdhc_ops = {
.get_cd = fsl_esdhc_get_cd,
.send_cmd = fsl_esdhc_send_cmd,
@@ -1656,6 +1686,7 @@ static const struct dm_mmc_ops fsl_esdhc_ops = {
#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
.set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
#endif
+ .wait_dat0 = fsl_esdhc_wait_dat0,
};
#endif
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index 719dd1e5e57..a5e9ac5637b 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -13,9 +13,17 @@
#include <mmc.h>
#include <asm/io.h>
#include <asm/gpio.h>
-#include <asm/arch/sd_emmc.h>
#include <linux/delay.h>
#include <linux/log2.h>
+#include "meson_gx_mmc.h"
+
+bool meson_gx_mmc_is_compatible(struct udevice *dev,
+ enum meson_gx_mmc_compatible family)
+{
+ enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev);
+
+ return compat == family;
+}
static inline void *get_regbase(const struct mmc *mmc)
{
@@ -42,6 +50,8 @@ static void meson_mmc_config_clock(struct mmc *mmc)
if (!mmc->clock)
return;
+ /* TOFIX This should use the proper clock taken from DT */
+
/* 1GHz / CLK_MAX_DIV = 15,9 MHz */
if (mmc->clock > 16000000) {
clk = SD_EMMC_CLKSRC_DIV2;
@@ -52,8 +62,16 @@ static void meson_mmc_config_clock(struct mmc *mmc)
}
clk_div = DIV_ROUND_UP(clk, mmc->clock);
- /* 180 phase core clock */
- meson_mmc_clk |= CLK_CO_PHASE_180;
+ /*
+ * SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180
+ * If CLK_CO_PHASE_270 is used, it's more stable than other.
+ * Other SoCs use CLK_CO_PHASE_180 by default.
+ * It needs to find what is a proper value about each SoCs.
+ */
+ if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
+ meson_mmc_clk |= CLK_CO_PHASE_270;
+ else
+ meson_mmc_clk |= CLK_CO_PHASE_180;
/* 180 phase tx clock */
meson_mmc_clk |= CLK_TX_PHASE_000;
@@ -308,8 +326,9 @@ int meson_mmc_bind(struct udevice *dev)
}
static const struct udevice_id meson_mmc_match[] = {
- { .compatible = "amlogic,meson-gx-mmc" },
- { .compatible = "amlogic,meson-axg-mmc" },
+ { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
+ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
+ { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
{ /* sentinel */ }
};
diff --git a/drivers/mmc/meson_gx_mmc.h b/drivers/mmc/meson_gx_mmc.h
new file mode 100644
index 00000000000..92aec5329f6
--- /dev/null
+++ b/drivers/mmc/meson_gx_mmc.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Carlo Caione <carlo@caione.org>
+ */
+
+#ifndef __MESON_GX_MMC_H__
+#define __MESON_GX_MMC_H__
+
+#include <mmc.h>
+#include <linux/bitops.h>
+
+enum meson_gx_mmc_compatible {
+ MMC_COMPATIBLE_GX,
+ MMC_COMPATIBLE_SM1,
+};
+
+#define SDIO_PORT_A 0
+#define SDIO_PORT_B 1
+#define SDIO_PORT_C 2
+
+#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */
+#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */
+
+#define MESON_SD_EMMC_CLOCK 0x00
+#define CLK_MAX_DIV 63
+#define CLK_SRC_24M (0 << 6)
+#define CLK_SRC_DIV2 (1 << 6)
+#define CLK_CO_PHASE_000 (0 << 8)
+#define CLK_CO_PHASE_090 (1 << 8)
+#define CLK_CO_PHASE_180 (2 << 8)
+#define CLK_CO_PHASE_270 (3 << 8)
+#define CLK_TX_PHASE_000 (0 << 10)
+#define CLK_TX_PHASE_090 (1 << 10)
+#define CLK_TX_PHASE_180 (2 << 10)
+#define CLK_TX_PHASE_270 (3 << 10)
+#define CLK_ALWAYS_ON BIT(24)
+
+#define MESON_SD_EMMC_CFG 0x44
+#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
+#define CFG_BUS_WIDTH_1 0
+#define CFG_BUS_WIDTH_4 1
+#define CFG_BUS_WIDTH_8 2
+#define CFG_BL_LEN_MASK GENMASK(7, 4)
+#define CFG_BL_LEN_SHIFT 4
+#define CFG_BL_LEN_512 (9 << 4)
+#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
+#define CFG_RESP_TIMEOUT_256 (8 << 8)
+#define CFG_RC_CC_MASK GENMASK(15, 12)
+#define CFG_RC_CC_16 (4 << 12)
+#define CFG_SDCLK_ALWAYS_ON BIT(18)
+#define CFG_AUTO_CLK BIT(23)
+
+#define MESON_SD_EMMC_STATUS 0x48
+#define STATUS_MASK GENMASK(15, 0)
+#define STATUS_ERR_MASK GENMASK(12, 0)
+#define STATUS_RXD_ERR_MASK GENMASK(7, 0)
+#define STATUS_TXD_ERR BIT(8)
+#define STATUS_DESC_ERR BIT(9)
+#define STATUS_RESP_ERR BIT(10)
+#define STATUS_RESP_TIMEOUT BIT(11)
+#define STATUS_DESC_TIMEOUT BIT(12)
+#define STATUS_END_OF_CHAIN BIT(13)
+
+#define MESON_SD_EMMC_IRQ_EN 0x4c
+
+#define MESON_SD_EMMC_CMD_CFG 0x50
+#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
+#define CMD_CFG_BLOCK_MODE BIT(9)
+#define CMD_CFG_R1B BIT(10)
+#define CMD_CFG_END_OF_CHAIN BIT(11)
+#define CMD_CFG_TIMEOUT_4S (12 << 12)
+#define CMD_CFG_NO_RESP BIT(16)
+#define CMD_CFG_DATA_IO BIT(18)
+#define CMD_CFG_DATA_WR BIT(19)
+#define CMD_CFG_RESP_NOCRC BIT(20)
+#define CMD_CFG_RESP_128 BIT(21)
+#define CMD_CFG_CMD_INDEX_SHIFT 24
+#define CMD_CFG_OWNER BIT(31)
+
+#define MESON_SD_EMMC_CMD_ARG 0x54
+#define MESON_SD_EMMC_CMD_DAT 0x58
+#define MESON_SD_EMMC_CMD_RSP 0x5c
+#define MESON_SD_EMMC_CMD_RSP1 0x60
+#define MESON_SD_EMMC_CMD_RSP2 0x64
+#define MESON_SD_EMMC_CMD_RSP3 0x68
+
+struct meson_mmc_platdata {
+ struct mmc_config cfg;
+ struct mmc mmc;
+ void *regbase;
+ void *w_buf;
+};
+
+#endif
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index a47700e313c..a6394bcf308 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -207,26 +207,65 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
}
#endif
+/**
+ * mmc_send_cmd_retry() - send a command to the mmc device, retrying on error
+ *
+ * @dev: device to receive the command
+ * @cmd: command to send
+ * @data: additional data to send/receive
+ * @retries: how many times to retry; mmc_send_cmd is always called at least
+ * once
+ * @return 0 if ok, -ve on error
+ */
+static int mmc_send_cmd_retry(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data, uint retries)
+{
+ int ret;
+
+ do {
+ ret = mmc_send_cmd(mmc, cmd, data);
+ } while (ret && retries--);
+
+ return ret;
+}
+
+/**
+ * mmc_send_cmd_quirks() - send a command to the mmc device, retrying if a
+ * specific quirk is enabled
+ *
+ * @dev: device to receive the command
+ * @cmd: command to send
+ * @data: additional data to send/receive
+ * @quirk: retry only if this quirk is enabled
+ * @retries: how many times to retry; mmc_send_cmd is always called at least
+ * once
+ * @return 0 if ok, -ve on error
+ */
+static int mmc_send_cmd_quirks(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data, u32 quirk, uint retries)
+{
+ if (CONFIG_IS_ENABLED(MMC_QUIRKS) && mmc->quirks & quirk)
+ return mmc_send_cmd_retry(mmc, cmd, data, retries);
+ else
+ return mmc_send_cmd(mmc, cmd, data);
+}
+
int mmc_send_status(struct mmc *mmc, unsigned int *status)
{
struct mmc_cmd cmd;
- int err, retries = 5;
+ int ret;
cmd.cmdidx = MMC_CMD_SEND_STATUS;
cmd.resp_type = MMC_RSP_R1;
if (!mmc_host_is_spi(mmc))
cmd.cmdarg = mmc->rca << 16;
- while (retries--) {
- err = mmc_send_cmd(mmc, &cmd, NULL);
- if (!err) {
- mmc_trace_state(mmc, &cmd);
- *status = cmd.response[0];
- return 0;
- }
- }
+ ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 4);
mmc_trace_state(mmc, &cmd);
- return -ECOMM;
+ if (!ret)
+ *status = cmd.response[0];
+
+ return ret;
}
int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
@@ -274,7 +313,6 @@ int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
int mmc_set_blocklen(struct mmc *mmc, int len)
{
struct mmc_cmd cmd;
- int err;
if (mmc->ddr_mode)
return 0;
@@ -283,24 +321,8 @@ int mmc_set_blocklen(struct mmc *mmc, int len)
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = len;
- err = mmc_send_cmd(mmc, &cmd, NULL);
-
-#ifdef CONFIG_MMC_QUIRKS
- if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
- int retries = 4;
- /*
- * It has been seen that SET_BLOCKLEN may fail on the first
- * attempt, let's try a few more time
- */
- do {
- err = mmc_send_cmd(mmc, &cmd, NULL);
- if (!err)
- break;
- } while (retries--);
- }
-#endif
-
- return err;
+ return mmc_send_cmd_quirks(mmc, &cmd, NULL,
+ MMC_QUIRK_RETRY_SET_BLOCKLEN, 4);
}
#ifdef MMC_SUPPORTS_TUNING
@@ -771,7 +793,6 @@ static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
(index == EXT_CSD_PART_CONF);
- int retries = 3;
int ret;
if (mmc->gen_cmd6_time)
@@ -786,10 +807,7 @@ static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
(index << 16) |
(value << 8);
- do {
- ret = mmc_send_cmd(mmc, &cmd, NULL);
- } while (ret && retries-- > 0);
-
+ ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 3);
if (ret)
return ret;
@@ -1287,22 +1305,15 @@ static int sd_get_capabilities(struct mmc *mmc)
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = 0;
- timeout = 3;
-
-retry_scr:
data.dest = (char *)scr;
data.blocksize = 8;
data.blocks = 1;
data.flags = MMC_DATA_READ;
- err = mmc_send_cmd(mmc, &cmd, &data);
-
- if (err) {
- if (timeout--)
- goto retry_scr;
+ err = mmc_send_cmd_retry(mmc, &cmd, &data, 3);
+ if (err)
return err;
- }
mmc->scr[0] = __be32_to_cpu(scr[0]);
mmc->scr[1] = __be32_to_cpu(scr[1]);
@@ -1463,28 +1474,13 @@ static int sd_read_ssr(struct mmc *mmc)
struct mmc_cmd cmd;
ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
struct mmc_data data;
- int timeout = 3;
unsigned int au, eo, et, es;
cmd.cmdidx = MMC_CMD_APP_CMD;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = mmc->rca << 16;
- err = mmc_send_cmd(mmc, &cmd, NULL);
-#ifdef CONFIG_MMC_QUIRKS
- if (err && (mmc->quirks & MMC_QUIRK_RETRY_APP_CMD)) {
- int retries = 4;
- /*
- * It has been seen that APP_CMD may fail on the first
- * attempt, let's try a few more times
- */
- do {
- err = mmc_send_cmd(mmc, &cmd, NULL);
- if (!err)
- break;
- } while (retries--);
- }
-#endif
+ err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_APP_CMD, 4);
if (err)
return err;
@@ -1492,19 +1488,14 @@ static int sd_read_ssr(struct mmc *mmc)
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = 0;
-retry_ssr:
data.dest = (char *)ssr;
data.blocksize = 64;
data.blocks = 1;
data.flags = MMC_DATA_READ;
- err = mmc_send_cmd(mmc, &cmd, &data);
- if (err) {
- if (timeout--)
- goto retry_ssr;
-
+ err = mmc_send_cmd_retry(mmc, &cmd, &data, 3);
+ if (err)
return err;
- }
for (i = 0; i < 16; i++)
ssr[i] = be32_to_cpu(ssr[i]);
@@ -2179,7 +2170,7 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
err = mmc_execute_tuning(mmc,
mwt->tuning);
if (err) {
- pr_debug("tuning failed\n");
+ pr_debug("tuning failed : %d\n", err);
goto error;
}
}
@@ -2200,7 +2191,7 @@ error:
}
}
- pr_err("unable to select a mode\n");
+ pr_err("unable to select a mode : %d\n", err);
return -ENOTSUPP;
}
@@ -2441,23 +2432,7 @@ static int mmc_startup(struct mmc *mmc)
cmd.resp_type = MMC_RSP_R2;
cmd.cmdarg = 0;
- err = mmc_send_cmd(mmc, &cmd, NULL);
-
-#ifdef CONFIG_MMC_QUIRKS
- if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
- int retries = 4;
- /*
- * It has been seen that SEND_CID may fail on the first
- * attempt, let's try a few more time
- */
- do {
- err = mmc_send_cmd(mmc, &cmd, NULL);
- if (!err)
- break;
- } while (retries--);
- }
-#endif
-
+ err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_SEND_CID, 4);
if (err)
return err;
@@ -2745,8 +2720,8 @@ static int mmc_power_on(struct mmc *mmc)
if (mmc->vmmc_supply) {
int ret = regulator_set_enable(mmc->vmmc_supply, true);
- if (ret) {
- puts("Error enabling VMMC supply\n");
+ if (ret && ret != -EACCES) {
+ printf("Error enabling VMMC supply : %d\n", ret);
return ret;
}
}
@@ -2761,8 +2736,8 @@ static int mmc_power_off(struct mmc *mmc)
if (mmc->vmmc_supply) {
int ret = regulator_set_enable(mmc->vmmc_supply, false);
- if (ret) {
- pr_debug("Error disabling VMMC supply\n");
+ if (ret && ret != -EACCES) {
+ pr_debug("Error disabling VMMC supply : %d\n", ret);
return ret;
}
}
@@ -2866,7 +2841,7 @@ retry:
if (err) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- pr_err("Card did not respond to voltage select!\n");
+ pr_err("Card did not respond to voltage select! : %d\n", err);
#endif
return -EOPNOTSUPP;
}
diff --git a/drivers/mmc/sti_sdhci.c b/drivers/mmc/sti_sdhci.c
index 5578feebef7..c3a1b344427 100644
--- a/drivers/mmc/sti_sdhci.c
+++ b/drivers/mmc/sti_sdhci.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
#include <common.h>
diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c
index 77871d5afc9..1f1b6cf4fb5 100644
--- a/drivers/mmc/stm32_sdmmc2.c
+++ b/drivers/mmc/stm32_sdmmc2.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
*/
#include <common.h>
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-30 08:45:02 +0000