diff options
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/Kconfig | 4 | ||||
| -rw-r--r-- | drivers/mmc/am654_sdhci.c | 5 | ||||
| -rw-r--r-- | drivers/mmc/cv1800b_sdhci.c | 4 | ||||
| -rw-r--r-- | drivers/mmc/mmc.c | 5 | ||||
| -rw-r--r-- | drivers/mmc/sdhci-cadence6.c | 2 | ||||
| -rw-r--r-- | drivers/mmc/snps_sdhci.c | 1 | ||||
| -rw-r--r-- | drivers/mmc/zynq_sdhci.c | 2 |
7 files changed, 17 insertions, 6 deletions
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 38867f30a7e..1c9b6898bff 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -528,7 +528,7 @@ config SPL_MMC_SDHCI_ADMA config MMC_SDHCI_ADMA_FORCE_32BIT bool "Force 32 bit mode for ADMA on 64 bit platforms" - depends on MMC_SDHCI_ADMA || SPL_MMC_SDHCI_ADMA + depends on MMC_SDHCI_ADMA_HELPERS help This forces SDHCI ADMA to be built for 32 bit descriptors, even on a 64 bit platform where they would otherwise be assumed to @@ -538,7 +538,7 @@ config MMC_SDHCI_ADMA_FORCE_32BIT config MMC_SDHCI_ADMA_64BIT bool "Use SHDCI ADMA with 64 bit descriptors" - depends on MMC_SDHCI_ADMA || SPL_MMC_SDHCI_ADMA + depends on MMC_SDHCI_ADMA_HELPERS depends on !MMC_SDHCI_ADMA_FORCE_32BIT default y if DMA_ADDR_T_64BIT help diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index 0df3568f073..d3c8f94dd0c 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -527,11 +527,16 @@ static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) void am654_sdhci_set_control_reg(struct sdhci_host *host) { struct mmc *mmc = host->mmc; + u32 reg; + reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); + reg &= ~SDHCI_CTRL_UHS_MASK; sdhci_set_voltage(host); if (mmc->selected_mode > MMC_HS_52) sdhci_set_uhs_timing(host); + else + sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); } const struct sdhci_ops am654_sdhci_ops = { diff --git a/drivers/mmc/cv1800b_sdhci.c b/drivers/mmc/cv1800b_sdhci.c index 4e75051c317..377e6a887df 100644 --- a/drivers/mmc/cv1800b_sdhci.c +++ b/drivers/mmc/cv1800b_sdhci.c @@ -31,6 +31,7 @@ static void cv1800b_sdhci_reset(struct sdhci_host *host, u8 mask) udelay(10); } +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) static int cv1800b_execute_tuning(struct mmc *mmc, u8 opcode) { struct sdhci_host *host = dev_get_priv(mmc->dev); @@ -61,9 +62,12 @@ static int cv1800b_execute_tuning(struct mmc *mmc, u8 opcode) return 0; } +#endif const struct sdhci_ops cv1800b_sdhci_sd_ops = { +#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING) .platform_execute_tuning = cv1800b_execute_tuning, +#endif }; static int cv1800b_sdhci_bind(struct udevice *dev) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index cdcf2e0c8fe..2c1f4f9c336 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -20,6 +20,7 @@ #include <linux/bitops.h> #include <linux/delay.h> #include <linux/printk.h> +#include <linux/sizes.h> #include <power/regulator.h> #include <malloc.h> #include <memalign.h> @@ -3277,8 +3278,8 @@ int mmc_set_bkops_enable(struct mmc *mmc, bool autobkops, bool enable) __weak int mmc_get_env_dev(void) { -#ifdef CONFIG_SYS_MMC_ENV_DEV - return CONFIG_SYS_MMC_ENV_DEV; +#ifdef CONFIG_ENV_MMC_DEVICE_INDEX + return CONFIG_ENV_MMC_DEVICE_INDEX; #else return 0; #endif diff --git a/drivers/mmc/sdhci-cadence6.c b/drivers/mmc/sdhci-cadence6.c index a5ed87321ab..9a92b8437a6 100644 --- a/drivers/mmc/sdhci-cadence6.c +++ b/drivers/mmc/sdhci-cadence6.c @@ -19,7 +19,7 @@ #include "sdhci-cadence.h" /* IO Delay Information */ -#define SDHCI_CDNS_HRS07 0X1C +#define SDHCI_CDNS_HRS07 0x1C #define SDHCI_CDNS_HRS07_RW_COMPENSATE GENMASK(20, 16) #define SDHCI_CDNS_HRS07_IDELAY_VAL GENMASK(4, 0) diff --git a/drivers/mmc/snps_sdhci.c b/drivers/mmc/snps_sdhci.c index f5ede38c3c1..fe834ec2969 100644 --- a/drivers/mmc/snps_sdhci.c +++ b/drivers/mmc/snps_sdhci.c @@ -6,6 +6,7 @@ #include <clk.h> #include <dm.h> #include <linux/bitfield.h> +#include <linux/sizes.h> #include <sdhci.h> /* DWCMSHC specific Mode Select value */ diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 0e2bdab4e7e..2375b15539b 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -83,7 +83,7 @@ #define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN 39 #define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL 146 -#define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL 0X77 +#define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL 0x77 struct arasan_sdhci_clk_data { int clk_phase_in[MMC_TIMING_MMC_HS400 + 1]; |