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-rw-r--r--drivers/mmc/Kconfig20
-rw-r--r--drivers/mmc/bcmstb_sdhci.c73
-rw-r--r--drivers/mmc/dw_mmc.c38
-rw-r--r--drivers/mmc/fsl_esdhc.c29
-rw-r--r--drivers/mmc/renesas-sdhi.c185
-rw-r--r--drivers/mmc/rockchip_dw_mmc.c4
-rw-r--r--drivers/mmc/sdhci.c188
-rw-r--r--drivers/mmc/tmio-common.h4
8 files changed, 451 insertions, 90 deletions
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index c34dd5d1879..c23299ea962 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -78,6 +78,12 @@ config SUPPORT_EMMC_RPMB
Enable support for reading, writing and programming the
key for the Replay Protection Memory Block partition in eMMC.
+config SUPPORT_EMMC_BOOT
+ bool "Support some additional features of the eMMC boot partitions"
+ help
+ Enable support for eMMC boot partitions. This also enables
+ extensions within the mmc command.
+
config MMC_IO_VOLTAGE
bool "Support IO voltage configuration"
help
@@ -385,6 +391,20 @@ config MMC_SDHCI_SDMA
This enables support for the SDMA (Single Operation DMA) defined
in the SD Host Controller Standard Specification Version 1.00 .
+config MMC_SDHCI_ADMA
+ bool "Support SDHCI ADMA2"
+ depends on MMC_SDHCI
+ help
+ This enables support for the ADMA (Advanced DMA) defined
+ in the SD Host Controller Standard Specification Version 3.00
+
+config SPL_MMC_SDHCI_ADMA
+ bool "Support SDHCI ADMA2 in SPL"
+ depends on MMC_SDHCI
+ help
+ This enables support for the ADMA (Advanced DMA) defined
+ in the SD Host Controller Standard Specification Version 3.00 in SPL.
+
config MMC_SDHCI_ATMEL
bool "Atmel SDHCI controller support"
depends on ARCH_AT91
diff --git a/drivers/mmc/bcmstb_sdhci.c b/drivers/mmc/bcmstb_sdhci.c
index 443ae8d4817..eef46f3af15 100644
--- a/drivers/mmc/bcmstb_sdhci.c
+++ b/drivers/mmc/bcmstb_sdhci.c
@@ -1,11 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018 Cisco Systems, Inc.
+ * (C) Copyright 2019 Synamedia
*
* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
*/
#include <common.h>
+#include <dm.h>
#include <mach/sdhci.h>
#include <malloc.h>
#include <sdhci.h>
@@ -36,32 +38,67 @@
*/
#define BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY 400000
-static char *BCMSTB_SDHCI_NAME = "bcmstb-sdhci";
-
/*
* This driver has only been tested with eMMC devices; SD devices may
* not work.
*/
-int bcmstb_sdhci_init(phys_addr_t regbase)
+struct sdhci_bcmstb_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+static int sdhci_bcmstb_bind(struct udevice *dev)
{
- struct sdhci_host *host = NULL;
+ struct sdhci_bcmstb_plat *plat = dev_get_platdata(dev);
- host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
- if (!host) {
- printf("%s: Failed to allocate memory\n", __func__);
- return 1;
- }
- memset(host, 0, sizeof(*host));
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static int sdhci_bcmstb_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct sdhci_bcmstb_plat *plat = dev_get_platdata(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ fdt_addr_t base;
+ int ret;
- host->name = BCMSTB_SDHCI_NAME;
- host->ioaddr = (void *)regbase;
- host->quirks = 0;
+ base = devfdt_get_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
- host->cfg.part_type = PART_TYPE_DOS;
+ host->name = dev->name;
+ host->ioaddr = (void *)base;
- host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
- return add_sdhci(host,
- BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY,
- BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY);
+ ret = sdhci_setup_cfg(&plat->cfg, host,
+ BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY,
+ BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY);
+ if (ret)
+ return ret;
+
+ upriv->mmc = &plat->mmc;
+ host->mmc = &plat->mmc;
+ host->mmc->priv = host;
+
+ return sdhci_probe(dev);
}
+
+static const struct udevice_id sdhci_bcmstb_match[] = {
+ { .compatible = "brcm,bcm7425-sdhci" },
+ { .compatible = "brcm,sdhci-brcmstb" },
+ { }
+};
+
+U_BOOT_DRIVER(sdhci_bcmstb) = {
+ .name = "sdhci-bcmstb",
+ .id = UCLASS_MMC,
+ .of_match = sdhci_bcmstb_match,
+ .ops = &sdhci_ops,
+ .bind = sdhci_bcmstb_bind,
+ .probe = sdhci_bcmstb_probe,
+ .priv_auto_alloc_size = sizeof(struct sdhci_host),
+ .platdata_auto_alloc_size = sizeof(struct sdhci_bcmstb_plat),
+};
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 93a836eac36..1992d611821 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -74,15 +74,15 @@ static void dwmci_prepare_data(struct dwmci_host *host,
dwmci_set_idma_desc(cur_idmac, flags, cnt,
(ulong)bounce_buffer + (i * PAGE_SIZE));
+ cur_idmac++;
if (blk_cnt <= 8)
break;
blk_cnt -= 8;
- cur_idmac++;
i++;
} while(1);
data_end = (ulong)cur_idmac;
- flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
+ flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN));
ctrl = dwmci_readl(host, DWMCI_CTRL);
ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
@@ -114,22 +114,40 @@ static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len)
return 0;
}
+static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size)
+{
+ unsigned int timeout;
+
+ timeout = size * 8 * 1000; /* counting in bits and msec */
+ timeout *= 2; /* wait twice as long */
+ timeout /= mmc->clock;
+ timeout /= mmc->bus_width;
+ timeout /= mmc->ddr_mode ? 2 : 1;
+ timeout = (timeout < 1000) ? 1000 : timeout;
+
+ return timeout;
+}
+
static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
{
+ struct mmc *mmc = host->mmc;
int ret = 0;
- u32 timeout = 240000;
- u32 mask, size, i, len = 0;
+ u32 timeout, mask, size, i, len = 0;
u32 *buf = NULL;
ulong start = get_timer(0);
u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
RX_WMARK_SHIFT) + 1) * 2;
- size = data->blocksize * data->blocks / 4;
+ size = data->blocksize * data->blocks;
if (data->flags == MMC_DATA_READ)
buf = (unsigned int *)data->dest;
else
buf = (unsigned int *)data->src;
+ timeout = dwmci_get_timeout(mmc, size);
+
+ size /= 4;
+
for (;;) {
mask = dwmci_readl(host, DWMCI_RINTSTS);
/* Error during data transfer. */
@@ -252,14 +270,20 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
} else {
if (data->flags == MMC_DATA_READ) {
- bounce_buffer_start(&bbstate, (void*)data->dest,
+ ret = bounce_buffer_start(&bbstate,
+ (void*)data->dest,
data->blocksize *
data->blocks, GEN_BB_WRITE);
} else {
- bounce_buffer_start(&bbstate, (void*)data->src,
+ ret = bounce_buffer_start(&bbstate,
+ (void*)data->src,
data->blocksize *
data->blocks, GEN_BB_READ);
}
+
+ if (ret)
+ return ret;
+
dwmci_prepare_data(host, data, cur_idmac,
bbstate.bounce_buffer);
}
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 9e34557d165..672691fa6a7 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -297,6 +297,13 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
return -ETIMEDOUT;
}
+ } else {
+#ifdef CONFIG_DM_GPIO
+ if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
+ printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
+ return -ETIMEDOUT;
+ }
+#endif
}
esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
@@ -1428,7 +1435,9 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
#endif
#if CONFIG_IS_ENABLED(DM_MMC)
+#ifndef CONFIG_PPC
#include <asm/arch/clock.h>
+#endif
__weak void init_clk_usdhc(u32 index)
{
}
@@ -1453,8 +1462,11 @@ static int fsl_esdhc_probe(struct udevice *dev)
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
-
+#ifdef CONFIG_PPC
+ priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
+#else
priv->esdhc_regs = (struct fsl_esdhc *)addr;
+#endif
priv->dev = dev;
priv->mode = -1;
if (data) {
@@ -1489,14 +1501,15 @@ static int fsl_esdhc_probe(struct udevice *dev)
#endif
}
- priv->wp_enable = 1;
-
+ if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
+ priv->wp_enable = 1;
+ } else {
+ priv->wp_enable = 0;
#ifdef CONFIG_DM_GPIO
- ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
+ gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
GPIOD_IS_IN);
- if (ret)
- priv->wp_enable = 0;
#endif
+ }
priv->vs18_enable = 0;
@@ -1560,7 +1573,11 @@ static int fsl_esdhc_probe(struct udevice *dev)
priv->sdhc_clk = clk_get_rate(&priv->per_clk);
} else {
+#ifndef CONFIG_PPC
priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
+#else
+ priv->sdhc_clk = gd->arch.sdhc_clk;
+#endif
if (priv->sdhc_clk <= 0) {
dev_err(dev, "Unable to get clk for %s\n", dev->name);
return -EINVAL;
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 6c51ccc294b..7c53aa221e5 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -23,24 +23,126 @@
/* SCC registers */
#define RENESAS_SDHI_SCC_DTCNTL 0x800
-#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
-#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
-#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
+#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
+#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
+#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
#define RENESAS_SDHI_SCC_TAPSET 0x804
#define RENESAS_SDHI_SCC_DT2FF 0x808
#define RENESAS_SDHI_SCC_CKSEL 0x80c
-#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
-#define RENESAS_SDHI_SCC_RVSCNTL 0x810
-#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
+#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
+#define RENESAS_SDHI_SCC_RVSCNTL 0x810
+#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
#define RENESAS_SDHI_SCC_RVSREQ 0x814
-#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
+#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
#define RENESAS_SDHI_SCC_SMPCMP 0x818
-#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
-#define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
-#define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
+#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
+#define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
+#define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
+#define RENESAS_SDHI_SCC_TMPPORT3 0x828
+#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0 3
+#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1 2
+#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2 1
+#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3 0
+#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK 0x3
+#define RENESAS_SDHI_SCC_TMPPORT4 0x82c
+#define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
+#define RENESAS_SDHI_SCC_TMPPORT5 0x830
+#define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
+#define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
+#define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
+#define RENESAS_SDHI_SCC_TMPPORT6 0x834
+#define RENESAS_SDHI_SCC_TMPPORT7 0x838
+#define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
+#define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
+#define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
#define RENESAS_SDHI_MAX_TAP 3
+static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
+{
+ /* read mode */
+ tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
+ (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
+ RENESAS_SDHI_SCC_TMPPORT5);
+
+ /* access start and stop */
+ tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
+ RENESAS_SDHI_SCC_TMPPORT4);
+ tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
+
+ return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
+}
+
+static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
+{
+ /* write mode */
+ tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
+ (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
+ RENESAS_SDHI_SCC_TMPPORT5);
+ tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
+
+ /* access start and stop */
+ tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
+ RENESAS_SDHI_SCC_TMPPORT4);
+ tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
+}
+
+static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
+{
+ u32 calib_code;
+
+ if (!priv->adjust_hs400_enable)
+ return;
+
+ if (!priv->needs_adjust_hs400)
+ return;
+
+ /*
+ * Enabled Manual adjust HS400 mode
+ *
+ * 1) Disabled Write Protect
+ * W(addr=0x00, WP_DISABLE_CODE)
+ * 2) Read Calibration code and adjust
+ * R(addr=0x26) - adjust value
+ * 3) Enabled Manual Calibration
+ * W(addr=0x22, manual mode | Calibration code)
+ * 4) Set Offset value to TMPPORT3 Reg
+ */
+ sd_scc_tmpport_write32(priv, 0x00,
+ RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
+ calib_code = sd_scc_tmpport_read32(priv, 0x26);
+ calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
+ if (calib_code > priv->adjust_hs400_calibrate)
+ calib_code -= priv->adjust_hs400_calibrate;
+ else
+ calib_code = 0;
+ sd_scc_tmpport_write32(priv, 0x22,
+ RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
+ calib_code);
+ tmio_sd_writel(priv, priv->adjust_hs400_offset,
+ RENESAS_SDHI_SCC_TMPPORT3);
+
+ /* Clear flag */
+ priv->needs_adjust_hs400 = false;
+}
+
+static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
+{
+
+ /* Disabled Manual adjust HS400 mode
+ *
+ * 1) Disabled Write Protect
+ * W(addr=0x00, WP_DISABLE_CODE)
+ * 2) Disabled Manual Calibration
+ * W(addr=0x22, 0)
+ * 3) Clear offset value to TMPPORT3 Reg
+ */
+ sd_scc_tmpport_write32(priv, 0x00,
+ RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
+ sd_scc_tmpport_write32(priv, 0x22, 0);
+ tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
+}
+
static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
{
u32 reg;
@@ -96,6 +198,9 @@ static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
+ /* Disable HS400 mode adjustment */
+ renesas_sdhi_adjust_hs400_mode_disable(priv);
+
reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
reg |= TMIO_SD_CLKCTL_SCLKEN;
tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
@@ -137,6 +242,10 @@ static int renesas_sdhi_hs400(struct udevice *dev)
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
+ /* Disable HS400 mode adjustment */
+ if (!hs400)
+ renesas_sdhi_adjust_hs400_mode_disable(priv);
+
tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
RENESAS_SDHI_SCC_DTCNTL_TAPEN,
RENESAS_SDHI_SCC_DTCNTL);
@@ -159,6 +268,10 @@ static int renesas_sdhi_hs400(struct udevice *dev)
reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
+ /* Execute adjust hs400 offset after setting to HS400 mode */
+ if (hs400)
+ priv->needs_adjust_hs400 = true;
+
return 0;
}
@@ -188,6 +301,8 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
bool select = false;
u32 reg;
+ priv->needs_adjust_hs400 = false;
+
/* Clear SCC_RVSREQ */
tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
@@ -405,8 +520,29 @@ static int renesas_sdhi_wait_dat0(struct udevice *dev, int state, int timeout)
}
#endif
+static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ int ret;
+
+ ret = tmio_sd_send_cmd(dev, cmd, data);
+ if (ret)
+ return ret;
+
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+
+ if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
+ renesas_sdhi_adjust_hs400_mode_enable(priv);
+#endif
+
+ return 0;
+}
+
static const struct dm_mmc_ops renesas_sdhi_ops = {
- .send_cmd = tmio_sd_send_cmd,
+ .send_cmd = renesas_sdhi_send_cmd,
.set_ios = renesas_sdhi_set_ios,
.get_cd = tmio_sd_get_cd,
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
@@ -451,14 +587,37 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
return;
- /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1 */
+ /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1,ES1.2 */
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() <= 1)) ||
((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
- (rmobile_get_cpu_rev_fraction() <= 1)))
+ (rmobile_get_cpu_rev_fraction() <= 2)))
plat->cfg.host_caps &= ~MMC_MODE_HS400;
+ /* M3W ES1.x for x>2 can use HS400 with manual adjustment */
+ if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
+ (rmobile_get_cpu_rev_integer() == 1) &&
+ (rmobile_get_cpu_rev_fraction() > 2)) {
+ priv->adjust_hs400_enable = true;
+ priv->adjust_hs400_offset = 0;
+ priv->adjust_hs400_calibrate = 0x9;
+ }
+
+ /* M3N can use HS400 with manual adjustment */
+ if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
+ priv->adjust_hs400_enable = true;
+ priv->adjust_hs400_offset = 0;
+ priv->adjust_hs400_calibrate = 0x0;
+ }
+
+ /* E3 can use HS400 with manual adjustment */
+ if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
+ priv->adjust_hs400_enable = true;
+ priv->adjust_hs400_offset = 0;
+ priv->adjust_hs400_calibrate = 0x2;
+ }
+
/* H3 ES2.0 uses 4 tuning taps */
if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() == 2))
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index bf2d83a52c5..b2a1201631a 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -13,8 +13,8 @@
#include <pwrseq.h>
#include <syscon.h>
#include <asm/gpio.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/periph.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/periph.h>
#include <linux/err.h>
struct rockchip_mmc_plat {
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index cdeba914f95..e2bb90abbdf 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -67,17 +67,123 @@ static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
}
}
-static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
- unsigned int start_addr)
+#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
+static void sdhci_adma_desc(struct sdhci_host *host, char *buf, u16 len,
+ bool end)
+{
+ struct sdhci_adma_desc *desc;
+ u8 attr;
+
+ desc = &host->adma_desc_table[host->desc_slot];
+
+ attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
+ if (!end)
+ host->desc_slot++;
+ else
+ attr |= ADMA_DESC_ATTR_END;
+
+ desc->attr = attr;
+ desc->len = len;
+ desc->reserved = 0;
+ desc->addr_lo = (dma_addr_t)buf;
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ desc->addr_hi = (u64)buf >> 32;
+#endif
+}
+
+static void sdhci_prepare_adma_table(struct sdhci_host *host,
+ struct mmc_data *data)
+{
+ uint trans_bytes = data->blocksize * data->blocks;
+ uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
+ int i = desc_count;
+ char *buf;
+
+ host->desc_slot = 0;
+
+ if (data->flags & MMC_DATA_READ)
+ buf = data->dest;
+ else
+ buf = (char *)data->src;
+
+ while (--i) {
+ sdhci_adma_desc(host, buf, ADMA_MAX_LEN, false);
+ buf += ADMA_MAX_LEN;
+ trans_bytes -= ADMA_MAX_LEN;
+ }
+
+ sdhci_adma_desc(host, buf, trans_bytes, true);
+
+ flush_cache((dma_addr_t)host->adma_desc_table,
+ ROUND(desc_count * sizeof(struct sdhci_adma_desc),
+ ARCH_DMA_MINALIGN));
+}
+#elif defined(CONFIG_MMC_SDHCI_SDMA)
+static void sdhci_prepare_adma_table(struct sdhci_host *host,
+ struct mmc_data *data)
+{}
+#endif
+#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
+static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
+ int *is_aligned, int trans_bytes)
{
- unsigned int stat, rdy, mask, timeout, block = 0;
- bool transfer_done = false;
-#ifdef CONFIG_MMC_SDHCI_SDMA
unsigned char ctrl;
+
+ if (data->flags == MMC_DATA_READ)
+ host->start_addr = (dma_addr_t)data->dest;
+ else
+ host->start_addr = (dma_addr_t)data->src;
+
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
ctrl &= ~SDHCI_CTRL_DMA_MASK;
+ if (host->flags & USE_ADMA64)
+ ctrl |= SDHCI_CTRL_ADMA64;
+ else if (host->flags & USE_ADMA)
+ ctrl |= SDHCI_CTRL_ADMA32;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+
+ if (host->flags & USE_SDMA) {
+ if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
+ (host->start_addr & 0x7) != 0x0) {
+ *is_aligned = 0;
+ host->start_addr = (unsigned long)aligned_buffer;
+ if (data->flags != MMC_DATA_READ)
+ memcpy(aligned_buffer, data->src, trans_bytes);
+ }
+
+#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
+ /*
+ * Always use this bounce-buffer when
+ * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
+ */
+ *is_aligned = 0;
+ host->start_addr = (unsigned long)aligned_buffer;
+ if (data->flags != MMC_DATA_READ)
+ memcpy(aligned_buffer, data->src, trans_bytes);
+#endif
+ sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS);
+
+ } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
+ sdhci_prepare_adma_table(host, data);
+
+ sdhci_writel(host, (u32)host->adma_addr, SDHCI_ADMA_ADDRESS);
+ if (host->flags & USE_ADMA64)
+ sdhci_writel(host, (u64)host->adma_addr >> 32,
+ SDHCI_ADMA_ADDRESS_HI);
+ }
+
+ flush_cache(host->start_addr, ROUND(trans_bytes, ARCH_DMA_MINALIGN));
+}
+#else
+static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
+ int *is_aligned, int trans_bytes)
+{}
#endif
+static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
+{
+ dma_addr_t start_addr = host->start_addr;
+ unsigned int stat, rdy, mask, timeout, block = 0;
+ bool transfer_done = false;
timeout = 1000000;
rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
@@ -104,14 +210,17 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
continue;
}
}
-#ifdef CONFIG_MMC_SDHCI_SDMA
- if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
+ if ((host->flags & USE_DMA) && !transfer_done &&
+ (stat & SDHCI_INT_DMA_END)) {
sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
- start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
- start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
- sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
+ if (host->flags & USE_SDMA) {
+ start_addr &=
+ ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
+ start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
+ sdhci_writel(host, start_addr,
+ SDHCI_DMA_ADDRESS);
+ }
}
-#endif
if (timeout-- > 0)
udelay(10);
else {
@@ -149,10 +258,11 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
int ret = 0;
int trans_bytes = 0, is_aligned = 1;
u32 mask, flags, mode;
- unsigned int time = 0, start_addr = 0;
+ unsigned int time = 0;
int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
ulong start = get_timer(0);
+ host->start_addr = 0;
/* Timeout unit - ms */
static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
@@ -218,33 +328,11 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
if (data->flags == MMC_DATA_READ)
mode |= SDHCI_TRNS_READ;
-#ifdef CONFIG_MMC_SDHCI_SDMA
- if (data->flags == MMC_DATA_READ)
- start_addr = (unsigned long)data->dest;
- else
- start_addr = (unsigned long)data->src;
- if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
- (start_addr & 0x7) != 0x0) {
- is_aligned = 0;
- start_addr = (unsigned long)aligned_buffer;
- if (data->flags != MMC_DATA_READ)
- memcpy(aligned_buffer, data->src, trans_bytes);
+ if (host->flags & USE_DMA) {
+ mode |= SDHCI_TRNS_DMA;
+ sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
}
-#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
- /*
- * Always use this bounce-buffer when
- * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
- */
- is_aligned = 0;
- start_addr = (unsigned long)aligned_buffer;
- if (data->flags != MMC_DATA_READ)
- memcpy(aligned_buffer, data->src, trans_bytes);
-#endif
-
- sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
- mode |= SDHCI_TRNS_DMA;
-#endif
sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
data->blocksize),
SDHCI_BLOCK_SIZE);
@@ -255,12 +343,6 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
}
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
-#ifdef CONFIG_MMC_SDHCI_SDMA
- if (data) {
- trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
- flush_cache(start_addr, trans_bytes);
- }
-#endif
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
start = get_timer(0);
do {
@@ -286,7 +368,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
ret = -1;
if (!ret && data)
- ret = sdhci_transfer_data(host, data, start_addr);
+ ret = sdhci_transfer_data(host, data);
if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
udelay(1000);
@@ -570,6 +652,24 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
__func__);
return -EINVAL;
}
+
+ host->flags |= USE_SDMA;
+#endif
+#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
+ if (!(caps & SDHCI_CAN_DO_ADMA2)) {
+ printf("%s: Your controller doesn't support SDMA!!\n",
+ __func__);
+ return -EINVAL;
+ }
+ host->adma_desc_table = (struct sdhci_adma_desc *)
+ memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
+
+ host->adma_addr = (dma_addr_t)host->adma_desc_table;
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ host->flags |= USE_ADMA64;
+#else
+ host->flags |= USE_ADMA;
+#endif
#endif
if (host->quirks & SDHCI_QUIRK_REG32_RW)
host->version =
diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h
index 58ce3d65b02..51607de1426 100644
--- a/drivers/mmc/tmio-common.h
+++ b/drivers/mmc/tmio-common.h
@@ -139,6 +139,10 @@ struct tmio_sd_priv {
#if CONFIG_IS_ENABLED(RENESAS_SDHI)
u8 tap_set;
u8 nrtaps;
+ bool needs_adjust_hs400;
+ bool adjust_hs400_enable;
+ u8 adjust_hs400_offset;
+ u8 adjust_hs400_calibrate;
#endif
ulong (*clk_get_rate)(struct tmio_sd_priv *);
};
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-23 10:33:08 +0000