diff options
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/Kconfig | 4 | ||||
| -rw-r--r-- | drivers/mmc/mmc.c | 1 | ||||
| -rw-r--r-- | drivers/mmc/sdhci-cadence6.c | 2 | ||||
| -rw-r--r-- | drivers/mmc/snps_sdhci.c | 1 | ||||
| -rw-r--r-- | drivers/mmc/zynq_sdhci.c | 2 |
5 files changed, 6 insertions, 4 deletions
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 38867f30a7e..1c9b6898bff 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -528,7 +528,7 @@ config SPL_MMC_SDHCI_ADMA config MMC_SDHCI_ADMA_FORCE_32BIT bool "Force 32 bit mode for ADMA on 64 bit platforms" - depends on MMC_SDHCI_ADMA || SPL_MMC_SDHCI_ADMA + depends on MMC_SDHCI_ADMA_HELPERS help This forces SDHCI ADMA to be built for 32 bit descriptors, even on a 64 bit platform where they would otherwise be assumed to @@ -538,7 +538,7 @@ config MMC_SDHCI_ADMA_FORCE_32BIT config MMC_SDHCI_ADMA_64BIT bool "Use SHDCI ADMA with 64 bit descriptors" - depends on MMC_SDHCI_ADMA || SPL_MMC_SDHCI_ADMA + depends on MMC_SDHCI_ADMA_HELPERS depends on !MMC_SDHCI_ADMA_FORCE_32BIT default y if DMA_ADDR_T_64BIT help diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index cdcf2e0c8fe..9421a846e45 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -20,6 +20,7 @@ #include <linux/bitops.h> #include <linux/delay.h> #include <linux/printk.h> +#include <linux/sizes.h> #include <power/regulator.h> #include <malloc.h> #include <memalign.h> diff --git a/drivers/mmc/sdhci-cadence6.c b/drivers/mmc/sdhci-cadence6.c index a5ed87321ab..9a92b8437a6 100644 --- a/drivers/mmc/sdhci-cadence6.c +++ b/drivers/mmc/sdhci-cadence6.c @@ -19,7 +19,7 @@ #include "sdhci-cadence.h" /* IO Delay Information */ -#define SDHCI_CDNS_HRS07 0X1C +#define SDHCI_CDNS_HRS07 0x1C #define SDHCI_CDNS_HRS07_RW_COMPENSATE GENMASK(20, 16) #define SDHCI_CDNS_HRS07_IDELAY_VAL GENMASK(4, 0) diff --git a/drivers/mmc/snps_sdhci.c b/drivers/mmc/snps_sdhci.c index f5ede38c3c1..fe834ec2969 100644 --- a/drivers/mmc/snps_sdhci.c +++ b/drivers/mmc/snps_sdhci.c @@ -6,6 +6,7 @@ #include <clk.h> #include <dm.h> #include <linux/bitfield.h> +#include <linux/sizes.h> #include <sdhci.h> /* DWCMSHC specific Mode Select value */ diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 0e2bdab4e7e..2375b15539b 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -83,7 +83,7 @@ #define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN 39 #define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL 146 -#define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL 0X77 +#define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL 0x77 struct arasan_sdhci_clk_data { int clk_phase_in[MMC_TIMING_MMC_HS400 + 1]; |