diff options
Diffstat (limited to 'drivers/mtd/nand/raw')
| -rw-r--r-- | drivers/mtd/nand/raw/Kconfig | 7 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/Makefile | 4 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/atmel/nand-controller.c | 4 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/atmel_nand.c | 4 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/brcmnand/Makefile | 1 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c | 152 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 6 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 8 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/nand_base.c | 10 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/omap_gpmc.c | 4 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/sand_nand.c | 4 |
11 files changed, 184 insertions, 20 deletions
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 9f3f1267cbd..c345fc1f1fb 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -120,6 +120,13 @@ config NAND_BRCMNAND Enable the driver for NAND flash on platforms using a Broadcom NAND controller. +config NAND_BRCMNAND_BCMBCA + bool "Support Broadcom NAND controller on BCMBCA platforms" + depends on NAND_BRCMNAND && ARCH_BCMBCA + help + Enable support for broadcom nand driver on BCA (broadband + access) platforms such as BCM6846. + config NAND_BRCMNAND_6368 bool "Support Broadcom NAND controller on bcm6368" depends on NAND_BRCMNAND && ARCH_BMIPS diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 46fead6fa48..b47a3d787ce 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifdef CONFIG_SPL_NAND_DRIVERS NORMAL_DRIVERS=y @@ -18,7 +18,7 @@ obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_amd.o nand_hynix.o \ nand_macronix.o nand_micron.o \ nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o -obj-$(CONFIG_$(SPL_TPL_)NAND_INIT) += nand.o +obj-$(CONFIG_$(PHASE_)NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o endif diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index ee4ec6da587..817fab4ca36 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1029,11 +1029,15 @@ static int atmel_nand_pmecc_init(struct nand_chip *chip) req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; else if (chip->ecc.strength) req.ecc.strength = chip->ecc.strength; + else if (chip->ecc_strength_ds) + req.ecc.strength = chip->ecc_strength_ds; else req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; if (chip->ecc.size) req.ecc.sectorsize = chip->ecc.size; + else if (chip->ecc_step_ds) + req.ecc.sectorsize = chip->ecc_step_ds; else req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO; diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index 4dbf7b47135..605298628d6 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -1251,7 +1251,7 @@ static int at91_nand_ready(struct mtd_info *mtd) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* The following code is for SPL */ static struct mtd_info *mtd; static struct nand_chip nand_chip; @@ -1526,4 +1526,4 @@ void board_nand_init(void) if (atmel_nand_chip_init(i, base_addr[i])) log_err("atmel_nand: Fail to initialize #%d chip", i); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/drivers/mtd/nand/raw/brcmnand/Makefile b/drivers/mtd/nand/raw/brcmnand/Makefile index 0c6325aaa61..24d0d568449 100644 --- a/drivers/mtd/nand/raw/brcmnand/Makefile +++ b/drivers/mtd/nand/raw/brcmnand/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_NAND_BRCMNAND_6753) += bcm6753_nand.o obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o +obj-$(CONFIG_NAND_BRCMNAND_BCMBCA) += bcmbca_nand.o obj-$(CONFIG_NAND_BRCMNAND_IPROC) += iproc_nand.o obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o obj-$(CONFIG_NAND_BRCMNAND) += brcmnand_compat.o diff --git a/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c b/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c new file mode 100644 index 00000000000..2753783ae70 --- /dev/null +++ b/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <asm/io.h> +#include <memalign.h> +#include <nand.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <linux/errno.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <dm.h> +#include <linux/printk.h> + +#include "brcmnand.h" + +struct bcmbca_nand_soc { + struct brcmnand_soc soc; + void __iomem *base; +}; + +#define BCMBCA_NAND_INT 0x00 +#define BCMBCA_NAND_STATUS_SHIFT 0 +#define BCMBCA_NAND_STATUS_MASK (0xfff << BCMBCA_NAND_STATUS_SHIFT) + +#define BCMBCA_NAND_INT_EN 0x04 +#define BCMBCA_NAND_ENABLE_SHIFT 0 +#define BCMBCA_NAND_ENABLE_MASK (0xffff << BCMBCA_NAND_ENABLE_SHIFT) + +enum { + BCMBCA_NP_READ = BIT(0), + BCMBCA_BLOCK_ERASE = BIT(1), + BCMBCA_COPY_BACK = BIT(2), + BCMBCA_PAGE_PGM = BIT(3), + BCMBCA_CTRL_READY = BIT(4), + BCMBCA_DEV_RBPIN = BIT(5), + BCMBCA_ECC_ERR_UNC = BIT(6), + BCMBCA_ECC_ERR_CORR = BIT(7), +}; + +#if defined(CONFIG_ARM64) +#define ALIGN_REQ 8 +#else +#define ALIGN_REQ 4 +#endif + +static inline bool bcmbca_nand_is_buf_aligned(void *flash_cache, void *buffer) +{ + return IS_ALIGNED((uintptr_t)buffer, ALIGN_REQ) && + IS_ALIGNED((uintptr_t)flash_cache, ALIGN_REQ); +} + +static bool bcmbca_nand_intc_ack(struct brcmnand_soc *soc) +{ + struct bcmbca_nand_soc *priv = + container_of(soc, struct bcmbca_nand_soc, soc); + void __iomem *mmio = priv->base + BCMBCA_NAND_INT; + u32 val = brcmnand_readl(mmio); + + if (val & (BCMBCA_CTRL_READY << BCMBCA_NAND_STATUS_SHIFT)) { + /* Ack interrupt */ + val &= ~BCMBCA_NAND_STATUS_MASK; + val |= BCMBCA_CTRL_READY << BCMBCA_NAND_STATUS_SHIFT; + brcmnand_writel(val, mmio); + return true; + } + + return false; +} + +static void bcmbca_nand_intc_set(struct brcmnand_soc *soc, bool en) +{ + struct bcmbca_nand_soc *priv = + container_of(soc, struct bcmbca_nand_soc, soc); + void __iomem *mmio = priv->base + BCMBCA_NAND_INT_EN; + u32 val = brcmnand_readl(mmio); + + /* Don't ack any interrupts */ + val &= ~BCMBCA_NAND_STATUS_MASK; + + if (en) + val |= BCMBCA_CTRL_READY << BCMBCA_NAND_ENABLE_SHIFT; + else + val &= ~(BCMBCA_CTRL_READY << BCMBCA_NAND_ENABLE_SHIFT); + + brcmnand_writel(val, mmio); +} + +static void bcmbca_read_data_bus(struct brcmnand_soc *soc, + void __iomem *flash_cache, u32 *buffer, int fc_words) +{ + /* + * memcpy can do unaligned aligned access depending on source + * and dest address, which is incompatible with nand cache. Fallback + * to the memcpy_fromio in such case + */ + if (bcmbca_nand_is_buf_aligned((void __force *)flash_cache, buffer)) + memcpy((void *)buffer, (void __force *)flash_cache, fc_words * 4); + else + memcpy_fromio((void *)buffer, flash_cache, fc_words * 4); +} + +static int bcmbca_nand_probe(struct udevice *dev) +{ + struct udevice *pdev = dev; + struct bcmbca_nand_soc *priv = dev_get_priv(dev); + struct brcmnand_soc *soc; + struct resource res; + + soc = &priv->soc; + + dev_read_resource_byname(pdev, "nand-int-base", &res); + priv->base = devm_ioremap(dev, res.start, resource_size(&res)); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + soc->ctlrdy_ack = bcmbca_nand_intc_ack; + soc->ctlrdy_set_enabled = bcmbca_nand_intc_set; + soc->read_data_bus = bcmbca_read_data_bus; + + /* Disable and ack all interrupts */ + brcmnand_writel(0, priv->base + BCMBCA_NAND_INT_EN); + brcmnand_writel(0, priv->base + BCMBCA_NAND_INT); + + return brcmnand_probe(pdev, soc); +} + +static const struct udevice_id bcmbca_nand_dt_ids[] = { + { + .compatible = "brcm,nand-bcm63138", + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(bcmbca_nand) = { + .name = "bcmbca-nand", + .id = UCLASS_MTD, + .of_match = bcmbca_nand_dt_ids, + .probe = bcmbca_nand_probe, + .priv_auto = sizeof(struct bcmbca_nand_soc), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(bcmbca_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize %s. (error %d)\n", dev->name, + ret); +} diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index c89661badbf..4430c4e93ee 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -152,7 +152,7 @@ static void lpc32xx_nand_init(void) &lpc32xx_nand_mlc_registers->time_reg); } -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) /** * lpc32xx_cmd_ctrl - write command to either cmd or data register @@ -606,7 +606,7 @@ void board_nand_init(void) pr_err("nand_register returned %i", ret); } -#else /* defined(CONFIG_SPL_BUILD) */ +#else /* defined(CONFIG_XPL_BUILD) */ void nand_init(void) { @@ -770,4 +770,4 @@ unsigned int nand_page_size(void) return BYTES_PER_PAGE; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index 4d643bc64bc..109c31fb4d1 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -84,7 +84,7 @@ static struct nand_ecclayout lpc32xx_nand_oob_16 = { } }; -#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD) #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CFG_SYS_NAND_ECCSIZE) /* @@ -162,7 +162,7 @@ static int lpc32xx_nand_dev_ready(struct mtd_info *mtd) return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY; } -#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD) /* * Prepares DMA descriptors for NAND RD/WR operations * If the size is < 256 Bytes then it is assumed to be @@ -510,7 +510,7 @@ static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte) */ int board_nand_init(struct nand_chip *lpc32xx_chip) { -#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD) int ret; /* Acquire a channel for our use */ @@ -533,7 +533,7 @@ int board_nand_init(struct nand_chip *lpc32xx_chip) lpc32xx_chip->read_byte = lpc32xx_read_byte; lpc32xx_chip->write_byte = lpc32xx_write_byte; -#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD) /* Hardware ECC calculation is supported when DMA driver is selected */ lpc32xx_chip->ecc.mode = NAND_ECC_HW; diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 0545c23e268..1b65c6f6443 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -414,7 +414,7 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) { struct nand_chip *chip = mtd_to_nand(mtd); int ret = 0; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int res; #endif @@ -434,7 +434,7 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) nand_release_device(mtd); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* Mark block bad in BBT */ if (chip->bbt) { res = nand_markbad_bbt(mtd, ofs); @@ -488,7 +488,7 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) if (!chip->bbt) return 0; /* Return info from the table */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD return nand_isreserved_bbt(mtd, ofs); #else return 0; @@ -518,7 +518,7 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) return chip->block_bad(mtd, ofs); /* Return info from the table */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD return nand_isbad_bbt(mtd, ofs, allowbbt); #else return 0; @@ -3729,7 +3729,7 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) if (!chip->read_buf || chip->read_buf == nand_read_buf) chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD if (!chip->scan_bbt) chip->scan_bbt = nand_default_bbt; #endif diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index a36e2a148cc..9c704c60e8e 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -1011,7 +1011,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * omap_nand_switch_ecc - switch the ECC operation between different engines * (h/w and s/w) and different algorithms (hamming and BCHx) @@ -1072,7 +1072,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) err = nand_scan_tail(mtd); return err; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* * Board-specific NAND initialization. The following members of the diff --git a/drivers/mtd/nand/raw/sand_nand.c b/drivers/mtd/nand/raw/sand_nand.c index 229d7b5b65a..3678bb8a41b 100644 --- a/drivers/mtd/nand/raw/sand_nand.c +++ b/drivers/mtd/nand/raw/sand_nand.c @@ -601,7 +601,7 @@ static int sand_nand_probe(struct udevice *dev) } nand = &chip->nand; - nand->options = spl_in_proper() ? 0 : NAND_SKIP_BBTSCAN; + nand->options = not_xpl() ? 0 : NAND_SKIP_BBTSCAN; nand->flash_node = np; nand->dev_ready = sand_nand_dev_ready; nand->cmdfunc = sand_nand_command; @@ -680,7 +680,7 @@ void board_nand_init(void) log_info("Failed to get sandbox NAND: %d\n", err); } -#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_NAND_INIT) +#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_NAND_INIT) void nand_deselect(void) { nand_chip->select_chip(nand_to_mtd(nand_chip), -1); |