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-rw-r--r--drivers/mtd/mtdpart.c14
-rw-r--r--drivers/mtd/nand/spi/core.c18
-rw-r--r--drivers/mtd/spi/spi-nor-core.c35
-rw-r--r--drivers/mtd/spi/spi-nor-ids.c11
4 files changed, 58 insertions, 20 deletions
diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c
index 3f8edeb5093..842d3e7274e 100644
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
@@ -236,6 +236,10 @@ int mtd_parse_partitions(struct mtd_info *parent, const char **_mtdparts,
if (ret)
return ret;
+ if (parts[idx].offset == MTD_OFFSET_NOT_SPECIFIED)
+ parts[idx].offset = cur_off;
+ cur_off += parts[idx].size;
+
if (parts[idx].size == MTD_SIZE_REMAINING)
parts[idx].size = parent->size - parts[idx].offset;
@@ -246,10 +250,6 @@ int mtd_parse_partitions(struct mtd_info *parent, const char **_mtdparts,
return -EINVAL;
}
- if (parts[idx].offset == MTD_OFFSET_NOT_SPECIFIED)
- parts[idx].offset = cur_off;
- cur_off += parts[idx].size;
-
parts[idx].ecclayout = parent->ecclayout;
}
@@ -909,11 +909,13 @@ int add_mtd_partitions_of(struct mtd_info *master)
continue;
offset = ofnode_get_addr_size_index_notrans(child, 0, &size);
- if (offset == FDT_ADDR_T_NONE || !size) {
- debug("Missing partition offset/size on \"%s\" partition\n",
+ if (offset == FDT_ADDR_T_NONE) {
+ debug("Missing partition offset on \"%s\" partition\n",
master->name);
continue;
}
+ if (size == MTDPART_SIZ_FULL)
+ size = master->size - offset;
part.name = ofnode_read_string(child, "label");
if (!part.name)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index f5ddfbf4b83..3a1e7e18736 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -941,6 +941,19 @@ spinand_select_op_variant(struct spinand_device *spinand,
return NULL;
}
+static int spinand_setup_slave(struct spinand_device *spinand,
+ const struct spinand_info *spinand_info)
+{
+ struct spi_slave *slave = spinand->slave;
+ struct udevice *bus = slave->dev->parent;
+ struct dm_spi_ops *ops = spi_get_ops(bus);
+
+ if (!ops->setup_for_spinand)
+ return 0;
+
+ return ops->setup_for_spinand(slave, spinand_info);
+}
+
/**
* spinand_match_and_init() - Try to find a match between a device ID and an
* entry in a spinand_info table
@@ -964,6 +977,7 @@ int spinand_match_and_init(struct spinand_device *spinand,
u8 *id = spinand->id.data;
struct nand_device *nand = spinand_to_nand(spinand);
unsigned int i;
+ int ret;
for (i = 0; i < table_size; i++) {
const struct spinand_info *info = &table[i];
@@ -975,6 +989,10 @@ int spinand_match_and_init(struct spinand_device *spinand,
if (memcmp(id + 1, info->devid.id, info->devid.len))
continue;
+ ret = spinand_setup_slave(spinand, info);
+ if (ret)
+ return ret;
+
nand->memorg = table[i].memorg;
nand->eccreq = table[i].eccreq;
spinand->eccinfo = table[i].eccinfo;
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 6f352c5c0e2..87a3099eeaf 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -655,7 +655,7 @@ static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
return mtd->priv;
}
-#ifndef CONFIG_SPI_FLASH_BAR
+#if !CONFIG_IS_ENABLED(SPI_FLASH_BAR)
static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
{
size_t i;
@@ -739,7 +739,7 @@ static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
}
-#endif /* !CONFIG_SPI_FLASH_BAR */
+#endif /* !CONFIG_IS_ENABLED(SPI_FLASH_BAR) */
/* Enable/disable 4-byte addressing mode. */
static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
@@ -930,7 +930,7 @@ static int spi_nor_erase_chip_wait_till_ready(struct spi_nor *nor, unsigned long
return spi_nor_wait_till_ready_with_timeout(nor, timeout);
}
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
/*
* This "clean_bar" is necessary in a situation when one was accessing
* spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
@@ -1141,7 +1141,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
nor->spi->flags &= ~SPI_XFER_U_PAGE;
}
}
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
ret = write_bar(nor, offset);
if (ret < 0)
goto erase_err;
@@ -1175,7 +1175,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
addr_known = false;
erase_err:
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
err = clean_bar(nor);
if (!ret)
ret = err;
@@ -1630,7 +1630,7 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
offset /= 2;
}
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
ret = write_bar(nor, offset);
if (ret < 0)
return log_ret(ret);
@@ -1667,7 +1667,7 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
ret = 0;
read_err:
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
ret = clean_bar(nor);
#endif
return ret;
@@ -2016,7 +2016,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
}
}
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
ret = write_bar(nor, offset);
if (ret < 0)
return ret;
@@ -2090,7 +2090,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
}
write_err:
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
ret = clean_bar(nor);
#endif
return ret;
@@ -3592,6 +3592,19 @@ static int spi_nor_select_erase(struct spi_nor *nor,
mtd->erasesize = info->sector_size;
}
+ if ((JEDEC_MFR(info) == SNOR_MFR_SST) && info->flags & SECT_4K) {
+ nor->erase_opcode = SPINOR_OP_BE_4K;
+ /*
+ * In parallel-memories the erase operation is
+ * performed on both the flashes simultaneously
+ * so, double the erasesize.
+ */
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ mtd->erasesize = 4096 * 2;
+ else
+ mtd->erasesize = 4096;
+ }
+
return 0;
}
@@ -3791,7 +3804,7 @@ static int s25_s28_setup(struct spi_nor *nor, const struct flash_info *info,
int ret;
u8 cr;
-#ifdef CONFIG_SPI_FLASH_BAR
+#if CONFIG_IS_ENABLED(SPI_FLASH_BAR)
return -ENOTSUPP; /* Bank Address Register is not supported */
#endif
/*
@@ -4577,7 +4590,7 @@ int spi_nor_scan(struct spi_nor *nor)
if (nor->flags & (SNOR_F_HAS_PARALLEL | SNOR_F_HAS_STACKED))
shift = 1;
if (nor->addr_width == 3 && (mtd->size >> shift) > SZ_16M) {
-#ifndef CONFIG_SPI_FLASH_BAR
+#if !CONFIG_IS_ENABLED(SPI_FLASH_BAR)
/* enable 4-byte addressing if the device exceeds 16MiB */
nor->addr_width = 4;
if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 91ae49c9484..e7e97780d7c 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -358,10 +358,13 @@ const struct flash_info spi_nor_ids[] = {
#ifdef CONFIG_SPI_FLASH_MT35XU
{ INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
{ INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
- { INFO("mt35xu01gaba", 0x2c5b1b, 0, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mt35xu01gaba", 0x2c5b1b, 0, 128 * 1024, 1024,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
#endif /* CONFIG_SPI_FLASH_MT35XU */
- { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
- { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
+ { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
+ { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048,
+ USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
/* Spansion/Cypress -- single (large) sector size only, at least
@@ -414,8 +417,10 @@ const struct flash_info spi_nor_ids[] = {
{ INFO6("s25fs256t", 0x342b19, 0x0f0890, 128 * 1024, 256,
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
#ifdef CONFIG_SPI_FLASH_S28HX_T
+ { INFO("s28hl256t", 0x345a19, 0, 256 * 1024, 128, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hl512t", 0x345a1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hl01gt", 0x345a1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) },
+ { INFO("s28hl02gt", 0x345a1c, 0, 256 * 1024, 1024, SPI_NOR_OCTAL_DTR_READ | NO_CHIP_ERASE) },
{ INFO("s28hs256t", 0x345b19, 0, 256 * 1024, 128, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hs01gt", 0x345b1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) },
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-04 07:32:17 +0000