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-rw-r--r--drivers/mtd/Makefile6
-rw-r--r--drivers/mtd/nand/Makefile4
-rw-r--r--drivers/mtd/nand/raw/Makefile4
-rw-r--r--drivers/mtd/nand/raw/atmel_nand.c4
-rw-r--r--drivers/mtd/nand/raw/lpc32xx_nand_mlc.c6
-rw-r--r--drivers/mtd/nand/raw/lpc32xx_nand_slc.c8
-rw-r--r--drivers/mtd/nand/raw/nand_base.c10
-rw-r--r--drivers/mtd/nand/raw/omap_gpmc.c4
-rw-r--r--drivers/mtd/nand/raw/sand_nand.c4
-rw-r--r--drivers/mtd/onenand/Makefile2
-rw-r--r--drivers/mtd/spi/Makefile10
-rw-r--r--drivers/mtd/spi/sf-uclass.c2
-rw-r--r--drivers/mtd/spi/sf_dataflash.c2
-rw-r--r--drivers/mtd/spi/spi-nor-core.c79
-rw-r--r--drivers/mtd/spi/spi-nor-ids.c29
15 files changed, 119 insertions, 55 deletions
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 10d575e9f93..ce05e206073 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -16,7 +16,7 @@ mtd-$(CONFIG_RENESAS_RPC_HF) += renesas_rpc_hf.o
mtd-$(CONFIG_HBMC_AM654) += hbmc-am654.o
# U-Boot build
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
+ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
ifneq ($(mtd-y),)
obj-y += mtd.o
@@ -34,9 +34,9 @@ else
ifneq ($(mtd-y),)
obj-$(CONFIG_SPL_MTD) += mtd.o
endif
-obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += nand/
+obj-$(CONFIG_$(PHASE_)NAND_SUPPORT) += nand/
obj-$(CONFIG_SPL_ONENAND_SUPPORT) += onenand/
-obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPORT) += spi/
+obj-$(CONFIG_$(PHASE_)SPI_FLASH_SUPPORT) += spi/
obj-$(CONFIG_SPL_UBI) += ubispl/
endif
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 96e186600a1..c8169cf7390 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -1,10 +1,10 @@
# SPDX-License-Identifier: GPL-2.0+
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
+ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
nandcore-objs := core.o bbt.o
obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
obj-$(CONFIG_MTD_RAW_NAND) += raw/
obj-$(CONFIG_MTD_SPI_NAND) += spi/
else
-obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += raw/
+obj-$(CONFIG_$(PHASE_)NAND_SUPPORT) += raw/
endif
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 46fead6fa48..b47a3d787ce 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -3,7 +3,7 @@
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifdef CONFIG_SPL_NAND_DRIVERS
NORMAL_DRIVERS=y
@@ -18,7 +18,7 @@ obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_amd.o nand_hynix.o \
nand_macronix.o nand_micron.o \
nand_samsung.o nand_toshiba.o
obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o
-obj-$(CONFIG_$(SPL_TPL_)NAND_INIT) += nand.o
+obj-$(CONFIG_$(PHASE_)NAND_INIT) += nand.o
ifeq ($(CONFIG_SPL_ENV_SUPPORT),y)
obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o
endif
diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c
index 4dbf7b47135..605298628d6 100644
--- a/drivers/mtd/nand/raw/atmel_nand.c
+++ b/drivers/mtd/nand/raw/atmel_nand.c
@@ -1251,7 +1251,7 @@ static int at91_nand_ready(struct mtd_info *mtd)
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* The following code is for SPL */
static struct mtd_info *mtd;
static struct nand_chip nand_chip;
@@ -1526,4 +1526,4 @@ void board_nand_init(void)
if (atmel_nand_chip_init(i, base_addr[i]))
log_err("atmel_nand: Fail to initialize #%d chip", i);
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
index c89661badbf..4430c4e93ee 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
@@ -152,7 +152,7 @@ static void lpc32xx_nand_init(void)
&lpc32xx_nand_mlc_registers->time_reg);
}
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
/**
* lpc32xx_cmd_ctrl - write command to either cmd or data register
@@ -606,7 +606,7 @@ void board_nand_init(void)
pr_err("nand_register returned %i", ret);
}
-#else /* defined(CONFIG_SPL_BUILD) */
+#else /* defined(CONFIG_XPL_BUILD) */
void nand_init(void)
{
@@ -770,4 +770,4 @@ unsigned int nand_page_size(void)
return BYTES_PER_PAGE;
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
index 4d643bc64bc..109c31fb4d1 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
@@ -84,7 +84,7 @@ static struct nand_ecclayout lpc32xx_nand_oob_16 = {
}
};
-#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD)
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CFG_SYS_NAND_ECCSIZE)
/*
@@ -162,7 +162,7 @@ static int lpc32xx_nand_dev_ready(struct mtd_info *mtd)
return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY;
}
-#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD)
/*
* Prepares DMA descriptors for NAND RD/WR operations
* If the size is < 256 Bytes then it is assumed to be
@@ -510,7 +510,7 @@ static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
*/
int board_nand_init(struct nand_chip *lpc32xx_chip)
{
-#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD)
int ret;
/* Acquire a channel for our use */
@@ -533,7 +533,7 @@ int board_nand_init(struct nand_chip *lpc32xx_chip)
lpc32xx_chip->read_byte = lpc32xx_read_byte;
lpc32xx_chip->write_byte = lpc32xx_write_byte;
-#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD)
/* Hardware ECC calculation is supported when DMA driver is selected */
lpc32xx_chip->ecc.mode = NAND_ECC_HW;
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 0545c23e268..1b65c6f6443 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -414,7 +414,7 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
{
struct nand_chip *chip = mtd_to_nand(mtd);
int ret = 0;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int res;
#endif
@@ -434,7 +434,7 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
nand_release_device(mtd);
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/* Mark block bad in BBT */
if (chip->bbt) {
res = nand_markbad_bbt(mtd, ofs);
@@ -488,7 +488,7 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
if (!chip->bbt)
return 0;
/* Return info from the table */
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
return nand_isreserved_bbt(mtd, ofs);
#else
return 0;
@@ -518,7 +518,7 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
return chip->block_bad(mtd, ofs);
/* Return info from the table */
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
return nand_isbad_bbt(mtd, ofs, allowbbt);
#else
return 0;
@@ -3729,7 +3729,7 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)
if (!chip->read_buf || chip->read_buf == nand_read_buf)
chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
if (!chip->scan_bbt)
chip->scan_bbt = nand_default_bbt;
#endif
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index a36e2a148cc..9c704c60e8e 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -1011,7 +1011,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/*
* omap_nand_switch_ecc - switch the ECC operation between different engines
* (h/w and s/w) and different algorithms (hamming and BCHx)
@@ -1072,7 +1072,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
err = nand_scan_tail(mtd);
return err;
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
/*
* Board-specific NAND initialization. The following members of the
diff --git a/drivers/mtd/nand/raw/sand_nand.c b/drivers/mtd/nand/raw/sand_nand.c
index 229d7b5b65a..3678bb8a41b 100644
--- a/drivers/mtd/nand/raw/sand_nand.c
+++ b/drivers/mtd/nand/raw/sand_nand.c
@@ -601,7 +601,7 @@ static int sand_nand_probe(struct udevice *dev)
}
nand = &chip->nand;
- nand->options = spl_in_proper() ? 0 : NAND_SKIP_BBTSCAN;
+ nand->options = not_xpl() ? 0 : NAND_SKIP_BBTSCAN;
nand->flash_node = np;
nand->dev_ready = sand_nand_dev_ready;
nand->cmdfunc = sand_nand_command;
@@ -680,7 +680,7 @@ void board_nand_init(void)
log_info("Failed to get sandbox NAND: %d\n", err);
}
-#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_NAND_INIT)
+#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_NAND_INIT)
void nand_deselect(void)
{
nand_chip->select_chip(nand_to_mtd(nand_chip), -1);
diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile
index 4dc417a5794..7f4a8514c17 100644
--- a/drivers/mtd/onenand/Makefile
+++ b/drivers/mtd/onenand/Makefile
@@ -3,7 +3,7 @@
# Copyright (C) 2005-2007 Samsung Electronics.
# Kyungmin Park <kyungmin.park@samsung.com>
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_CMD_ONENAND) := onenand_uboot.o onenand_base.o onenand_bbt.o
obj-$(CONFIG_SAMSUNG_ONENAND) += samsung.o
else
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 409395382f5..44e67cd913a 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -3,12 +3,12 @@
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-$(CONFIG_$(SPL_TPL_)DM_SPI_FLASH) += sf-uclass.o
+obj-$(CONFIG_$(PHASE_)DM_SPI_FLASH) += sf-uclass.o
spi-nor-y := sf_probe.o spi-nor-ids.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
-ifeq ($(CONFIG_$(SPL_TPL_)SPI_FLASH_TINY),y)
+ifeq ($(CONFIG_$(PHASE_)SPI_FLASH_TINY),y)
spi-nor-y += spi-nor-tiny.o
else
spi-nor-y += spi-nor-core.o
@@ -19,6 +19,6 @@ endif
obj-$(CONFIG_SPI_FLASH) += spi-nor.o
obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
-obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_MTD) += sf_mtd.o
+obj-$(CONFIG_$(PHASE_)SPI_FLASH_MTD) += sf_mtd.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
-obj-$(CONFIG_$(SPL_TPL_)BOOTDEV_SPI_FLASH) += sf_bootdev.o
+obj-$(CONFIG_$(PHASE_)BOOTDEV_SPI_FLASH) += sf_bootdev.o
diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
index a4d15bd64aa..102a9236826 100644
--- a/drivers/mtd/spi/sf-uclass.c
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -54,7 +54,7 @@ struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
struct udevice *bus;
char *str;
-#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(USE_TINY_PRINTF)
+#if defined(CONFIG_XPL_BUILD) && CONFIG_IS_ENABLED(USE_TINY_PRINTF)
str = "spi_flash";
#else
char name[30];
diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index 6db24189c8e..438eb3698d5 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -438,7 +438,7 @@ static int add_dataflash(struct udevice *dev, char *name, int nr_pages,
spi_flash->size = nr_pages * pagesize;
spi_flash->erase_size = pagesize;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
printf("SPI DataFlash: Detected %s with page size ", spi_flash->name);
print_size(spi_flash->page_size, ", erase size ");
print_size(spi_flash->erase_size, ", total ");
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 032e429d3fa..6f5395c7b9b 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -595,6 +595,24 @@ static int read_cr(struct spi_nor *nor)
}
#endif
+/**
+ * read_sr3() - Read status register 3 unique to newer Winbond flashes
+ * @nor: pointer to a 'struct spi_nor'
+ */
+static int read_sr3(struct spi_nor *nor)
+{
+ int ret;
+ u8 val;
+
+ ret = nor->read_reg(nor, SPINOR_OP_RDSR3, &val, 1);
+ if (ret < 0) {
+ dev_dbg(nor->dev, "error %d reading SR3\n", ret);
+ return ret;
+ }
+
+ return val;
+}
+
/*
* Write status register 1 byte
* Returns negative if error occurred.
@@ -605,6 +623,17 @@ static int write_sr(struct spi_nor *nor, u8 val)
return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
}
+/**
+ * write_sr3() - Write status register 3 unique to newer Winbond flashes
+ * @nor: pointer to a 'struct spi_nor'
+ * @val: value to be written into SR3
+ */
+static int write_sr3(struct spi_nor *nor, u8 val)
+{
+ nor->cmd_buf[0] = val;
+ return nor->write_reg(nor, SPINOR_OP_WRSR3, nor->cmd_buf, 1);
+}
+
/*
* Set write enable latch with Write Enable command.
* Returns negative if error occurred.
@@ -1096,7 +1125,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
while (len) {
schedule();
- if (!IS_ENABLED(CONFIG_SPL_BUILD) && ctrlc()) {
+ if (!IS_ENABLED(CONFIG_XPL_BUILD) && ctrlc()) {
addr_known = false;
ret = -EINTR;
goto erase_err;
@@ -3655,8 +3684,10 @@ static int s25fs_s_quad_enable(struct spi_nor *nor)
static int s25fs_s_erase_non_uniform(struct spi_nor *nor, loff_t addr)
{
+ u8 opcode = nor->addr_width == 4 ? SPINOR_OP_BE_4K_4B : SPINOR_OP_BE_4K;
+
/* Support 8 x 4KB sectors at bottom */
- return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, SZ_32K);
+ return spansion_erase_non_uniform(nor, addr, opcode, 0, SZ_32K);
}
static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info,
@@ -3710,12 +3741,24 @@ static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor,
static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor,
struct spi_nor_flash_parameter *params)
{
- /* READ_1_1_2 is not supported */
- params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2;
- /* READ_1_1_4 is not supported */
- params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4;
- /* PP_1_1_4 is not supported */
- params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4;
+ /*
+ * The S25FS064S(8MB) supports 1-1-2 and 1-1-4 commands, but params for
+ * read ops in SFDP are wrong. The other density parts do not support
+ * 1-1-2 and 1-1-4 commands.
+ */
+ if (params->size == SZ_8M) {
+ spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
+ 0, 8, SPINOR_OP_READ_1_1_2,
+ SNOR_PROTO_1_1_2);
+ spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
+ 0, 8, SPINOR_OP_READ_1_1_4,
+ SNOR_PROTO_1_1_4);
+ } else {
+ params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2;
+ params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4;
+ params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4;
+ }
+
/* Use volatile register to enable quad */
params->quad_enable = s25fs_s_quad_enable;
}
@@ -4225,6 +4268,24 @@ static int spi_nor_init(struct spi_nor *nor)
write_enable(nor);
write_sr(nor, 0);
spi_nor_wait_till_ready(nor);
+
+ /*
+ * Some Winbond SPI NORs have special SR3 register which is
+ * used among other things to control whether non-standard
+ * "Individual Block/Sector Write Protection" (WPS bit)
+ * locking scheme is activated. This non-standard locking
+ * scheme is not supported by either U-Boot or Linux SPI
+ * NOR stack so make sure it is disabled, otherwise the
+ * SPI NOR may appear locked for no obvious reason.
+ */
+ if (JEDEC_MFR(nor->info) == SNOR_MFR_WINBOND) {
+ err = read_sr3(nor);
+ if (err > 0 && err & SR3_WPS) {
+ write_enable(nor);
+ write_sr3(nor, err & ~SR3_WPS);
+ write_disable(nor);
+ }
+ }
}
if (nor->quad_enable) {
@@ -4556,7 +4617,7 @@ int spi_nor_scan(struct spi_nor *nor)
nor->erase_size = mtd->erasesize;
nor->sector_size = mtd->erasesize;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
printf("SF: Detected %s with page size ", nor->name);
print_size(nor->page_size, ", erase size ");
print_size(nor->erase_size, ", total ");
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 88709a52b3a..dfe92c3986e 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -258,7 +258,6 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) },
{ INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) },
- { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K) },
{ INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
@@ -339,9 +338,12 @@ const struct flash_info spi_nor_ids[] = {
*/
{ INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
- { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
+ { INFO6("s25fl256s0", 0x010219, 0x4d0080, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
+ { INFO6("s25fl256s1", 0x010219, 0x4d0180, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
+ { INFO6("s25fs064s", 0x010217, 0x4d0181, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
+ { INFO6("s25fs128s", 0x012018, 0x4d0181, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
+ { INFO6("s25fs256s", 0x010219, 0x4d0181, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
@@ -369,7 +371,7 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_CLSR) },
{ INFO6("s25hl02gt", 0x342a1c, 0x0f0090, 256 * 1024, 1024,
- SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
{ INFO6("s25hs512t", 0x342b1a, 0x0f0390, 256 * 1024, 256,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_CLSR) },
@@ -377,15 +379,16 @@ const struct flash_info spi_nor_ids[] = {
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_CLSR) },
{ INFO6("s25hs02gt", 0x342b1c, 0x0f0090, 256 * 1024, 1024,
- SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | NO_CHIP_ERASE) },
{ INFO6("s25fs256t", 0x342b19, 0x0f0890, 128 * 1024, 256,
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
#ifdef CONFIG_SPI_FLASH_S28HX_T
{ INFO("s28hl512t", 0x345a1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hl01gt", 0x345a1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) },
+ { INFO("s28hs256t", 0x345b19, 0, 256 * 1024, 128, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) },
{ INFO("s28hs01gt", 0x345b1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) },
- { INFO("s28hs02gt", 0x345b1c, 0, 256 * 1024, 1024, SPI_NOR_OCTAL_DTR_READ) },
+ { INFO("s28hs02gt", 0x345b1c, 0, 256 * 1024, 1024, SPI_NOR_OCTAL_DTR_READ | NO_CHIP_ERASE) },
#endif
#endif
#ifdef CONFIG_SPI_FLASH_SST /* SST */
@@ -430,11 +433,6 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("w25x05", 0xef3010, 0, 64 * 1024, 1, SECT_4K) },
{ INFO("w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K) },
{ INFO("w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K) },
- {
- INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
- },
{ INFO("w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K) },
{ INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) },
{ INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) },
@@ -442,7 +440,8 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{
INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64,
@@ -541,7 +540,11 @@ const struct flash_info spi_nor_ids[] = {
},
{ INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },
{ INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ {
+ INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
{ INFO("w25q32bv", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q128", 0xef4018, 0, 64 * 1024, 256,
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 11:09:49 +0000