diff options
Diffstat (limited to 'drivers/net/phy')
| -rw-r--r-- | drivers/net/phy/atheros.c | 53 | ||||
| -rw-r--r-- | drivers/net/phy/mv88e61xx.c | 61 |
2 files changed, 111 insertions, 3 deletions
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index e57c4120a3e..b34cdd3d87d 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -8,6 +8,15 @@ */ #include <phy.h> +#define AR803x_PHY_DEBUG_ADDR_REG 0x1d +#define AR803x_PHY_DEBUG_DATA_REG 0x1e + +#define AR803x_DEBUG_REG_5 0x5 +#define AR803x_RGMII_TX_CLK_DLY 0x100 + +#define AR803x_DEBUG_REG_0 0x0 +#define AR803x_RGMII_RX_CLK_DLY 0x8000 + static int ar8021_config(struct phy_device *phydev) { phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); @@ -17,6 +26,32 @@ static int ar8021_config(struct phy_device *phydev) return 0; } +static int ar8031_config(struct phy_device *phydev) +{ + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, + AR803x_DEBUG_REG_5); + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, + AR803x_RGMII_TX_CLK_DLY); + } + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, + AR803x_DEBUG_REG_0); + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, + AR803x_RGMII_RX_CLK_DLY); + } + + phydev->supported = phydev->drv->features; + + genphy_config_aneg(phydev); + genphy_restart_aneg(phydev); + + return 0; +} + static int ar8035_config(struct phy_device *phydev) { int regval; @@ -31,6 +66,22 @@ static int ar8035_config(struct phy_device *phydev) regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100)); + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || + (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { + /* select debug reg 5 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5); + /* enable tx delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100); + } + + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || + (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) { + /* select debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0); + /* enable rx delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000); + } + phydev->supported = phydev->drv->features; genphy_config_aneg(phydev); @@ -54,7 +105,7 @@ static struct phy_driver AR8031_driver = { .uid = 0x4dd074, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, - .config = ar8035_config, + .config = ar8031_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 74d56098b5c..a2fd1686fc3 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -40,7 +40,7 @@ #define PHY_AUTONEGOTIATE_TIMEOUT 5000 -#define PORT_COUNT 7 +#define PORT_COUNT 11 #define PORT_MASK ((1 << PORT_COUNT) - 1) /* Device addresses */ @@ -103,8 +103,16 @@ #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 #define PORT_REG_STATUS_CMODE_SGMII 0xa +#define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10) +#define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9) +#define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7) +#define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6) #define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5) #define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4) +#define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3) +#define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2) +#define PORT_REG_PHYS_CTRL_SPD1000 BIT(1) +#define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0)) #define PORT_REG_CTRL_PSTATE_SHIFT 0 #define PORT_REG_CTRL_PSTATE_WIDTH 2 @@ -166,7 +174,17 @@ #error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to #endif +/* + * These are ports without PHYs that may be wired directly + * to other serdes interfaces + */ +#ifndef CONFIG_MV88E61XX_FIXED_PORTS +#define CONFIG_MV88E61XX_FIXED_PORTS 0 +#endif + /* ID register values for different switch models */ +#define PORT_SWITCH_ID_6096 0x0980 +#define PORT_SWITCH_ID_6097 0x0990 #define PORT_SWITCH_ID_6172 0x1720 #define PORT_SWITCH_ID_6176 0x1760 #define PORT_SWITCH_ID_6240 0x2400 @@ -580,7 +598,7 @@ static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port) } static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port, - u8 mask) + u16 mask) { int val; @@ -791,6 +809,27 @@ static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy) return 0; } +static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) +{ + int val; + + val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); + if (val < 0) + return val; + + val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK | + PORT_REG_PHYS_CTRL_FC_VALUE); + val |= PORT_REG_PHYS_CTRL_PCS_AN_EN | + PORT_REG_PHYS_CTRL_PCS_AN_RST | + PORT_REG_PHYS_CTRL_FC_FORCE | + PORT_REG_PHYS_CTRL_DUPLEX_VALUE | + PORT_REG_PHYS_CTRL_DUPLEX_FORCE | + PORT_REG_PHYS_CTRL_SPD1000; + + return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, + val); +} + static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy) { int val; @@ -909,6 +948,12 @@ static int mv88e61xx_phy_config(struct phy_device *phydev) /* Return success if any PHY succeeds */ ret = 0; + } else if ((1 << i) & CONFIG_MV88E61XX_FIXED_PORTS) { + res = mv88e61xx_fixed_port_setup(phydev, i); + if (res < 0) { + printf("Error configuring port %i\n", i); + continue; + } } } @@ -974,9 +1019,21 @@ static struct phy_driver mv88e61xx_driver = { .shutdown = &genphy_shutdown, }; +static struct phy_driver mv88e609x_driver = { + .name = "Marvell MV88E609x", + .uid = 0x1410c89, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .probe = mv88e61xx_probe, + .config = mv88e61xx_phy_config, + .startup = mv88e61xx_phy_startup, + .shutdown = &genphy_shutdown, +}; + int phy_mv88e61xx_init(void) { phy_register(&mv88e61xx_driver); + phy_register(&mv88e609x_driver); return 0; } |