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-rw-r--r--drivers/net/Kconfig1
-rw-r--r--drivers/net/aspeed_mdio.c1
-rw-r--r--drivers/net/fec_mxc.c13
-rw-r--r--drivers/net/fm/eth.c6
-rw-r--r--drivers/net/ftgmac100.c89
-rw-r--r--drivers/net/ftgmac100.h17
-rw-r--r--drivers/net/phy/Kconfig1
-rw-r--r--drivers/net/zynq_gem.c9
8 files changed, 108 insertions, 29 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 6ed325517c0..e7d0ddfe25a 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -468,6 +468,7 @@ config FTMAC100
config FTGMAC100
bool "Ftgmac100 Ethernet Support"
select PHYLIB
+ depends on NET
help
This driver supports the Faraday's FTGMAC100 Gigabit SoC
Ethernet controller that can be found on Aspeed SoCs (which
diff --git a/drivers/net/aspeed_mdio.c b/drivers/net/aspeed_mdio.c
index f2e4392aa9a..2e1f3cdf11a 100644
--- a/drivers/net/aspeed_mdio.c
+++ b/drivers/net/aspeed_mdio.c
@@ -113,6 +113,7 @@ static int aspeed_mdio_probe(struct udevice *dev)
static const struct udevice_id aspeed_mdio_ids[] = {
{ .compatible = "aspeed,ast2600-mdio" },
+ { .compatible = "aspeed,ast2700-mdio" },
{ }
};
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 0a0d92bc2cd..d6d5cb52fdd 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -615,8 +615,7 @@ static int fecmxc_init(struct udevice *dev)
if (fec->xcv_type != SEVENWIRE)
miiphy_restart_aneg(dev);
#endif
- fec_open(dev);
- return 0;
+ return fec_open(dev);
}
/**
@@ -818,6 +817,9 @@ static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
return -ENOMEM;
}
+ if (!(readl(&fec->eth->ecntrl) & FEC_ECNTRL_ETHER_EN))
+ return 0;
+
/* Check if any critical events have happened */
ievent = readl(&fec->eth->ievent);
writel(ievent, &fec->eth->ievent);
@@ -1210,10 +1212,13 @@ static int fecmxc_set_ref_clk(struct clk *clk_ref, phy_interface_t interface)
else if (interface == PHY_INTERFACE_MODE_RGMII ||
interface == PHY_INTERFACE_MODE_RGMII_ID ||
interface == PHY_INTERFACE_MODE_RGMII_RXID ||
- interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ interface == PHY_INTERFACE_MODE_RGMII_TXID) {
freq = 125000000;
- else
+ if (is_imx93())
+ freq = freq << 1;
+ } else {
return -EINVAL;
+ }
ret = clk_set_rate(clk_ref, freq);
if (ret < 0)
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 19f3f0fef07..63fe4b2d33c 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -26,7 +26,8 @@
#include "fm.h"
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
+#if ((defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
+ !defined(CONFIG_BITBANGMII))
#define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
TBIANA_FULL_DUPLEX)
@@ -701,8 +702,11 @@ static int init_phy(struct fm_eth *fm_eth)
supported |= SUPPORTED_2500baseX_Full;
#endif
+#if (CONFIG_IS_ENABLED(MII) || CONFIG_IS_ENABLED(CMD_MII)) && \
+ !CONFIG_IS_ENABLED(BITBANGMII)
if (fm_eth->type == FM_ETH_1G_E)
dtsec_init_phy(fm_eth);
+#endif
#ifdef CONFIG_PHYLIB
#ifdef CONFIG_DM_MDIO
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 8781e50a48d..f5ea2e72d1b 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -26,6 +26,7 @@
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/printk.h>
+#include <linux/bitfield.h>
#include "ftgmac100.h"
@@ -57,6 +58,15 @@
enum ftgmac100_model {
FTGMAC100_MODEL_FARADAY,
FTGMAC100_MODEL_ASPEED,
+ FTGMAC100_MODEL_ASPEED_AST2700,
+};
+
+union ftgmac100_dma_addr {
+ dma_addr_t addr;
+ struct {
+ u32 lo;
+ u32 hi;
+ };
};
/**
@@ -96,6 +106,8 @@ struct ftgmac100_data {
/* End of RX/TX ring buffer bits. Depend on model */
u32 rxdes0_edorr_mask;
u32 txdes0_edotr_mask;
+
+ bool is_ast2700;
};
/*
@@ -222,7 +234,7 @@ static int ftgmac100_phy_init(struct udevice *dev)
struct phy_device *phydev;
int ret;
- if (IS_ENABLED(CONFIG_DM_MDIO))
+ if (IS_ENABLED(CONFIG_DM_MDIO) && priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
phydev = dm_eth_phy_connect(dev);
else
phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
@@ -320,8 +332,9 @@ static int ftgmac100_start(struct udevice *dev)
struct eth_pdata *plat = dev_get_plat(dev);
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100 *ftgmac100 = priv->iobase;
+ union ftgmac100_dma_addr dma_addr = {.hi = 0, .lo = 0};
struct phy_device *phydev = priv->phydev;
- unsigned int maccr;
+ unsigned int maccr, dblac, desc_size;
ulong start, end;
int ret;
int i;
@@ -341,6 +354,7 @@ static int ftgmac100_start(struct udevice *dev)
priv->rx_index = 0;
for (i = 0; i < PKTBUFSTX; i++) {
+ priv->txdes[i].txdes2 = 0;
priv->txdes[i].txdes3 = 0;
priv->txdes[i].txdes0 = 0;
}
@@ -351,7 +365,14 @@ static int ftgmac100_start(struct udevice *dev)
flush_dcache_range(start, end);
for (i = 0; i < PKTBUFSRX; i++) {
- priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
+ unsigned int ip_align = 0;
+
+ dma_addr.addr = (dma_addr_t)net_rx_packets[i];
+ priv->rxdes[i].rxdes2 = FIELD_PREP(FTGMAC100_RXDES2_RXBUF_BADR_HI, dma_addr.hi);
+ /* For IP alignment */
+ if ((dma_addr.lo & (PKTALIGN - 1)) == 0)
+ ip_align = 2;
+ priv->rxdes[i].rxdes3 = dma_addr.lo + ip_align;
priv->rxdes[i].rxdes0 = 0;
}
priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
@@ -361,10 +382,25 @@ static int ftgmac100_start(struct udevice *dev)
flush_dcache_range(start, end);
/* transmit ring */
- writel((u32)priv->txdes, &ftgmac100->txr_badr);
+ dma_addr.addr = (dma_addr_t)priv->txdes;
+ writel(dma_addr.lo, &ftgmac100->txr_badr);
+ writel(dma_addr.hi, &ftgmac100->txr_badr_hi);
/* receive ring */
- writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
+ dma_addr.addr = (dma_addr_t)priv->rxdes;
+ writel(dma_addr.lo, &ftgmac100->rxr_badr);
+ writel(dma_addr.hi, &ftgmac100->rxr_badr_hi);
+
+ /* Configure TX/RX decsriptor size
+ * This size is calculated based on cache line.
+ */
+ desc_size = ARCH_DMA_MINALIGN / FTGMAC100_DESC_UNIT;
+ /* The descriptor size is at least 2 descriptor units. */
+ if (desc_size < 2)
+ desc_size = 2;
+ dblac = readl(&ftgmac100->dblac) & ~GENMASK(19, 12);
+ dblac |= FTGMAC100_DBLAC_RXDES_SIZE(desc_size) | FTGMAC100_DBLAC_TXDES_SIZE(desc_size);
+ writel(dblac, &ftgmac100->dblac);
/* poll receive descriptor automatically */
writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
@@ -382,6 +418,10 @@ static int ftgmac100_start(struct udevice *dev)
FTGMAC100_MACCR_RX_RUNT |
FTGMAC100_MACCR_RX_BROADPKT;
+ if (priv->is_ast2700 && (priv->phydev->interface == PHY_INTERFACE_MODE_RMII ||
+ priv->phydev->interface == PHY_INTERFACE_MODE_NCSI))
+ maccr |= FTGMAC100_MACCR_RMII_ENABLE;
+
writel(maccr, &ftgmac100->maccr);
ret = phy_startup(phydev);
@@ -410,6 +450,14 @@ static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
ulong des_end = des_start +
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
+ /*
+ * Make sure there are no stale data in write-back over this area, which
+ * might get written into the memory while the ftgmac100 also writes
+ * into the same memory area.
+ */
+ flush_dcache_range((ulong)net_rx_packets[priv->rx_index],
+ (ulong)net_rx_packets[priv->rx_index] + PKTSIZE_ALIGN);
+
/* Release buffer to DMA and flush descriptor */
curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
flush_dcache_range(des_start, des_end);
@@ -431,9 +479,11 @@ static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
ulong des_end = des_start +
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
- ulong data_start = curr_des->rxdes3;
+ union ftgmac100_dma_addr data_start = { .lo = 0, .hi = 0 };
ulong data_end;
+ data_start.hi = FIELD_GET(FTGMAC100_RXDES2_RXBUF_BADR_HI, curr_des->rxdes2);
+ data_start.lo = curr_des->rxdes3;
invalidate_dcache_range(des_start, des_end);
if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
@@ -453,9 +503,9 @@ static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
__func__, priv->rx_index, rxlen);
/* Invalidate received data */
- data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
- invalidate_dcache_range(data_start, data_end);
- *packetp = (uchar *)data_start;
+ data_end = data_start.addr + roundup(rxlen, ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(data_start.addr, data_end);
+ *packetp = (uchar *)data_start.addr;
return rxlen;
}
@@ -481,6 +531,7 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length)
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100 *ftgmac100 = priv->iobase;
struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
+ union ftgmac100_dma_addr dma_addr;
ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
ulong des_end = des_start +
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
@@ -499,10 +550,12 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length)
length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
- curr_des->txdes3 = (unsigned int)packet;
+ dma_addr.addr = (dma_addr_t)packet;
+ curr_des->txdes2 = FIELD_PREP(FTGMAC100_TXDES2_TXBUF_BADR_HI, dma_addr.hi);
+ curr_des->txdes3 = dma_addr.lo;
/* Flush data to be sent */
- data_start = curr_des->txdes3;
+ data_start = (ulong)dma_addr.addr;
data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
flush_dcache_range(data_start, data_end);
@@ -565,6 +618,11 @@ static int ftgmac100_of_to_plat(struct udevice *dev)
if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
priv->rxdes0_edorr_mask = BIT(30);
priv->txdes0_edotr_mask = BIT(30);
+ priv->is_ast2700 = false;
+ } else if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED_AST2700) {
+ priv->rxdes0_edorr_mask = BIT(30);
+ priv->txdes0_edotr_mask = BIT(30);
+ priv->is_ast2700 = true;
} else {
priv->rxdes0_edorr_mask = BIT(15);
priv->txdes0_edotr_mask = BIT(15);
@@ -655,10 +713,11 @@ static const struct eth_ops ftgmac100_ops = {
};
static const struct udevice_id ftgmac100_ids[] = {
- { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
- { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
- { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED },
- { }
+ { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
+ { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
+ { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED },
+ { .compatible = "aspeed,ast2700-mac", .data = FTGMAC100_MODEL_ASPEED_AST2700 },
+ {}
};
U_BOOT_DRIVER(ftgmac100) = {
diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h
index f7874ae68b6..c38b57c9541 100644
--- a/drivers/net/ftgmac100.h
+++ b/drivers/net/ftgmac100.h
@@ -66,6 +66,13 @@ struct ftgmac100 {
unsigned int rx_runt; /* 0xc0 */
unsigned int rx_crcer_ftl; /* 0xc4 */
unsigned int rx_col_lost; /* 0xc8 */
+ unsigned int reserved[43]; /* 0xcc - 0x174 */
+ unsigned int txr_badr_lo; /* 0x178, defined in ast2700 */
+ unsigned int txr_badr_hi; /* 0x17c, defined in ast2700 */
+ unsigned int hptxr_badr_lo; /* 0x180, defined in ast2700 */
+ unsigned int hptxr_badr_hi; /* 0x184, defined in ast2700 */
+ unsigned int rxr_badr_lo; /* 0x188, defined in ast2700 */
+ unsigned int rxr_badr_hi; /* 0x18c, defined in ast2700 */
};
/*
@@ -111,6 +118,7 @@ struct ftgmac100 {
#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10)
#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12)
#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16)
+#define FTGMAC100_DESC_UNIT 8
#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20)
#define FTGMAC100_DBLAC_IFG_INC BIT(23)
@@ -157,6 +165,7 @@ struct ftgmac100 {
#define FTGMAC100_MACCR_RX_BROADPKT BIT(17)
#define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18)
#define FTGMAC100_MACCR_FAST_MODE BIT(19)
+#define FTGMAC100_MACCR_RMII_ENABLE BIT(20) /* defined in ast2700 */
#define FTGMAC100_MACCR_SW_RST BIT(31)
/*
@@ -183,7 +192,7 @@ struct ftgmac100_txdes {
unsigned int txdes1;
unsigned int txdes2; /* not used by HW */
unsigned int txdes3; /* TXBUF_BADR */
-} __aligned(16);
+} __aligned(ARCH_DMA_MINALIGN);
#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
#define FTGMAC100_TXDES0_EDOTR BIT(15)
@@ -201,6 +210,8 @@ struct ftgmac100_txdes {
#define FTGMAC100_TXDES1_TX2FIC BIT(30)
#define FTGMAC100_TXDES1_TXIC BIT(31)
+#define FTGMAC100_TXDES2_TXBUF_BADR_HI GENMASK(18, 16)
+
/*
* Receive descriptor, aligned to 16 bytes
*/
@@ -209,7 +220,7 @@ struct ftgmac100_rxdes {
unsigned int rxdes1;
unsigned int rxdes2; /* not used by HW */
unsigned int rxdes3; /* RXBUF_BADR */
-} __aligned(16);
+} __aligned(ARCH_DMA_MINALIGN);
#define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff)
#define FTGMAC100_RXDES0_EDORR BIT(15)
@@ -240,4 +251,6 @@ struct ftgmac100_rxdes {
#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26)
#define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27)
+#define FTGMAC100_RXDES2_RXBUF_BADR_HI GENMASK(18, 16)
+
#endif /* __FTGMAC100_H */
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 73064b2af68..a9efc509814 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -368,6 +368,7 @@ config PHY_FIXED
config PHY_NCSI
bool "NC-SI based PHY"
+ depends on NET
endif #PHYLIB
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index fe7d1084450..461805ae53f 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -228,7 +228,6 @@ struct zynq_gem_priv {
struct clk tx_clk;
struct clk pclk;
u32 max_speed;
- bool int_pcs;
bool dma_64bit;
u32 clk_en_info;
struct reset_ctl_bulk resets;
@@ -504,8 +503,7 @@ static int zynq_gem_init(struct udevice *dev)
* Set SGMII enable PCS selection only if internal PCS/PMA
* core is used and interface is SGMII.
*/
- if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
- priv->int_pcs) {
+ if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
ZYNQ_GEM_NWCFG_PCS_SEL;
}
@@ -529,8 +527,7 @@ static int zynq_gem_init(struct udevice *dev)
writel(nwcfg, &regs->nwcfg);
#ifdef CONFIG_ARM64
- if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
- priv->int_pcs) {
+ if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
/*
* Disable AN for fixed link configuration, enable otherwise.
* Must be written after PCS_SEL is set in nwconfig,
@@ -992,8 +989,6 @@ static int zynq_gem_of_to_plat(struct udevice *dev)
return -EINVAL;
priv->interface = pdata->phy_interface;
- priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
-
priv->clk_en_info = dev_get_driver_data(dev);
return 0;
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-13 10:18:51 +0000