diff options
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/Kconfig | 18 | ||||
| -rw-r--r-- | drivers/net/Makefile | 1 | ||||
| -rw-r--r-- | drivers/net/fec_mxc.c | 27 | ||||
| -rw-r--r-- | drivers/net/mdio_gpio.c | 313 | ||||
| -rw-r--r-- | drivers/net/mtk_eth.c | 175 | ||||
| -rw-r--r-- | drivers/net/mtk_eth.h | 26 | ||||
| -rw-r--r-- | drivers/net/phy/marvell.c | 3 | ||||
| -rw-r--r-- | drivers/net/phy/motorcomm.c | 183 | ||||
| -rw-r--r-- | drivers/net/rswitch.c | 238 |
9 files changed, 839 insertions, 145 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 576cd2d50ad..88ff025a37b 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -975,6 +975,18 @@ config MEDIATEK_ETH This Driver support MediaTek Ethernet GMAC Say Y to enable support for the MediaTek Ethernet GMAC. +if MEDIATEK_ETH + +config MTK_ETH_SGMII + bool + default y if ARCH_MEDIATEK && !TARGET_MT7623 + +config MTK_ETH_XGMII + bool + default y if TARGET_MT7987 || TARGET_MT7988 + +endif # MEDIATEK_ETH + config HIFEMAC_ETH bool "HiSilicon Fast Ethernet Controller" select DM_CLK @@ -1007,6 +1019,12 @@ config FSL_ENETC This driver supports the NXP ENETC Ethernet controller found on some of the NXP SoCs. +config MDIO_GPIO_BITBANG + bool "GPIO bitbanging MDIO driver" + depends on DM_MDIO && DM_GPIO + help + Driver for bitbanging MDIO + config MDIO_MUX_I2CREG bool "MDIO MUX accessed as a register over I2C" depends on DM_MDIO_MUX && DM_I2C diff --git a/drivers/net/Makefile b/drivers/net/Makefile index f5ab1f5dedf..e51a917933e 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_LITEETH) += liteeth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o +obj-$(CONFIG_MDIO_GPIO_BITBANG) += mdio_gpio.o obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o obj-$(CONFIG_MDIO_MUX_MESON_G12A) += mdio_mux_meson_g12a.o obj-$(CONFIG_MDIO_MUX_MESON_GXL) += mdio_mux_meson_gxl.o diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index d6d5cb52fdd..54b08482b91 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -160,7 +160,7 @@ static int fec_get_clk_rate(void *udev, int idx) } } -static void fec_mii_setspeed(struct ethernet_regs *eth) +static void fec_mii_setspeed(struct udevice *dev, struct ethernet_regs *eth) { /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock @@ -182,7 +182,7 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) u32 hold; int ret; - ret = fec_get_clk_rate(NULL, 0); + ret = fec_get_clk_rate(dev, 0); if (ret < 0) { printf("Can't find FEC0 clk rate: %d\n", ret); return; @@ -581,7 +581,7 @@ static int fecmxc_init(struct udevice *dev) fec_reg_setup(fec); if (fec->xcv_type != SEVENWIRE) - fec_mii_setspeed(fec->bus->priv); + fec_mii_setspeed(dev, fec->bus->priv); /* Set Opcode/Pause Duration Register */ writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ @@ -996,7 +996,7 @@ static void fec_free_descs(struct fec_priv *fec) free(fec->tbd_base); } -struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) +struct mii_dev *fec_get_miibus(struct udevice *dev, ulong base_addr, int dev_id) { struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; struct mii_dev *bus; @@ -1018,7 +1018,7 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) free(bus); return NULL; } - fec_mii_setspeed(eth); + fec_mii_setspeed(dev, eth); return bus; } @@ -1162,6 +1162,7 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) { struct phy_device *phydev = NULL; int addr; + int ret; addr = device_get_phy_addr(priv, dev); #ifdef CFG_FEC_MXC_PHYADDR @@ -1175,6 +1176,17 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) if (!phydev) return -ENODEV; + switch (priv->interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RMII: + ret = phy_set_supported(phydev, SPEED_100); + if (ret) + return ret; + break; + default: + break; + } + priv->phydev = phydev; priv->phydev->node = priv->phy_of_node; phy_config(phydev); @@ -1354,10 +1366,10 @@ static int fecmxc_probe(struct udevice *dev) if (!bus) { dm_mii_bus = false; #ifdef CONFIG_FEC_MXC_MDIO_BASE - bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, + bus = fec_get_miibus(dev, (ulong)CONFIG_FEC_MXC_MDIO_BASE, dev_seq(dev)); #else - bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev)); + bus = fec_get_miibus(dev, (ulong)priv->eth, dev_seq(dev)); #endif } if (!bus) { @@ -1491,4 +1503,5 @@ U_BOOT_DRIVER(fecmxc_gem) = { .ops = &fecmxc_ops, .priv_auto = sizeof(struct fec_priv), .plat_auto = sizeof(struct eth_pdata), + .flags = DM_FLAG_ACTIVE_DMA, }; diff --git a/drivers/net/mdio_gpio.c b/drivers/net/mdio_gpio.c new file mode 100644 index 00000000000..a2a41f95190 --- /dev/null +++ b/drivers/net/mdio_gpio.c @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * GPIO based MDIO bitbang driver. + * + * Copyright 2024 Markus Gothe <markus.gothe@genexis.eu> + * + * This file is based on the Linux kernel drivers drivers/net/phy/mdio-gpio.c + * and drivers/net/phy/mdio-bitbang.c which have the following copyrights: + * + * Copyright (c) 2008 CSE Semaphore Belgium. + * by Laurent Pinchart <laurentp@cse-semaphore.com> + * + * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt> + * + * Author: Scott Wood <scottwood@freescale.com> + * Copyright (c) 2007 Freescale Semiconductor + * + * Copyright (c) 2003 Intracom S.A. + * by Pantelis Antoniou <panto@intracom.gr> + * + * 2005 (c) MontaVista Software, Inc. + * Vitaly Bordug <vbordug@ru.mvista.com> + */ + +#include <dm.h> +#include <log.h> +#include <miiphy.h> +#include <asm/gpio.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/mdio.h> + +#define MDIO_READ 2 +#define MDIO_WRITE 1 + +#define MDIO_C45 BIT(15) +#define MDIO_C45_ADDR (MDIO_C45 | 0) +#define MDIO_C45_READ (MDIO_C45 | 3) +#define MDIO_C45_WRITE (MDIO_C45 | 1) + +/* Minimum MDC period is 400 ns, plus some margin for error. MDIO_DELAY + * is done twice per period. + */ +#define MDIO_DELAY 250 + +/* The PHY may take up to 300 ns to produce data, plus some margin + * for error. + */ +#define MDIO_READ_DELAY 350 + +#define MDIO_GPIO_MDC 0 +#define MDIO_GPIO_MDIO 1 +#define MDIO_GPIO_MDO 2 + +struct mdio_gpio_priv { + struct gpio_desc mdc, mdio, mdo; +}; + +static void mdio_dir(struct udevice *mdio_dev, int dir) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + if (dm_gpio_is_valid(&priv->mdo)) { + /* Separate output pin. Always set its value to high + * when changing direction. If direction is input, + * assume the pin serves as pull-up. If direction is + * output, the default value is high. + */ + dm_gpio_set_value(&priv->mdo, 1); + return; + } + + if (dir) + dm_gpio_set_dir_flags(&priv->mdio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + else + dm_gpio_set_dir_flags(&priv->mdio, GPIOD_IS_IN); +} + +static int mdio_get(struct udevice *mdio_dev) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + return dm_gpio_get_value(&priv->mdio); +} + +static void mdio_set(struct udevice *mdio_dev, int what) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + if (dm_gpio_is_valid(&priv->mdo)) + dm_gpio_set_value(&priv->mdo, what); + else + dm_gpio_set_value(&priv->mdio, what); +} + +static void mdc_set(struct udevice *mdio_dev, int what) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + + dm_gpio_set_value(&priv->mdc, what); +} + +/* MDIO must already be configured as output. */ +static void mdio_gpio_send_bit(struct udevice *mdio_dev, int val) +{ + mdio_set(mdio_dev, val); + ndelay(MDIO_DELAY); + mdc_set(mdio_dev, 1); + ndelay(MDIO_DELAY); + mdc_set(mdio_dev, 0); +} + +/* MDIO must already be configured as input. */ +static int mdio_gpio_get_bit(struct udevice *mdio_dev) +{ + ndelay(MDIO_DELAY); + mdc_set(mdio_dev, 1); + ndelay(MDIO_READ_DELAY); + mdc_set(mdio_dev, 0); + + return mdio_get(mdio_dev); +} + +/* MDIO must already be configured as output. */ +static void mdio_gpio_send_num(struct udevice *mdio_dev, u16 val, int bits) +{ + int i; + + for (i = bits - 1; i >= 0; i--) + mdio_gpio_send_bit(mdio_dev, (val >> i) & 1); +} + +/* MDIO must already be configured as input. */ +static u16 mdio_gpio_get_num(struct udevice *mdio_dev, int bits) +{ + int i; + u16 ret = 0; + + for (i = bits - 1; i >= 0; i--) { + ret <<= 1; + ret |= mdio_gpio_get_bit(mdio_dev); + } + + return ret; +} + +/* Utility to send the preamble, address, and + * register (common to read and write). + */ +static void mdio_gpio_cmd(struct udevice *mdio_dev, int op, u8 phy, u8 reg) +{ + int i; + + mdio_dir(mdio_dev, 1); + + /* + * Send a 32 bit preamble ('1's) with an extra '1' bit for good + * measure. The IEEE spec says this is a PHY optional + * requirement. The AMD 79C874 requires one after power up and + * one after a MII communications error. This means that we are + * doing more preambles than we need, but it is safer and will be + * much more robust. + */ + for (i = 0; i < 32; i++) + mdio_gpio_send_bit(mdio_dev, 1); + + /* + * Send the start bit (01) and the read opcode (10) or write (01). + * Clause 45 operation uses 00 for the start and 11, 10 for + * read/write. + */ + mdio_gpio_send_bit(mdio_dev, 0); + if (op & MDIO_C45) + mdio_gpio_send_bit(mdio_dev, 0); + else + mdio_gpio_send_bit(mdio_dev, 1); + mdio_gpio_send_bit(mdio_dev, (op >> 1) & 1); + mdio_gpio_send_bit(mdio_dev, (op >> 0) & 1); + + mdio_gpio_send_num(mdio_dev, phy, 5); + mdio_gpio_send_num(mdio_dev, reg, 5); +} + +/* + * In clause 45 mode all commands are prefixed by MDIO_ADDR to specify the + * lower 16 bits of the 21 bit address. This transfer is done identically to a + * MDIO_WRITE except for a different code. To enable clause 45 mode or + * MII_ADDR_C45 into the address. Theoretically clause 45 and normal devices + * can exist on the same bus. Normal devices should ignore the MDIO_ADDR + * phase. + */ +static int mdio_gpio_cmd_addr(struct udevice *mdio_dev, int phy, u32 dev_addr, u32 reg) +{ + mdio_gpio_cmd(mdio_dev, MDIO_C45_ADDR, phy, dev_addr); + + /* send the turnaround (10) */ + mdio_gpio_send_bit(mdio_dev, 1); + mdio_gpio_send_bit(mdio_dev, 0); + + mdio_gpio_send_num(mdio_dev, reg, 16); + + mdio_dir(mdio_dev, 0); + mdio_gpio_get_bit(mdio_dev); + + return dev_addr; +} + +static int mdio_gpio_read(struct udevice *mdio_dev, int addr, int devad, int reg) +{ + int ret, i; + + if (devad != MDIO_DEVAD_NONE) { + reg = mdio_gpio_cmd_addr(mdio_dev, addr, devad, reg); + mdio_gpio_cmd(mdio_dev, MDIO_C45_READ, addr, reg); + } else { + mdio_gpio_cmd(mdio_dev, MDIO_READ, addr, reg); + } + + mdio_dir(mdio_dev, 0); + + /* check the turnaround bit: the PHY should be driving it to zero. + */ + if (mdio_gpio_get_bit(mdio_dev) != 0) { + /* PHY didn't drive TA low -- flush any bits it + * may be trying to send. + */ + for (i = 0; i < 32; i++) + mdio_gpio_get_bit(mdio_dev); + + return 0xffff; + } + + ret = mdio_gpio_get_num(mdio_dev, 16); + mdio_gpio_get_bit(mdio_dev); + + return ret; +} + +static int mdio_gpio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val) +{ + if (devad != MDIO_DEVAD_NONE) { + reg = mdio_gpio_cmd_addr(mdio_dev, addr, devad, reg); + mdio_gpio_cmd(mdio_dev, MDIO_C45_WRITE, addr, reg); + } else { + mdio_gpio_cmd(mdio_dev, MDIO_WRITE, addr, reg); + } + + /* send the turnaround (10) */ + mdio_gpio_send_bit(mdio_dev, 1); + mdio_gpio_send_bit(mdio_dev, 0); + + mdio_gpio_send_num(mdio_dev, val, 16); + + mdio_dir(mdio_dev, 0); + mdio_gpio_get_bit(mdio_dev); + + return 0; +} + +static const struct mdio_ops mdio_gpio_ops = { + .read = mdio_gpio_read, + .write = mdio_gpio_write, + .reset = NULL, +}; + +/* + * Name the device, we use the device tree node name. + * This can be overwritten by MDIO class code if device-name property is + * present. + */ +static int mdio_gpio_bind(struct udevice *mdio_dev) +{ + if (ofnode_valid(dev_ofnode(mdio_dev))) + device_set_name(mdio_dev, ofnode_get_name(dev_ofnode(mdio_dev))); + + return 0; +} + +static int mdio_gpio_probe(struct udevice *mdio_dev) +{ + struct mdio_gpio_priv *priv = dev_get_priv(mdio_dev); + int ret = 0; + + ret = gpio_request_by_name(mdio_dev, "gpios", MDIO_GPIO_MDC, &priv->mdc, GPIOD_IS_OUT); + if (ret) + return ret; + + ret = gpio_request_by_name(mdio_dev, "gpios", MDIO_GPIO_MDIO, &priv->mdio, GPIOD_IS_IN); + if (ret) + return ret; + + ret = gpio_request_by_name(mdio_dev, "gpios", MDIO_GPIO_MDO, &priv->mdo, GPIOD_IS_OUT); + if (ret && ret != -ENOENT) + return ret; + + return 0; +} + +static const struct udevice_id mdio_gpio_ids[] = { + { .compatible = "virtual,mdio-gpio" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(gpio_mdio) = { + .name = "gpio_mdio", + .id = UCLASS_MDIO, + .of_match = mdio_gpio_ids, + .bind = mdio_gpio_bind, + .probe = mdio_gpio_probe, + .ops = &mdio_gpio_ops, + .plat_auto = sizeof(struct mdio_perdev_priv), + .priv_auto = sizeof(struct mdio_gpio_priv), +}; diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 5098afef8a8..454caa3cd3a 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -29,8 +29,8 @@ #include "mtk_eth.h" -#define NUM_TX_DESC 24 -#define NUM_RX_DESC 24 +#define NUM_TX_DESC 32 +#define NUM_RX_DESC 32 #define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN) #define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN) #define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE) @@ -835,8 +835,8 @@ static int mt7531_port_sgmii_init(struct mtk_eth_priv *priv, } /* Set SGMII GEN2 speed(2.5G) */ - mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), - SGMSYS_SPEED_2500, SGMSYS_SPEED_2500); + mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK, + FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); /* Disable SGMII AN */ mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port), @@ -1246,6 +1246,7 @@ static int mtk_phy_start(struct mtk_eth_priv *priv) if (!priv->force_mode) { if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || priv->phy_interface == PHY_INTERFACE_MODE_XGMII) mtk_xphy_link_adjust(priv); else @@ -1281,8 +1282,7 @@ static int mtk_phy_probe(struct udevice *dev) static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) { /* Set SGMII GEN1 speed(1G) */ - clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, - SGMSYS_SPEED_2500, 0); + clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK); /* Enable SGMII AN */ setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, @@ -1305,8 +1305,9 @@ static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) static void mtk_sgmii_force_init(struct mtk_eth_priv *priv) { /* Set SGMII GEN2 speed(2.5G) */ - setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, - SGMSYS_SPEED_2500); + clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, + SGMSYS_SPEED_MASK, + FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); /* Disable SGMII AN */ clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, @@ -1425,6 +1426,71 @@ static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv) udelay(400); } +static void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth_priv *priv) +{ + regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6C); + regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); + regmap_write(priv->usxgmii_regmap, 0x80C, 0xB0000000); + ndelay(1020); + regmap_write(priv->usxgmii_regmap, 0x80C, 0x90000000); + ndelay(1020); + + regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); + regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); + regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); + regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); + regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); + regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); + regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); + regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); + regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); + regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); + regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); + regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); + regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); + regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); + regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); + regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); + regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); + regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); + regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); + regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); + regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); + regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); + regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); + ndelay(1020); + regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); + regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); + regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); + regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); + regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); + regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); + regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); + regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x47684100); + regmap_write(priv->xfi_pextp_regmap, 0x3050, 0x00000000); + regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x00000000); + regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); + if (priv->gmac_id == 2) + regmap_write(priv->xfi_pextp_regmap, 0xA008, 0x0007B400); + regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); + regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); + udelay(150); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); + ndelay(1020); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); + udelay(15); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); + ndelay(1020); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); + udelay(100); + regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); + regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); + regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); + udelay(400); +} + static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) { mtk_xfi_pll_enable(priv); @@ -1432,11 +1498,23 @@ static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) mtk_usxgmii_setup_phya_an_10000(priv); } -static void mtk_mac_init(struct mtk_eth_priv *priv) +static void mtk_10gbaser_init(struct mtk_eth_priv *priv) +{ + mtk_xfi_pll_enable(priv); + mtk_usxgmii_reset(priv); + mtk_usxgmii_setup_phya_force_10000(priv); +} + +static int mtk_mac_init(struct mtk_eth_priv *priv) { - int i, ge_mode = 0; + int i, sgmii_sel_mask = 0, ge_mode = 0; u32 mcr; + if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7629_GMAC2)) { + mtk_infra_rmw(priv, MT7629_INFRA_MISC2_REG, + INFRA_MISC2_BONDING_OPTION, priv->gmac_id); + } + switch (priv->phy_interface) { case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII: @@ -1444,18 +1522,28 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) break; case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_2500BASEX: + if (!IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { + printf("Error: SGMII is not supported on this platform\n"); + return -ENOTSUPP; + } + if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) { mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK, SGMII_QPHY_SEL); } - ge_mode = GE_MODE_RGMII; - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M, - SYSCFG0_SGMII_SEL(priv->gmac_id)); + if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII)) + sgmii_sel_mask = SYSCFG1_SGMII_SEL_M; + + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask, + SYSCFG1_SGMII_SEL(priv->gmac_id)); + if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) mtk_sgmii_an_init(priv); else mtk_sgmii_force_init(priv); + + ge_mode = GE_MODE_RGMII; break; case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: @@ -1469,9 +1557,9 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) } /* set the gmac to the right mode */ - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, - SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), - ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id)); + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, + SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), + ge_mode << SYSCFG1_GE_MODE_S(priv->gmac_id)); if (priv->force_mode) { mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | @@ -1512,26 +1600,37 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) RX_RST | RXC_DQSISEL); mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0); } + + return 0; } -static void mtk_xmac_init(struct mtk_eth_priv *priv) +static int mtk_xmac_init(struct mtk_eth_priv *priv) { u32 force_link = 0; + if (!IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { + printf("Error: 10Gb interface is not supported on this platform\n"); + return -ENOTSUPP; + } + switch (priv->phy_interface) { case PHY_INTERFACE_MODE_USXGMII: mtk_usxgmii_an_init(priv); break; + case PHY_INTERFACE_MODE_10GBASER: + mtk_10gbaser_init(priv); + break; default: break; } /* Set GMAC to the correct mode */ - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, - SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, + SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), 0); - if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII && + if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && priv->gmac_id == 1) { mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX, NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL); @@ -1546,6 +1645,8 @@ static void mtk_xmac_init(struct mtk_eth_priv *priv) /* Force GMAC link down */ mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE); + + return 0; } static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) @@ -1661,10 +1762,16 @@ static int mtk_eth_start(struct udevice *dev) if (priv->sw == SW_MT7988 && priv->gmac_id == 0) { mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_BRIDGE_TO_CPU); - } - mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, - GDMA_CPU_BRIDGE_EN); + mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, + GDMA_CPU_BRIDGE_EN); + } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || + priv->phy_interface == PHY_INTERFACE_MODE_XGMII) && + priv->gmac_id != 0) { + mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, + GDMA_CPU_BRIDGE_EN); + } } udelay(500); @@ -1790,6 +1897,9 @@ static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length) rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; + invalidate_dcache_range((ulong)rxd->rxd1, + (ulong)rxd->rxd1 + PKTSIZE_ALIGN); + if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); @@ -1833,10 +1943,14 @@ static int mtk_eth_probe(struct udevice *dev) /* Set MAC mode */ if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || priv->phy_interface == PHY_INTERFACE_MODE_XGMII) - mtk_xmac_init(priv); + ret = mtk_xmac_init(priv); else - mtk_mac_init(priv); + ret = mtk_mac_init(priv); + + if (ret) + return ret; /* Probe phy if switch is not specified */ if (priv->sw == SW_NONE) @@ -1944,8 +2058,9 @@ static int mtk_eth_of_to_plat(struct udevice *dev) } } - if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII || - priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { + if ((priv->phy_interface == PHY_INTERFACE_MODE_SGMII || + priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) && + IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { /* get corresponding sgmii phandle */ ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys", NULL, 0, 0, &args); @@ -1967,7 +2082,9 @@ static int mtk_eth_of_to_plat(struct udevice *dev) /* Upstream linux use mediatek,pnswap instead of pn_swap */ priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") || ofnode_read_bool(args.node, "mediatek,pnswap"); - } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) { + } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && + IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { /* get corresponding usxgmii phandle */ ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", NULL, 0, 0, &args); @@ -2096,6 +2213,7 @@ static const struct mtk_soc_data mt7981_data = { }; static const struct mtk_soc_data mt7629_data = { + .caps = MT7629_CAPS, .ana_rgc3 = 0x128, .gdma_count = 2, .pdma_base = PDMA_V1_BASE, @@ -2112,6 +2230,7 @@ static const struct mtk_soc_data mt7623_data = { }; static const struct mtk_soc_data mt7622_data = { + .caps = MT7622_CAPS, .ana_rgc3 = 0x2028, .gdma_count = 2, .pdma_base = PDMA_V1_BASE, diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h index fd31c782c7f..1aa037907c5 100644 --- a/drivers/net/mtk_eth.h +++ b/drivers/net/mtk_eth.h @@ -23,6 +23,8 @@ enum mkt_eth_capabilities { /* PATH BITS */ MTK_ETH_PATH_GMAC1_TRGMII_BIT, MTK_ETH_PATH_GMAC2_SGMII_BIT, + MTK_ETH_PATH_MT7622_SGMII_BIT, + MTK_ETH_PATH_MT7629_GMAC2_BIT, }; #define MTK_TRGMII BIT(MTK_TRGMII_BIT) @@ -36,6 +38,8 @@ enum mkt_eth_capabilities { #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) +#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) +#define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT) #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) @@ -45,8 +49,12 @@ enum mkt_eth_capabilities { #define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) +#define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII) + #define MT7623_CAPS (MTK_GMAC1_TRGMII) +#define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA) + #define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) #define MT7986_CAPS (MTK_NETSYS_V2) @@ -65,11 +73,11 @@ enum mkt_eth_capabilities { /* Ethernet subsystem registers */ -#define ETHSYS_SYSCFG0_REG 0x14 -#define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2)) -#define SYSCFG0_GE_MODE_M 0x3 -#define SYSCFG0_SGMII_SEL_M (0x3 << 8) -#define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8)) +#define ETHSYS_SYSCFG1_REG 0x14 +#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) +#define SYSCFG1_GE_MODE_M 0x3 +#define SYSCFG1_SGMII_SEL_M GENMASK(9, 8) +#define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac)) #define ETHSYS_CLKCFG0_REG 0x2c #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) @@ -84,7 +92,10 @@ enum mkt_eth_capabilities { #define QPHY_SEL_MASK 0x3 #define SGMII_QPHY_SEL 0x2 -/* SYSCFG0_GE_MODE: GE Modes */ +#define MT7629_INFRA_MISC2_REG 0x70c +#define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0) + +/* SYSCFG1_GE_MODE: GE Modes */ #define GE_MODE_RGMII 0 #define GE_MODE_MII 1 #define GE_MODE_MII_PHY 2 @@ -108,7 +119,8 @@ enum mkt_eth_capabilities { #define SGMSYS_GEN2_SPEED 0x2028 #define SGMSYS_GEN2_SPEED_V2 0x128 -#define SGMSYS_SPEED_2500 BIT(2) +#define SGMSYS_SPEED_MASK GENMASK(3, 2) +#define SGMSYS_SPEED_2500 1 /* USXGMII subsystem config registers */ /* Register to control USXGMII XFI PLL digital */ diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index b0a0b7fcb38..08608a99b9d 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -461,8 +461,7 @@ static int m88e151x_config(struct phy_device *phydev) reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR); reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY; - if (phydev->interface == PHY_INTERFACE_MODE_RGMII || - phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) reg |= MIIM_88E151x_RGMII_RXTX_DELAY; else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) reg |= MIIM_88E151x_RGMII_RX_DELAY; diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 4d67203ee70..e1630e1c229 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Motorcomm 8531 PHY driver. + * Motorcomm YT8511/YT8531/YT8531S/YT8821/YT8521S PHY driver. * * Copyright (C) 2023 StarFive Technology Co., Ltd. + * Copyright (C) 2024 Motorcomm Electronic Technology Co., Ltd. */ #include <config.h> @@ -13,6 +14,8 @@ #define PHY_ID_YT8511 0x0000010a #define PHY_ID_YT8531 0x4f51e91b #define PHY_ID_YT8821 0x4f51ea19 +#define PHY_ID_YT8531S 0x4f51e91a +#define PHY_ID_YT8521S 0x0000011a #define PHY_ID_MASK GENMASK(31, 0) /* Extended Register's Address Offset Register */ @@ -33,6 +36,17 @@ #define YTPHY_DTS_OUTPUT_CLK_25M 25000000 #define YTPHY_DTS_OUTPUT_CLK_125M 125000000 +#define YT8521S_SCR_SYNCE_ENABLE BIT(5) +/* 1b0 output 25m clock *default* + * 1b1 output 125m clock + */ +#define YT8521S_SCR_CLK_FRE_SEL_125M BIT(3) +#define YT8521S_SCR_CLK_SRC_MASK GENMASK(2, 1) +#define YT8521S_SCR_CLK_SRC_PLL_125M 0 +#define YT8521S_SCR_CLK_SRC_UTP_RX 1 +#define YT8521S_SCR_CLK_SRC_SDS_RX 2 +#define YT8521S_SCR_CLK_SRC_REF_25M 3 + #define YT8511_EXT_CLK_GATE 0x0c #define YT8511_EXT_DELAY_DRIVE 0x0d #define YT8511_EXT_SLEEP_CTRL 0x27 @@ -1114,6 +1128,151 @@ static int yt8821_startup(struct phy_device *phydev) return 0; } +static int yt8521s_config(struct phy_device *phydev) +{ + struct ytphy_plat_priv *priv = phydev->priv; + u16 mask, val; + int ret; + + ret = genphy_config_aneg(phydev); + if (ret < 0) + return ret; + + ytphy_dt_parse(phydev); + switch (priv->clk_out_frequency) { + case YTPHY_DTS_OUTPUT_CLK_DIS: + mask = YT8521S_SCR_SYNCE_ENABLE; + val = 0; + break; + case YTPHY_DTS_OUTPUT_CLK_25M: + mask = YT8521S_SCR_SYNCE_ENABLE | YT8521S_SCR_CLK_SRC_MASK | + YT8521S_SCR_CLK_FRE_SEL_125M; + val = YT8521S_SCR_SYNCE_ENABLE | + FIELD_PREP(YT8521S_SCR_CLK_SRC_MASK, + YT8521S_SCR_CLK_SRC_REF_25M); + break; + case YTPHY_DTS_OUTPUT_CLK_125M: + mask = YT8521S_SCR_SYNCE_ENABLE | YT8521S_SCR_CLK_SRC_MASK | + YT8521S_SCR_CLK_FRE_SEL_125M; + val = YT8521S_SCR_SYNCE_ENABLE | YT8521S_SCR_CLK_FRE_SEL_125M | + FIELD_PREP(YT8521S_SCR_CLK_SRC_MASK, + YT8521S_SCR_CLK_SRC_PLL_125M); + break; + default: + pr_warn("Freq err:%u\n", priv->clk_out_frequency); + return -EINVAL; + } + + ret = ytphy_modify_ext(phydev, YTPHY_SYNCE_CFG_REG, mask, + val); + if (ret < 0) + return ret; + + ret = ytphy_rgmii_clk_delay_config(phydev); + if (ret < 0) + return ret; + + if (priv->flag & AUTO_SLEEP_DISABLED) { + /* disable auto sleep */ + ret = ytphy_modify_ext(phydev, + YT8531_EXTREG_SLEEP_CONTROL1_REG, + YT8531_ESC1R_SLEEP_SW, 0); + if (ret < 0) + return ret; + } + + if (priv->flag & KEEP_PLL_ENABLED) { + /* enable RXC clock when no wire plug */ + ret = ytphy_modify_ext(phydev, + YT8531_CLOCK_GATING_REG, + YT8531_CGR_RX_CLK_EN, 0); + if (ret < 0) + return ret; + } + + return 0; +} + +static int yt8531s_config(struct phy_device *phydev) +{ + struct ytphy_plat_priv *priv = phydev->priv; + u16 mask, val; + int ret; + + ret = genphy_config_aneg(phydev); + if (ret < 0) + return ret; + + ytphy_dt_parse(phydev); + switch (priv->clk_out_frequency) { + case YTPHY_DTS_OUTPUT_CLK_DIS: + mask = YT8531_SCR_SYNCE_ENABLE; + val = 0; + break; + case YTPHY_DTS_OUTPUT_CLK_25M: + mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | + YT8531_SCR_CLK_FRE_SEL_125M; + val = YT8531_SCR_SYNCE_ENABLE | + FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, + YT8531_SCR_CLK_SRC_REF_25M); + break; + case YTPHY_DTS_OUTPUT_CLK_125M: + mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | + YT8531_SCR_CLK_FRE_SEL_125M; + val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M | + FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, + YT8531_SCR_CLK_SRC_PLL_125M); + break; + default: + pr_warn("Freq err:%u\n", priv->clk_out_frequency); + return -EINVAL; + } + + ret = ytphy_modify_ext(phydev, YTPHY_SYNCE_CFG_REG, mask, + val); + if (ret < 0) + return ret; + + ret = ytphy_rgmii_clk_delay_config(phydev); + if (ret < 0) + return ret; + + if (priv->flag & AUTO_SLEEP_DISABLED) { + /* disable auto sleep */ + ret = ytphy_modify_ext(phydev, + YT8531_EXTREG_SLEEP_CONTROL1_REG, + YT8531_ESC1R_SLEEP_SW, 0); + if (ret < 0) + return ret; + } + + if (priv->flag & KEEP_PLL_ENABLED) { + /* enable RXC clock when no wire plug */ + ret = ytphy_modify_ext(phydev, + YT8531_CLOCK_GATING_REG, + YT8531_CGR_RX_CLK_EN, 0); + if (ret < 0) + return ret; + } + + return 0; +} + +static int yt8531s_startup(struct phy_device *phydev) +{ + int ret; + + ret = genphy_update_link(phydev); + if (ret) + return ret; + + ret = yt8531_parse_status(phydev); + if (ret) + return ret; + + return 0; +} + U_BOOT_PHY_DRIVER(motorcomm8511) = { .name = "YT8511 Gigabit Ethernet", .uid = PHY_ID_YT8511, @@ -1145,3 +1304,25 @@ U_BOOT_PHY_DRIVER(motorcomm8821) = { .startup = &yt8821_startup, .shutdown = &genphy_shutdown, }; + +U_BOOT_PHY_DRIVER(motorcomm8531S) = { + .name = "YT8531S Gigabit Ethernet Transceiver", + .uid = PHY_ID_YT8531S, + .mask = PHY_ID_MASK, + .features = PHY_GBIT_FEATURES, + .probe = &yt8531_probe, + .config = &yt8531s_config, + .startup = &yt8531s_startup, + .shutdown = &genphy_shutdown, +}; + +U_BOOT_PHY_DRIVER(motorcomm8521S) = { + .name = "YT8521S Gigabit Ethernet Transceiver", + .uid = PHY_ID_YT8521S, + .mask = PHY_ID_MASK, + .features = PHY_GBIT_FEATURES, + .probe = &yt8531_probe, + .config = &yt8521s_config, + .startup = &yt8531s_startup, + .shutdown = &genphy_shutdown, +}; diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index 57eff748c90..62d3f39f071 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -36,95 +36,94 @@ #define RSWITCH_MAX_CTAG_PCP 7 /* Registers */ -#define RSWITCH_COMA_OFFSET 0x00009000 -#define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */ -#define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */ +#define RSWITCH_COMA_OFFSET 0x00009000 +#define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */ +#define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */ #define RSWITCH_GWCA_OFFSET 0x00010000 #define RSWITCH_GWCA_SIZE 0x00002000 -#define FWRO 0 -#define CARO RSWITCH_COMA_OFFSET -#define GWRO 0 -#define TARO 0 -#define RMRO 0x1000 - -enum rswitch_reg { - EAMC = TARO + 0x0000, - EAMS = TARO + 0x0004, - EATDQDC = TARO + 0x0060, - EATTFC = TARO + 0x0138, - EATASRIRM = TARO + 0x03E4, - - GWMC = GWRO + 0x0000, - GWMS = GWRO + 0x0004, - GWMTIRM = GWRO + 0x0100, - GWVCC = GWRO + 0x0130, - GWTTFC = GWRO + 0x0138, - GWDCBAC0 = GWRO + 0x0194, - GWDCBAC1 = GWRO + 0x0198, - GWTRC = GWRO + 0x0200, - GWARIRM = GWRO + 0x0380, - GWDCC = GWRO + 0x0400, - - RRC = CARO + 0x0004, - RCEC = CARO + 0x0008, - RCDC = CARO + 0x000C, - CABPIRM = CARO + 0x0140, - - FWPC0 = FWRO + 0x0100, - FWPBFC = FWRO + 0x4A00, - FWPBFCSDC = FWRO + 0x4A04, - - MPSM = RMRO + 0x0000, - MPIC = RMRO + 0x0004, - MRMAC0 = RMRO + 0x0084, - MRMAC1 = RMRO + 0x0088, - MRAFC = RMRO + 0x008C, - MRSCE = RMRO + 0x0090, - MRSCP = RMRO + 0x0094, - MLVC = RMRO + 0x0180, - MLBC = RMRO + 0x0188, - MXGMIIC = RMRO + 0x0190, - MPCH = RMRO + 0x0194, - MANM = RMRO + 0x019C, - MMIS0 = RMRO + 0x0210, - MMIS1 = RMRO + 0x0220, -}; +#define FWRO 0 +#define CARO RSWITCH_COMA_OFFSET +#define GWRO 0 +#define TARO 0 +#define RMRO 0x1000 + +/* List of TSNA registers (ETHA) */ +#define EAMC (TARO + 0x0000) +#define EAMS (TARO + 0x0004) +#define EATDQDCR (TARO + 0x0060) +#define EATTFC (TARO + 0x0138) +#define EATASRIRM (TARO + 0x03e4) +/* Gateway CPU agent block (GWCA) */ +#define GWMC (GWRO + 0x0000) +#define GWMS (GWRO + 0x0004) +#define GWMTIRM (GWRO + 0x0100) +#define GWVCC (GWRO + 0x0130) +#define GWTTFC (GWRO + 0x0138) +#define GWDCBAC0 (GWRO + 0x0194) +#define GWDCBAC1 (GWRO + 0x0198) +#define GWTRCR (GWRO + 0x0200) +#define GWARIRM (GWRO + 0x0380) +#define GWDCCR (GWRO + 0x0400) +/* List of Common Agent registers (COMA) */ +#define RRC (CARO + 0x0004) +#define RCEC (CARO + 0x0008) +#define RCDC (CARO + 0x000c) +#define CABPIRM (CARO + 0x0140) +/* List of MFWD registers */ +#define FWPC (FWRO + 0x0100) +#define FWPBFCR (FWRO + 0x4a00) +#define FWPBFCSDCR (FWRO + 0x4a04) +/* List of RMAC registers (RMAC) */ +#define MPSM (RMRO + 0x0000) +#define MPIC (RMRO + 0x0004) +#define MRMAC0 (RMRO + 0x0084) +#define MRMAC1 (RMRO + 0x0088) +#define MRAFC (RMRO + 0x008c) +#define MRSCE (RMRO + 0x0090) +#define MRSCP (RMRO + 0x0094) +#define MLVC (RMRO + 0x0180) +#define MLBC (RMRO + 0x0188) +#define MXGMIIC (RMRO + 0x0190) +#define MPCH (RMRO + 0x0194) +#define MANM (RMRO + 0x019c) +#define MMIS0 (RMRO + 0x0210) +#define MMIS1 (RMRO + 0x0220) /* COMA */ -#define RRC_RR BIT(0) -#define RCEC_RCE BIT(16) +#define RRC_RR BIT(0) +#define RCEC_RCE BIT(16) -#define CABPIRM_BPIOG BIT(0) -#define CABPIRM_BPR BIT(1) +#define CABPIRM_BPIOG BIT(0) +#define CABPIRM_BPR BIT(1) /* MFWD */ -#define FWPC0(i) (FWPC0 + (i) * 0x10) -#define FWPC0_LTHTA BIT(0) -#define FWPC0_IP4UE BIT(3) -#define FWPC0_IP4TE BIT(4) -#define FWPC0_IP4OE BIT(5) -#define FWPC0_L2SE BIT(9) -#define FWPC0_IP4EA BIT(10) -#define FWPC0_IPDSA BIT(12) -#define FWPC0_IPHLA BIT(18) -#define FWPC0_MACSDA BIT(20) -#define FWPC0_MACHLA BIT(26) -#define FWPC0_MACHMA BIT(27) -#define FWPC0_VLANSA BIT(28) - -#define FWPC0_DEFAULT (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \ - FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \ - FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \ - FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA) - -#define FWPBFC(i) (FWPBFC + (i) * 0x10) -#define FWPBFCSDC(j, i) (FWPBFCSDC + (i) * 0x10 + (j) * 0x04) +#define FWPC0(i) (FWPC + (i) * 0x10) +#define FWPC0_LTHTA BIT(0) +#define FWPC0_IP4UE BIT(3) +#define FWPC0_IP4TE BIT(4) +#define FWPC0_IP4OE BIT(5) +#define FWPC0_L2SE BIT(9) +#define FWPC0_IP4EA BIT(10) +#define FWPC0_IPDSA BIT(12) +#define FWPC0_IPHLA BIT(18) +#define FWPC0_MACSDA BIT(20) +#define FWPC0_MACHLA BIT(26) +#define FWPC0_MACHMA BIT(27) +#define FWPC0_VLANSA BIT(28) + +#define FWPC0_DEFAULT (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \ + FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \ + FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \ + FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA) + +#define FWPBFC(i) (FWPBFCR + (i) * 0x10) +#define FWPBFCSDC(j, i) (FWPBFCSDCR + (i) * 0x10 + (j) * 0x04) /* ETHA */ #define EATASRIRM_TASRIOG BIT(0) #define EATASRIRM_TASRR BIT(1) -#define EATDQDC(q) (EATDQDC + (q) * 0x04) +#define EATDQDC(q) (EATDQDCR + (q) * 0x04) #define EATDQDC_DQD (0xff) /* RMAC */ @@ -149,8 +148,8 @@ enum rswitch_reg { #define MDIO_WRITE_C45 0x01 #define MDIO_ADDR_C45 0x00 -#define MDIO_READ_C22 0x02 -#define MDIO_WRITE_C22 0x01 +#define MDIO_READ_C22 0x02 +#define MDIO_WRITE_C22 0x01 #define MPSM_POP_MASK (0x03 << 13) #define MPSM_PRA_MASK (0x1f << 8) @@ -189,8 +188,8 @@ enum rswitch_gwca_mode { #define GWARIRM_ARR BIT(1) #define GWVCC_VEM_SC_TAG (0x3 << 16) #define GWDCBAC0_DCBAUP (0xff) -#define GWTRC(i) (GWTRC + (i) * 0x04) -#define GWDCC(i) (GWDCC + (i) * 0x04) +#define GWTRC(i) (GWTRCR + (i) * 0x04) +#define GWDCC(i) (GWDCCR + (i) * 0x04) #define GWDCC_DQT BIT(11) #define GWDCC_BALR BIT(24) @@ -356,15 +355,52 @@ static int rswitch_gwca_change_mode(struct rswitch_port_priv *priv, return ret; } +static int rswitch_mii_access_c22(struct rswitch_etha *etha, bool read, + int phyad, int regad, int data) +{ + const u32 pop = read ? MDIO_READ_C22 : MDIO_WRITE_C22; + u32 val, pval; + int ret; + + /* Clear Station Management Mode : Clause 22 */ + clrbits_le32(etha->addr + MPSM, MPSM_MFF_C45); + + /* Clear completion flags */ + writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); + + /* Submit C22 access to PHY */ + val = MPSM_PSME | (pop << 13) | (regad << 8) | (phyad << 3); + if (!read) + val |= data << 16; + writel(val, etha->addr + MPSM); + + ret = readl_poll_sleep_timeout(etha->addr + MPSM, pval, + !(pval & MPSM_PSME), + RSWITCH_SLEEP_US, + RSWITCH_TIMEOUT_US); + if (ret) + return ret; + + if (!read) + return 0; + + /* Read data */ + ret = (readl(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16; + + /* Clear read completion flag */ + setbits_le32(etha->addr + MMIS1, MMIS1_PRACS); + + return ret; +} + static int rswitch_mii_access_c45(struct rswitch_etha *etha, bool read, int phyad, int devad, int regad, int data) { u32 pval, val; int ret; - /* No match device */ - if (devad == 0xffffffff) - return 0; + /* Set Station Management Mode : Clause 45 */ + setbits_le32(etha->addr + MPSM, MPSM_MFF_C45); /* Clear completion flags */ writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); @@ -418,7 +454,6 @@ static int rswitch_mii_read_c45(struct mii_dev *miidev, int phyad, int devad, in struct rswitch_port_priv *priv = miidev->priv; struct rswitch_etha *etha = &priv->etha; int val; - int reg; /* Change to disable mode */ rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE); @@ -427,15 +462,17 @@ static int rswitch_mii_read_c45(struct mii_dev *miidev, int phyad, int devad, in rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG); /* Enable Station Management clock */ - reg = readl(etha->addr + MPIC); - reg &= ~MPIC_PSMCS_MASK & ~MPIC_PSMHT_MASK; - writel(reg | MPIC_MDC_CLK_SET, etha->addr + MPIC); - - /* Set Station Management Mode : Clause 45 */ - setbits_le32(etha->addr + MPSM, MPSM_MFF_C45); + clrsetbits_le32(etha->addr + MPIC, + MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, + MPIC_MDC_CLK_SET); /* Access PHY register */ - val = rswitch_mii_access_c45(etha, true, phyad, devad, regad, 0); + if (devad != MDIO_DEVAD_NONE) /* Definitelly C45 */ + val = rswitch_mii_access_c45(etha, true, phyad, devad, regad, 0); + else if (etha->phydev->is_c45) /* C22 access to C45 PHY */ + val = rswitch_mii_access_c45(etha, true, phyad, 1, regad, 0); + else + val = rswitch_mii_access_c22(etha, true, phyad, regad, 0); /* Disable Station Management Clock */ clrbits_le32(etha->addr + MPIC, MPIC_PSMCS_MASK); @@ -450,7 +487,6 @@ int rswitch_mii_write_c45(struct mii_dev *miidev, int phyad, int devad, int rega { struct rswitch_port_priv *priv = miidev->priv; struct rswitch_etha *etha = &priv->etha; - int reg; /* Change to disable mode */ rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE); @@ -459,15 +495,17 @@ int rswitch_mii_write_c45(struct mii_dev *miidev, int phyad, int devad, int rega rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG); /* Enable Station Management clock */ - reg = readl(etha->addr + MPIC); - reg &= ~MPIC_PSMCS_MASK & ~MPIC_PSMHT_MASK; - writel(reg | MPIC_MDC_CLK_SET, etha->addr + MPIC); - - /* Set Station Management Mode : Clause 45 */ - setbits_le32(etha->addr + MPSM, MPSM_MFF_C45); + clrsetbits_le32(etha->addr + MPIC, + MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, + MPIC_MDC_CLK_SET); /* Access PHY register */ - rswitch_mii_access_c45(etha, false, phyad, devad, regad, data); + if (devad != MDIO_DEVAD_NONE) /* Definitelly C45 */ + rswitch_mii_access_c45(etha, false, phyad, devad, regad, data); + else if (etha->phydev->is_c45) /* C22 access to C45 PHY */ + rswitch_mii_access_c45(etha, false, phyad, 1, regad, data); + else + rswitch_mii_access_c22(etha, false, phyad, regad, data); /* Disable Station Management Clock */ clrbits_le32(etha->addr + MPIC, MPIC_PSMCS_MASK); |