diff options
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/Kconfig | 12 | ||||
| -rw-r--r-- | drivers/net/fec_mxc.c | 27 | ||||
| -rw-r--r-- | drivers/net/mtk_eth.c | 175 | ||||
| -rw-r--r-- | drivers/net/mtk_eth.h | 26 | ||||
| -rw-r--r-- | drivers/net/ravb.c | 6 | ||||
| -rw-r--r-- | drivers/net/rswitch.c | 242 |
6 files changed, 341 insertions, 147 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 576cd2d50ad..5a57d05d977 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -975,6 +975,18 @@ config MEDIATEK_ETH This Driver support MediaTek Ethernet GMAC Say Y to enable support for the MediaTek Ethernet GMAC. +if MEDIATEK_ETH + +config MTK_ETH_SGMII + bool + default y if ARCH_MEDIATEK && !TARGET_MT7623 + +config MTK_ETH_XGMII + bool + default y if TARGET_MT7987 || TARGET_MT7988 + +endif # MEDIATEK_ETH + config HIFEMAC_ETH bool "HiSilicon Fast Ethernet Controller" select DM_CLK diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index d6d5cb52fdd..54b08482b91 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -160,7 +160,7 @@ static int fec_get_clk_rate(void *udev, int idx) } } -static void fec_mii_setspeed(struct ethernet_regs *eth) +static void fec_mii_setspeed(struct udevice *dev, struct ethernet_regs *eth) { /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock @@ -182,7 +182,7 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) u32 hold; int ret; - ret = fec_get_clk_rate(NULL, 0); + ret = fec_get_clk_rate(dev, 0); if (ret < 0) { printf("Can't find FEC0 clk rate: %d\n", ret); return; @@ -581,7 +581,7 @@ static int fecmxc_init(struct udevice *dev) fec_reg_setup(fec); if (fec->xcv_type != SEVENWIRE) - fec_mii_setspeed(fec->bus->priv); + fec_mii_setspeed(dev, fec->bus->priv); /* Set Opcode/Pause Duration Register */ writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ @@ -996,7 +996,7 @@ static void fec_free_descs(struct fec_priv *fec) free(fec->tbd_base); } -struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) +struct mii_dev *fec_get_miibus(struct udevice *dev, ulong base_addr, int dev_id) { struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; struct mii_dev *bus; @@ -1018,7 +1018,7 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) free(bus); return NULL; } - fec_mii_setspeed(eth); + fec_mii_setspeed(dev, eth); return bus; } @@ -1162,6 +1162,7 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) { struct phy_device *phydev = NULL; int addr; + int ret; addr = device_get_phy_addr(priv, dev); #ifdef CFG_FEC_MXC_PHYADDR @@ -1175,6 +1176,17 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) if (!phydev) return -ENODEV; + switch (priv->interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RMII: + ret = phy_set_supported(phydev, SPEED_100); + if (ret) + return ret; + break; + default: + break; + } + priv->phydev = phydev; priv->phydev->node = priv->phy_of_node; phy_config(phydev); @@ -1354,10 +1366,10 @@ static int fecmxc_probe(struct udevice *dev) if (!bus) { dm_mii_bus = false; #ifdef CONFIG_FEC_MXC_MDIO_BASE - bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, + bus = fec_get_miibus(dev, (ulong)CONFIG_FEC_MXC_MDIO_BASE, dev_seq(dev)); #else - bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev)); + bus = fec_get_miibus(dev, (ulong)priv->eth, dev_seq(dev)); #endif } if (!bus) { @@ -1491,4 +1503,5 @@ U_BOOT_DRIVER(fecmxc_gem) = { .ops = &fecmxc_ops, .priv_auto = sizeof(struct fec_priv), .plat_auto = sizeof(struct eth_pdata), + .flags = DM_FLAG_ACTIVE_DMA, }; diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 5098afef8a8..454caa3cd3a 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -29,8 +29,8 @@ #include "mtk_eth.h" -#define NUM_TX_DESC 24 -#define NUM_RX_DESC 24 +#define NUM_TX_DESC 32 +#define NUM_RX_DESC 32 #define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN) #define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN) #define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE) @@ -835,8 +835,8 @@ static int mt7531_port_sgmii_init(struct mtk_eth_priv *priv, } /* Set SGMII GEN2 speed(2.5G) */ - mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), - SGMSYS_SPEED_2500, SGMSYS_SPEED_2500); + mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK, + FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); /* Disable SGMII AN */ mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port), @@ -1246,6 +1246,7 @@ static int mtk_phy_start(struct mtk_eth_priv *priv) if (!priv->force_mode) { if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || priv->phy_interface == PHY_INTERFACE_MODE_XGMII) mtk_xphy_link_adjust(priv); else @@ -1281,8 +1282,7 @@ static int mtk_phy_probe(struct udevice *dev) static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) { /* Set SGMII GEN1 speed(1G) */ - clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, - SGMSYS_SPEED_2500, 0); + clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK); /* Enable SGMII AN */ setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, @@ -1305,8 +1305,9 @@ static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) static void mtk_sgmii_force_init(struct mtk_eth_priv *priv) { /* Set SGMII GEN2 speed(2.5G) */ - setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, - SGMSYS_SPEED_2500); + clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, + SGMSYS_SPEED_MASK, + FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); /* Disable SGMII AN */ clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, @@ -1425,6 +1426,71 @@ static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv) udelay(400); } +static void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth_priv *priv) +{ + regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6C); + regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); + regmap_write(priv->usxgmii_regmap, 0x80C, 0xB0000000); + ndelay(1020); + regmap_write(priv->usxgmii_regmap, 0x80C, 0x90000000); + ndelay(1020); + + regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); + regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); + regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); + regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); + regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); + regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); + regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); + regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); + regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); + regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); + regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); + regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); + regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); + regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); + regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); + regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); + regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); + regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); + regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); + regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); + regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); + regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); + regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); + ndelay(1020); + regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); + regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); + regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); + regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); + regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); + regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); + regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); + regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x47684100); + regmap_write(priv->xfi_pextp_regmap, 0x3050, 0x00000000); + regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x00000000); + regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); + if (priv->gmac_id == 2) + regmap_write(priv->xfi_pextp_regmap, 0xA008, 0x0007B400); + regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); + regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); + udelay(150); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); + ndelay(1020); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); + udelay(15); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); + ndelay(1020); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); + udelay(100); + regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); + regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); + regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); + udelay(400); +} + static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) { mtk_xfi_pll_enable(priv); @@ -1432,11 +1498,23 @@ static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) mtk_usxgmii_setup_phya_an_10000(priv); } -static void mtk_mac_init(struct mtk_eth_priv *priv) +static void mtk_10gbaser_init(struct mtk_eth_priv *priv) +{ + mtk_xfi_pll_enable(priv); + mtk_usxgmii_reset(priv); + mtk_usxgmii_setup_phya_force_10000(priv); +} + +static int mtk_mac_init(struct mtk_eth_priv *priv) { - int i, ge_mode = 0; + int i, sgmii_sel_mask = 0, ge_mode = 0; u32 mcr; + if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7629_GMAC2)) { + mtk_infra_rmw(priv, MT7629_INFRA_MISC2_REG, + INFRA_MISC2_BONDING_OPTION, priv->gmac_id); + } + switch (priv->phy_interface) { case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII: @@ -1444,18 +1522,28 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) break; case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_2500BASEX: + if (!IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { + printf("Error: SGMII is not supported on this platform\n"); + return -ENOTSUPP; + } + if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) { mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK, SGMII_QPHY_SEL); } - ge_mode = GE_MODE_RGMII; - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M, - SYSCFG0_SGMII_SEL(priv->gmac_id)); + if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII)) + sgmii_sel_mask = SYSCFG1_SGMII_SEL_M; + + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask, + SYSCFG1_SGMII_SEL(priv->gmac_id)); + if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) mtk_sgmii_an_init(priv); else mtk_sgmii_force_init(priv); + + ge_mode = GE_MODE_RGMII; break; case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: @@ -1469,9 +1557,9 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) } /* set the gmac to the right mode */ - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, - SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), - ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id)); + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, + SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), + ge_mode << SYSCFG1_GE_MODE_S(priv->gmac_id)); if (priv->force_mode) { mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | @@ -1512,26 +1600,37 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) RX_RST | RXC_DQSISEL); mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0); } + + return 0; } -static void mtk_xmac_init(struct mtk_eth_priv *priv) +static int mtk_xmac_init(struct mtk_eth_priv *priv) { u32 force_link = 0; + if (!IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { + printf("Error: 10Gb interface is not supported on this platform\n"); + return -ENOTSUPP; + } + switch (priv->phy_interface) { case PHY_INTERFACE_MODE_USXGMII: mtk_usxgmii_an_init(priv); break; + case PHY_INTERFACE_MODE_10GBASER: + mtk_10gbaser_init(priv); + break; default: break; } /* Set GMAC to the correct mode */ - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, - SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, + SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), 0); - if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII && + if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && priv->gmac_id == 1) { mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX, NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL); @@ -1546,6 +1645,8 @@ static void mtk_xmac_init(struct mtk_eth_priv *priv) /* Force GMAC link down */ mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE); + + return 0; } static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) @@ -1661,10 +1762,16 @@ static int mtk_eth_start(struct udevice *dev) if (priv->sw == SW_MT7988 && priv->gmac_id == 0) { mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_BRIDGE_TO_CPU); - } - mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, - GDMA_CPU_BRIDGE_EN); + mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, + GDMA_CPU_BRIDGE_EN); + } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || + priv->phy_interface == PHY_INTERFACE_MODE_XGMII) && + priv->gmac_id != 0) { + mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, + GDMA_CPU_BRIDGE_EN); + } } udelay(500); @@ -1790,6 +1897,9 @@ static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length) rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; + invalidate_dcache_range((ulong)rxd->rxd1, + (ulong)rxd->rxd1 + PKTSIZE_ALIGN); + if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); @@ -1833,10 +1943,14 @@ static int mtk_eth_probe(struct udevice *dev) /* Set MAC mode */ if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || priv->phy_interface == PHY_INTERFACE_MODE_XGMII) - mtk_xmac_init(priv); + ret = mtk_xmac_init(priv); else - mtk_mac_init(priv); + ret = mtk_mac_init(priv); + + if (ret) + return ret; /* Probe phy if switch is not specified */ if (priv->sw == SW_NONE) @@ -1944,8 +2058,9 @@ static int mtk_eth_of_to_plat(struct udevice *dev) } } - if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII || - priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { + if ((priv->phy_interface == PHY_INTERFACE_MODE_SGMII || + priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) && + IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { /* get corresponding sgmii phandle */ ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys", NULL, 0, 0, &args); @@ -1967,7 +2082,9 @@ static int mtk_eth_of_to_plat(struct udevice *dev) /* Upstream linux use mediatek,pnswap instead of pn_swap */ priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") || ofnode_read_bool(args.node, "mediatek,pnswap"); - } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) { + } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && + IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { /* get corresponding usxgmii phandle */ ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", NULL, 0, 0, &args); @@ -2096,6 +2213,7 @@ static const struct mtk_soc_data mt7981_data = { }; static const struct mtk_soc_data mt7629_data = { + .caps = MT7629_CAPS, .ana_rgc3 = 0x128, .gdma_count = 2, .pdma_base = PDMA_V1_BASE, @@ -2112,6 +2230,7 @@ static const struct mtk_soc_data mt7623_data = { }; static const struct mtk_soc_data mt7622_data = { + .caps = MT7622_CAPS, .ana_rgc3 = 0x2028, .gdma_count = 2, .pdma_base = PDMA_V1_BASE, diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h index fd31c782c7f..1aa037907c5 100644 --- a/drivers/net/mtk_eth.h +++ b/drivers/net/mtk_eth.h @@ -23,6 +23,8 @@ enum mkt_eth_capabilities { /* PATH BITS */ MTK_ETH_PATH_GMAC1_TRGMII_BIT, MTK_ETH_PATH_GMAC2_SGMII_BIT, + MTK_ETH_PATH_MT7622_SGMII_BIT, + MTK_ETH_PATH_MT7629_GMAC2_BIT, }; #define MTK_TRGMII BIT(MTK_TRGMII_BIT) @@ -36,6 +38,8 @@ enum mkt_eth_capabilities { #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) +#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) +#define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT) #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) @@ -45,8 +49,12 @@ enum mkt_eth_capabilities { #define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) +#define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII) + #define MT7623_CAPS (MTK_GMAC1_TRGMII) +#define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA) + #define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) #define MT7986_CAPS (MTK_NETSYS_V2) @@ -65,11 +73,11 @@ enum mkt_eth_capabilities { /* Ethernet subsystem registers */ -#define ETHSYS_SYSCFG0_REG 0x14 -#define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2)) -#define SYSCFG0_GE_MODE_M 0x3 -#define SYSCFG0_SGMII_SEL_M (0x3 << 8) -#define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8)) +#define ETHSYS_SYSCFG1_REG 0x14 +#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) +#define SYSCFG1_GE_MODE_M 0x3 +#define SYSCFG1_SGMII_SEL_M GENMASK(9, 8) +#define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac)) #define ETHSYS_CLKCFG0_REG 0x2c #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) @@ -84,7 +92,10 @@ enum mkt_eth_capabilities { #define QPHY_SEL_MASK 0x3 #define SGMII_QPHY_SEL 0x2 -/* SYSCFG0_GE_MODE: GE Modes */ +#define MT7629_INFRA_MISC2_REG 0x70c +#define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0) + +/* SYSCFG1_GE_MODE: GE Modes */ #define GE_MODE_RGMII 0 #define GE_MODE_MII 1 #define GE_MODE_MII_PHY 2 @@ -108,7 +119,8 @@ enum mkt_eth_capabilities { #define SGMSYS_GEN2_SPEED 0x2028 #define SGMSYS_GEN2_SPEED_V2 0x128 -#define SGMSYS_SPEED_2500 BIT(2) +#define SGMSYS_SPEED_MASK GENMASK(3, 2) +#define SGMSYS_SPEED_2500 1 /* USXGMII subsystem config registers */ /* Register to control USXGMII XFI PLL digital */ diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index f1401d2f6ed..231764e60b5 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -649,7 +649,6 @@ static const struct eth_ops ravb_ops = { int ravb_of_to_plat(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); - const fdt32_t *cell; pdata->iobase = dev_read_addr(dev); @@ -657,10 +656,7 @@ int ravb_of_to_plat(struct udevice *dev) if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) return -EINVAL; - pdata->max_speed = 1000; - cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL); - if (cell) - pdata->max_speed = fdt32_to_cpu(*cell); + pdata->max_speed = dev_read_u32_default(dev, "max-speed", 1000); sprintf(bb_miiphy_buses[0].name, dev->name); diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index 8e1b6e2f6f6..62d3f39f071 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -36,95 +36,94 @@ #define RSWITCH_MAX_CTAG_PCP 7 /* Registers */ -#define RSWITCH_COMA_OFFSET 0x00009000 -#define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */ -#define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */ +#define RSWITCH_COMA_OFFSET 0x00009000 +#define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */ +#define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */ #define RSWITCH_GWCA_OFFSET 0x00010000 #define RSWITCH_GWCA_SIZE 0x00002000 -#define FWRO 0 -#define CARO RSWITCH_COMA_OFFSET -#define GWRO 0 -#define TARO 0 -#define RMRO 0x1000 - -enum rswitch_reg { - EAMC = TARO + 0x0000, - EAMS = TARO + 0x0004, - EATDQDC = TARO + 0x0060, - EATTFC = TARO + 0x0138, - EATASRIRM = TARO + 0x03E4, - - GWMC = GWRO + 0x0000, - GWMS = GWRO + 0x0004, - GWMTIRM = GWRO + 0x0100, - GWVCC = GWRO + 0x0130, - GWTTFC = GWRO + 0x0138, - GWDCBAC0 = GWRO + 0x0194, - GWDCBAC1 = GWRO + 0x0198, - GWTRC = GWRO + 0x0200, - GWARIRM = GWRO + 0x0380, - GWDCC = GWRO + 0x0400, - - RRC = CARO + 0x0004, - RCEC = CARO + 0x0008, - RCDC = CARO + 0x000C, - CABPIRM = CARO + 0x0140, - - FWPC0 = FWRO + 0x0100, - FWPBFC = FWRO + 0x4A00, - FWPBFCSDC = FWRO + 0x4A04, - - MPSM = RMRO + 0x0000, - MPIC = RMRO + 0x0004, - MRMAC0 = RMRO + 0x0084, - MRMAC1 = RMRO + 0x0088, - MRAFC = RMRO + 0x008C, - MRSCE = RMRO + 0x0090, - MRSCP = RMRO + 0x0094, - MLVC = RMRO + 0x0180, - MLBC = RMRO + 0x0188, - MXGMIIC = RMRO + 0x0190, - MPCH = RMRO + 0x0194, - MANM = RMRO + 0x019C, - MMIS0 = RMRO + 0x0210, - MMIS1 = RMRO + 0x0220, -}; +#define FWRO 0 +#define CARO RSWITCH_COMA_OFFSET +#define GWRO 0 +#define TARO 0 +#define RMRO 0x1000 + +/* List of TSNA registers (ETHA) */ +#define EAMC (TARO + 0x0000) +#define EAMS (TARO + 0x0004) +#define EATDQDCR (TARO + 0x0060) +#define EATTFC (TARO + 0x0138) +#define EATASRIRM (TARO + 0x03e4) +/* Gateway CPU agent block (GWCA) */ +#define GWMC (GWRO + 0x0000) +#define GWMS (GWRO + 0x0004) +#define GWMTIRM (GWRO + 0x0100) +#define GWVCC (GWRO + 0x0130) +#define GWTTFC (GWRO + 0x0138) +#define GWDCBAC0 (GWRO + 0x0194) +#define GWDCBAC1 (GWRO + 0x0198) +#define GWTRCR (GWRO + 0x0200) +#define GWARIRM (GWRO + 0x0380) +#define GWDCCR (GWRO + 0x0400) +/* List of Common Agent registers (COMA) */ +#define RRC (CARO + 0x0004) +#define RCEC (CARO + 0x0008) +#define RCDC (CARO + 0x000c) +#define CABPIRM (CARO + 0x0140) +/* List of MFWD registers */ +#define FWPC (FWRO + 0x0100) +#define FWPBFCR (FWRO + 0x4a00) +#define FWPBFCSDCR (FWRO + 0x4a04) +/* List of RMAC registers (RMAC) */ +#define MPSM (RMRO + 0x0000) +#define MPIC (RMRO + 0x0004) +#define MRMAC0 (RMRO + 0x0084) +#define MRMAC1 (RMRO + 0x0088) +#define MRAFC (RMRO + 0x008c) +#define MRSCE (RMRO + 0x0090) +#define MRSCP (RMRO + 0x0094) +#define MLVC (RMRO + 0x0180) +#define MLBC (RMRO + 0x0188) +#define MXGMIIC (RMRO + 0x0190) +#define MPCH (RMRO + 0x0194) +#define MANM (RMRO + 0x019c) +#define MMIS0 (RMRO + 0x0210) +#define MMIS1 (RMRO + 0x0220) /* COMA */ -#define RRC_RR BIT(0) -#define RCEC_RCE BIT(16) +#define RRC_RR BIT(0) +#define RCEC_RCE BIT(16) -#define CABPIRM_BPIOG BIT(0) -#define CABPIRM_BPR BIT(1) +#define CABPIRM_BPIOG BIT(0) +#define CABPIRM_BPR BIT(1) /* MFWD */ -#define FWPC0(i) (FWPC0 + (i) * 0x10) -#define FWPC0_LTHTA BIT(0) -#define FWPC0_IP4UE BIT(3) -#define FWPC0_IP4TE BIT(4) -#define FWPC0_IP4OE BIT(5) -#define FWPC0_L2SE BIT(9) -#define FWPC0_IP4EA BIT(10) -#define FWPC0_IPDSA BIT(12) -#define FWPC0_IPHLA BIT(18) -#define FWPC0_MACSDA BIT(20) -#define FWPC0_MACHLA BIT(26) -#define FWPC0_MACHMA BIT(27) -#define FWPC0_VLANSA BIT(28) - -#define FWPC0_DEFAULT (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \ - FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \ - FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \ - FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA) - -#define FWPBFC(i) (FWPBFC + (i) * 0x10) -#define FWPBFCSDC(j, i) (FWPBFCSDC + (i) * 0x10 + (j) * 0x04) +#define FWPC0(i) (FWPC + (i) * 0x10) +#define FWPC0_LTHTA BIT(0) +#define FWPC0_IP4UE BIT(3) +#define FWPC0_IP4TE BIT(4) +#define FWPC0_IP4OE BIT(5) +#define FWPC0_L2SE BIT(9) +#define FWPC0_IP4EA BIT(10) +#define FWPC0_IPDSA BIT(12) +#define FWPC0_IPHLA BIT(18) +#define FWPC0_MACSDA BIT(20) +#define FWPC0_MACHLA BIT(26) +#define FWPC0_MACHMA BIT(27) +#define FWPC0_VLANSA BIT(28) + +#define FWPC0_DEFAULT (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \ + FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \ + FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \ + FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA) + +#define FWPBFC(i) (FWPBFCR + (i) * 0x10) +#define FWPBFCSDC(j, i) (FWPBFCSDCR + (i) * 0x10 + (j) * 0x04) /* ETHA */ #define EATASRIRM_TASRIOG BIT(0) #define EATASRIRM_TASRR BIT(1) -#define EATDQDC(q) (EATDQDC + (q) * 0x04) +#define EATDQDC(q) (EATDQDCR + (q) * 0x04) #define EATDQDC_DQD (0xff) /* RMAC */ @@ -149,8 +148,8 @@ enum rswitch_reg { #define MDIO_WRITE_C45 0x01 #define MDIO_ADDR_C45 0x00 -#define MDIO_READ_C22 0x02 -#define MDIO_WRITE_C22 0x01 +#define MDIO_READ_C22 0x02 +#define MDIO_WRITE_C22 0x01 #define MPSM_POP_MASK (0x03 << 13) #define MPSM_PRA_MASK (0x1f << 8) @@ -189,8 +188,8 @@ enum rswitch_gwca_mode { #define GWARIRM_ARR BIT(1) #define GWVCC_VEM_SC_TAG (0x3 << 16) #define GWDCBAC0_DCBAUP (0xff) -#define GWTRC(i) (GWTRC + (i) * 0x04) -#define GWDCC(i) (GWDCC + (i) * 0x04) +#define GWTRC(i) (GWTRCR + (i) * 0x04) +#define GWDCC(i) (GWDCCR + (i) * 0x04) #define GWDCC_DQT BIT(11) #define GWDCC_BALR BIT(24) @@ -356,15 +355,52 @@ static int rswitch_gwca_change_mode(struct rswitch_port_priv *priv, return ret; } +static int rswitch_mii_access_c22(struct rswitch_etha *etha, bool read, + int phyad, int regad, int data) +{ + const u32 pop = read ? MDIO_READ_C22 : MDIO_WRITE_C22; + u32 val, pval; + int ret; + + /* Clear Station Management Mode : Clause 22 */ + clrbits_le32(etha->addr + MPSM, MPSM_MFF_C45); + + /* Clear completion flags */ + writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); + + /* Submit C22 access to PHY */ + val = MPSM_PSME | (pop << 13) | (regad << 8) | (phyad << 3); + if (!read) + val |= data << 16; + writel(val, etha->addr + MPSM); + + ret = readl_poll_sleep_timeout(etha->addr + MPSM, pval, + !(pval & MPSM_PSME), + RSWITCH_SLEEP_US, + RSWITCH_TIMEOUT_US); + if (ret) + return ret; + + if (!read) + return 0; + + /* Read data */ + ret = (readl(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16; + + /* Clear read completion flag */ + setbits_le32(etha->addr + MMIS1, MMIS1_PRACS); + + return ret; +} + static int rswitch_mii_access_c45(struct rswitch_etha *etha, bool read, int phyad, int devad, int regad, int data) { u32 pval, val; int ret; - /* No match device */ - if (devad == 0xffffffff) - return 0; + /* Set Station Management Mode : Clause 45 */ + setbits_le32(etha->addr + MPSM, MPSM_MFF_C45); /* Clear completion flags */ writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); @@ -418,7 +454,6 @@ static int rswitch_mii_read_c45(struct mii_dev *miidev, int phyad, int devad, in struct rswitch_port_priv *priv = miidev->priv; struct rswitch_etha *etha = &priv->etha; int val; - int reg; /* Change to disable mode */ rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE); @@ -427,15 +462,17 @@ static int rswitch_mii_read_c45(struct mii_dev *miidev, int phyad, int devad, in rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG); /* Enable Station Management clock */ - reg = readl(etha->addr + MPIC); - reg &= ~MPIC_PSMCS_MASK & ~MPIC_PSMHT_MASK; - writel(reg | MPIC_MDC_CLK_SET, etha->addr + MPIC); - - /* Set Station Management Mode : Clause 45 */ - setbits_le32(etha->addr + MPSM, MPSM_MFF_C45); + clrsetbits_le32(etha->addr + MPIC, + MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, + MPIC_MDC_CLK_SET); /* Access PHY register */ - val = rswitch_mii_access_c45(etha, true, phyad, devad, regad, 0); + if (devad != MDIO_DEVAD_NONE) /* Definitelly C45 */ + val = rswitch_mii_access_c45(etha, true, phyad, devad, regad, 0); + else if (etha->phydev->is_c45) /* C22 access to C45 PHY */ + val = rswitch_mii_access_c45(etha, true, phyad, 1, regad, 0); + else + val = rswitch_mii_access_c22(etha, true, phyad, regad, 0); /* Disable Station Management Clock */ clrbits_le32(etha->addr + MPIC, MPIC_PSMCS_MASK); @@ -450,7 +487,6 @@ int rswitch_mii_write_c45(struct mii_dev *miidev, int phyad, int devad, int rega { struct rswitch_port_priv *priv = miidev->priv; struct rswitch_etha *etha = &priv->etha; - int reg; /* Change to disable mode */ rswitch_etha_change_mode(priv, EAMC_OPC_DISABLE); @@ -459,15 +495,17 @@ int rswitch_mii_write_c45(struct mii_dev *miidev, int phyad, int devad, int rega rswitch_etha_change_mode(priv, EAMC_OPC_CONFIG); /* Enable Station Management clock */ - reg = readl(etha->addr + MPIC); - reg &= ~MPIC_PSMCS_MASK & ~MPIC_PSMHT_MASK; - writel(reg | MPIC_MDC_CLK_SET, etha->addr + MPIC); - - /* Set Station Management Mode : Clause 45 */ - setbits_le32(etha->addr + MPSM, MPSM_MFF_C45); + clrsetbits_le32(etha->addr + MPIC, + MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, + MPIC_MDC_CLK_SET); /* Access PHY register */ - rswitch_mii_access_c45(etha, false, phyad, devad, regad, data); + if (devad != MDIO_DEVAD_NONE) /* Definitelly C45 */ + rswitch_mii_access_c45(etha, false, phyad, devad, regad, data); + else if (etha->phydev->is_c45) /* C22 access to C45 PHY */ + rswitch_mii_access_c45(etha, false, phyad, 1, regad, data); + else + rswitch_mii_access_c22(etha, false, phyad, regad, data); /* Disable Station Management Clock */ clrbits_le32(etha->addr + MPIC, MPIC_PSMCS_MASK); @@ -837,6 +875,7 @@ static int rswitch_send(struct udevice *dev, void *packet, int len) /* Update TX descriptor */ rswitch_flush_dcache((uintptr_t)packet, len); + rswitch_invalidate_dcache((uintptr_t)desc, sizeof(*desc)); memset(desc, 0x0, sizeof(*desc)); desc->die_dt = DT_FSINGLE; desc->info_ds = len; @@ -1112,6 +1151,9 @@ static int rswitch_bind(struct udevice *parent) return -ENOENT; ofnode_for_each_subnode(node, ports_np) { + if (!ofnode_is_enabled(node)) + continue; + ret = device_bind_with_driver_data(parent, drv, ofnode_get_name(node), (ulong)priv, node, &dev); |