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-rw-r--r--drivers/net/Kconfig33
-rw-r--r--drivers/net/Makefile4
-rw-r--r--drivers/net/designware.c96
-rw-r--r--drivers/net/dsa_sandbox.c179
-rw-r--r--drivers/net/dwmac_meson8b.c150
-rw-r--r--drivers/net/fm/Makefile2
-rw-r--r--drivers/net/mdio_mux_meson_g12a.c149
-rw-r--r--drivers/net/mdio_mux_mmioreg.c129
-rw-r--r--drivers/net/phy/Kconfig1
-rw-r--r--drivers/net/phy/fixed.c54
-rw-r--r--drivers/net/phy/phy.c63
-rw-r--r--drivers/net/phy/xilinx_gmii2rgmii.c61
-rw-r--r--drivers/net/tsec.c36
-rw-r--r--drivers/net/zynq_gem.c25
14 files changed, 876 insertions, 106 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 0e84c22b507..72822eaec4b 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -78,6 +78,15 @@ config DM_ETH_PHY
help
Enable driver model for Ethernet Generic PHY .
+config DSA_SANDBOX
+ depends on DM_DSA && SANDBOX
+ default y
+ bool "Sandbox: Mocked DSA driver"
+ help
+ This driver implements a dummy DSA switch connected to a dummy sandbox
+ Ethernet device used as DSA master, to test DSA class code, including
+ exported DSA API and datapath processing of Ethernet traffic.
+
menuconfig NETDEVICES
bool "Network device support"
depends on NET
@@ -271,6 +280,14 @@ config ETH_DESIGNWARE
100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
provide the PHY (physical media interface).
+config ETH_DESIGNWARE_MESON8B
+ bool "Amlogic Meson8b and later glue driver for Synopsys Designware Ethernet MAC"
+ depends on DM_ETH
+ select ETH_DESIGNWARE
+ help
+ This provides glue layer to use Synopsys Designware Ethernet MAC
+ present on the Amlogic Meson8b, GX, AXG & G12A SoCs.
+
config ETH_DESIGNWARE_SOCFPGA
select REGMAP
select SYSCON
@@ -713,13 +730,11 @@ config SYS_DPAA_QBMAN
ARCH_T1040 || \
ARCH_T1042 || \
ARCH_T2080 || \
- ARCH_T2081 || \
ARCH_T4240 || \
ARCH_T4160 || \
ARCH_P4080 || \
ARCH_P3041 || \
ARCH_P5040 || \
- ARCH_P5020 || \
ARCH_LS1043A || \
ARCH_LS1046A
help
@@ -790,4 +805,18 @@ config FSL_LS_MDIO
This driver supports the MDIO bus found on the Fman 10G Ethernet MACs and
on the mEMAC (which supports both Clauses 22 and 45).
+config MDIO_MUX_MMIOREG
+ bool "MDIO MUX accessed as a MMIO register access"
+ depends on DM_MDIO_MUX
+ help
+ This driver is used for MDIO muxes driven by writing to a register in
+ the MMIO physical memory.
+
+config MDIO_MUX_MESON_G12A
+ bool "MDIO MUX for Amlogic Meson G12A SoCs"
+ depends on DM_MDIO_MUX
+ help
+ This driver is used for the MDIO mux found on the Amlogic G12A & compatible
+ SoCs.
+
endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a19511aaa7b..2ce89f7e3c6 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -18,10 +18,12 @@ obj-$(CONFIG_CORTINA_NI_ENET) += cortina_ni.o
obj-$(CONFIG_CS8900) += cs8900.o
obj-$(CONFIG_TULIP) += dc2114x.o
obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
+obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o
obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o
obj-$(CONFIG_ETH_DESIGNWARE_S700) += dwmac_s700.o
obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DNET) += dnet.o
+obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
@@ -43,6 +45,8 @@ obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o
obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o
+obj-$(CONFIG_MDIO_MUX_MESON_G12A) += mdio_mux_meson_g12a.o
+obj-$(CONFIG_MDIO_MUX_MMIOREG) += mdio_mux_mmioreg.o
obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o
obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 9dba55adaa7..b8ba00b7c0c 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -21,7 +21,9 @@
#include <reset.h>
#include <asm/cache.h>
#include <dm/device_compat.h>
+#include <dm/device-internal.h>
#include <dm/devres.h>
+#include <dm/lists.h>
#include <linux/compiler.h>
#include <linux/delay.h>
#include <linux/err.h>
@@ -122,6 +124,55 @@ static int dw_mdio_reset(struct mii_dev *bus)
}
#endif
+#if IS_ENABLED(CONFIG_DM_MDIO)
+int designware_eth_mdio_read(struct udevice *mdio_dev, int addr, int devad, int reg)
+{
+ struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
+
+ return dw_mdio_read(pdata->mii_bus, addr, devad, reg);
+}
+
+int designware_eth_mdio_write(struct udevice *mdio_dev, int addr, int devad, int reg, u16 val)
+{
+ struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
+
+ return dw_mdio_write(pdata->mii_bus, addr, devad, reg, val);
+}
+
+#if CONFIG_IS_ENABLED(DM_GPIO)
+int designware_eth_mdio_reset(struct udevice *mdio_dev)
+{
+ struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
+
+ return dw_mdio_reset(pdata->mii_bus);
+}
+#endif
+
+static const struct mdio_ops designware_eth_mdio_ops = {
+ .read = designware_eth_mdio_read,
+ .write = designware_eth_mdio_write,
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ .reset = designware_eth_mdio_reset,
+#endif
+};
+
+static int designware_eth_mdio_probe(struct udevice *dev)
+{
+ /* Use the priv data of parent */
+ dev_set_priv(dev, dev_get_priv(dev->parent));
+
+ return 0;
+}
+
+U_BOOT_DRIVER(designware_eth_mdio) = {
+ .name = "eth_designware_mdio",
+ .id = UCLASS_MDIO,
+ .probe = designware_eth_mdio_probe,
+ .ops = &designware_eth_mdio_ops,
+ .plat_auto = sizeof(struct mdio_perdev_priv),
+};
+#endif
+
static int dw_mdio_init(const char *name, void *priv)
{
struct mii_dev *bus = mdio_alloc();
@@ -143,6 +194,34 @@ static int dw_mdio_init(const char *name, void *priv)
return mdio_register(bus);
}
+#if IS_ENABLED(CONFIG_DM_MDIO)
+static int dw_dm_mdio_init(const char *name, void *priv)
+{
+ struct udevice *dev = priv;
+ ofnode node;
+ int ret;
+
+ ofnode_for_each_subnode(node, dev_ofnode(dev)) {
+ const char *subnode_name = ofnode_get_name(node);
+ struct udevice *mdiodev;
+
+ if (strcmp(subnode_name, "mdio"))
+ continue;
+
+ ret = device_bind_driver_to_node(dev, "eth_designware_mdio",
+ subnode_name, node, &mdiodev);
+ if (ret)
+ debug("%s: not able to bind mdio device node\n", __func__);
+
+ return 0;
+ }
+
+ printf("%s: mdio node is missing, registering legacy mdio bus", __func__);
+
+ return dw_mdio_init(name, priv);
+}
+#endif
+
static void tx_descs_init(struct dw_eth_dev *priv)
{
struct eth_dma_regs *dma_p = priv->dma_regs_p;
@@ -487,7 +566,14 @@ static int _dw_free_pkt(struct dw_eth_dev *priv)
static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
{
struct phy_device *phydev;
- int phy_addr = -1, ret;
+ int ret;
+
+#if IS_ENABLED(CONFIG_DM_MDIO) && IS_ENABLED(CONFIG_DM_ETH)
+ phydev = dm_eth_phy_connect(dev);
+ if (!phydev)
+ return -ENODEV;
+#else
+ int phy_addr = -1;
#ifdef CONFIG_PHY_ADDR
phy_addr = CONFIG_PHY_ADDR;
@@ -496,6 +582,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
if (!phydev)
return -ENODEV;
+#endif
phydev->supported &= PHY_GBIT_FEATURES;
if (priv->max_speed) {
@@ -759,7 +846,11 @@ int designware_eth_probe(struct udevice *dev)
priv->interface = pdata->phy_interface;
priv->max_speed = pdata->max_speed;
+#if IS_ENABLED(CONFIG_DM_MDIO)
+ ret = dw_dm_mdio_init(dev->name, dev);
+#else
ret = dw_mdio_init(dev->name, dev);
+#endif
if (ret) {
err = ret;
goto mdio_err;
@@ -856,9 +947,6 @@ int designware_eth_of_to_plat(struct udevice *dev)
static const struct udevice_id designware_eth_ids[] = {
{ .compatible = "allwinner,sun7i-a20-gmac" },
{ .compatible = "amlogic,meson6-dwmac" },
- { .compatible = "amlogic,meson-gx-dwmac" },
- { .compatible = "amlogic,meson-gxbb-dwmac" },
- { .compatible = "amlogic,meson-axg-dwmac" },
{ .compatible = "st,stm32-dwmac" },
{ .compatible = "snps,arc-dwmac-3.70a" },
{ }
diff --git a/drivers/net/dsa_sandbox.c b/drivers/net/dsa_sandbox.c
new file mode 100644
index 00000000000..4b62670e5d1
--- /dev/null
+++ b/drivers/net/dsa_sandbox.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+#include <asm/eth.h>
+#include <net/dsa.h>
+#include <net.h>
+
+#define DSA_SANDBOX_MAGIC 0x00415344
+#define DSA_SANDBOX_TAG_LEN sizeof(struct dsa_sandbox_tag)
+
+struct dsa_sandbox_priv {
+ struct eth_sandbox_priv *master_priv;
+ int port_en_mask;
+};
+
+struct dsa_sandbox_tag {
+ u32 magic;
+ u32 port;
+};
+
+static bool sb_dsa_port_enabled(struct udevice *dev, int port)
+{
+ struct dsa_sandbox_priv *priv = dev_get_priv(dev);
+
+ return priv->port_en_mask & BIT(port);
+}
+
+static bool sb_dsa_master_enabled(struct udevice *dev)
+{
+ struct dsa_sandbox_priv *priv = dev_get_priv(dev);
+
+ return !priv->master_priv->disabled;
+}
+
+static int dsa_sandbox_port_enable(struct udevice *dev, int port,
+ struct phy_device *phy)
+{
+ struct dsa_sandbox_priv *priv = dev_get_priv(dev);
+
+ if (!sb_dsa_master_enabled(dev))
+ return -EFAULT;
+
+ priv->port_en_mask |= BIT(port);
+
+ return 0;
+}
+
+static void dsa_sandbox_port_disable(struct udevice *dev, int port,
+ struct phy_device *phy)
+{
+ struct dsa_sandbox_priv *priv = dev_get_priv(dev);
+
+ priv->port_en_mask &= ~BIT(port);
+}
+
+static int dsa_sandbox_xmit(struct udevice *dev, int port, void *packet,
+ int length)
+{
+ struct dsa_sandbox_tag *tag = packet;
+
+ if (!sb_dsa_master_enabled(dev))
+ return -EFAULT;
+
+ if (!sb_dsa_port_enabled(dev, port))
+ return -EFAULT;
+
+ tag->magic = DSA_SANDBOX_MAGIC;
+ tag->port = port;
+
+ return 0;
+}
+
+static int dsa_sandbox_rcv(struct udevice *dev, int *port, void *packet,
+ int length)
+{
+ struct dsa_sandbox_tag *tag = packet;
+
+ if (!sb_dsa_master_enabled(dev))
+ return -EFAULT;
+
+ if (tag->magic != DSA_SANDBOX_MAGIC)
+ return -EFAULT;
+
+ *port = tag->port;
+ if (!sb_dsa_port_enabled(dev, tag->port))
+ return -EFAULT;
+
+ return 0;
+}
+
+static const struct dsa_ops dsa_sandbox_ops = {
+ .port_enable = dsa_sandbox_port_enable,
+ .port_disable = dsa_sandbox_port_disable,
+ .xmit = dsa_sandbox_xmit,
+ .rcv = dsa_sandbox_rcv,
+};
+
+static int sb_dsa_handler(struct udevice *dev, void *packet,
+ unsigned int len)
+{
+ struct eth_sandbox_priv *master_priv;
+ struct dsa_sandbox_tag *tag = packet;
+ struct udevice *dsa_dev;
+ u32 port_index;
+ void *rx_buf;
+ int i;
+
+ /* this emulates the switch hw and the network side */
+ if (tag->magic != DSA_SANDBOX_MAGIC)
+ return -EFAULT;
+
+ port_index = tag->port;
+ master_priv = dev_get_priv(dev);
+ dsa_dev = master_priv->priv;
+ if (!sb_dsa_port_enabled(dsa_dev, port_index))
+ return -EFAULT;
+
+ packet += DSA_SANDBOX_TAG_LEN;
+ len -= DSA_SANDBOX_TAG_LEN;
+
+ if (!sandbox_eth_arp_req_to_reply(dev, packet, len))
+ goto dsa_tagging;
+ if (!sandbox_eth_ping_req_to_reply(dev, packet, len))
+ goto dsa_tagging;
+
+ return 0;
+
+dsa_tagging:
+ master_priv->recv_packets--;
+ i = master_priv->recv_packets;
+ rx_buf = master_priv->recv_packet_buffer[i];
+ len = master_priv->recv_packet_length[i];
+ memmove(rx_buf + DSA_SANDBOX_TAG_LEN, rx_buf, len);
+
+ tag = rx_buf;
+ tag->magic = DSA_SANDBOX_MAGIC;
+ tag->port = port_index;
+ len += DSA_SANDBOX_TAG_LEN;
+ master_priv->recv_packet_length[i] = len;
+ master_priv->recv_packets++;
+
+ return 0;
+}
+
+static int dsa_sandbox_probe(struct udevice *dev)
+{
+ struct dsa_sandbox_priv *priv = dev_get_priv(dev);
+ struct udevice *master = dsa_get_master(dev);
+ struct eth_sandbox_priv *master_priv;
+
+ if (!master)
+ return -ENODEV;
+
+ dsa_set_tagging(dev, DSA_SANDBOX_TAG_LEN, 0);
+
+ master_priv = dev_get_priv(master);
+ master_priv->priv = dev;
+ master_priv->tx_handler = sb_dsa_handler;
+
+ priv->master_priv = master_priv;
+
+ return 0;
+}
+
+static const struct udevice_id dsa_sandbox_ids[] = {
+ { .compatible = "sandbox,dsa" },
+ { }
+};
+
+U_BOOT_DRIVER(dsa_sandbox) = {
+ .name = "dsa_sandbox",
+ .id = UCLASS_DSA,
+ .of_match = dsa_sandbox_ids,
+ .probe = dsa_sandbox_probe,
+ .ops = &dsa_sandbox_ops,
+ .priv_auto = sizeof(struct dsa_sandbox_priv),
+};
diff --git a/drivers/net/dwmac_meson8b.c b/drivers/net/dwmac_meson8b.c
new file mode 100644
index 00000000000..c0b6ef49942
--- /dev/null
+++ b/drivers/net/dwmac_meson8b.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 BayLibre, SAS
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <phy.h>
+#include "designware.h"
+#include <dm/device_compat.h>
+#include <linux/err.h>
+
+#define ETH_REG_0 0x0
+#define ETH_REG_1 0x4
+#define ETH_REG_2 0x18
+#define ETH_REG_3 0x1c
+
+#define GX_ETH_REG_0_PHY_INTF BIT(0)
+#define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
+#define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
+#define GX_ETH_REG_0_PHY_CLK_EN BIT(10)
+#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11)
+#define GX_ETH_REG_0_CLK_EN BIT(12)
+
+#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0)
+#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2)
+#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
+#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
+#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10)
+#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11)
+#define AXG_ETH_REG_0_CLK_EN BIT(12)
+
+struct dwmac_meson8b_plat {
+ struct dw_eth_pdata dw_eth_pdata;
+ int (*dwmac_setup)(struct udevice *dev, struct eth_pdata *edata);
+ void *regs;
+};
+
+static int dwmac_meson8b_of_to_plat(struct udevice *dev)
+{
+ struct dwmac_meson8b_plat *pdata = dev_get_plat(dev);
+
+ pdata->regs = (void *)dev_read_addr_index(dev, 1);
+ if ((fdt_addr_t)pdata->regs == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ pdata->dwmac_setup = (void *)dev_get_driver_data(dev);
+ if (!pdata->dwmac_setup)
+ return -EINVAL;
+
+ return designware_eth_of_to_plat(dev);
+}
+
+static int dwmac_setup_axg(struct udevice *dev, struct eth_pdata *edata)
+{
+ struct dwmac_meson8b_plat *plat = dev_get_plat(dev);
+
+ switch (edata->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* Set RGMII mode */
+ setbits_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
+ AXG_ETH_REG_0_TX_PHASE(1) |
+ AXG_ETH_REG_0_TX_RATIO(4) |
+ AXG_ETH_REG_0_PHY_CLK_EN |
+ AXG_ETH_REG_0_CLK_EN);
+ break;
+
+ case PHY_INTERFACE_MODE_RMII:
+ /* Set RMII mode */
+ out_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
+ AXG_ETH_REG_0_INVERT_RMII_CLK |
+ AXG_ETH_REG_0_CLK_EN);
+ break;
+ default:
+ dev_err(dev, "Unsupported PHY mode\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int dwmac_setup_gx(struct udevice *dev, struct eth_pdata *edata)
+{
+ struct dwmac_meson8b_plat *plat = dev_get_plat(dev);
+
+ switch (edata->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* Set RGMII mode */
+ setbits_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
+ GX_ETH_REG_0_TX_PHASE(1) |
+ GX_ETH_REG_0_TX_RATIO(4) |
+ GX_ETH_REG_0_PHY_CLK_EN |
+ GX_ETH_REG_0_CLK_EN);
+
+ break;
+
+ case PHY_INTERFACE_MODE_RMII:
+ /* Set RMII mode */
+ out_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
+ GX_ETH_REG_0_CLK_EN);
+
+ if (!IS_ENABLED(CONFIG_MESON_GXBB))
+ writel(0x10110181, plat->regs + ETH_REG_2);
+
+ break;
+ default:
+ dev_err(dev, "Unsupported PHY mode\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int dwmac_meson8b_probe(struct udevice *dev)
+{
+ struct dwmac_meson8b_plat *pdata = dev_get_plat(dev);
+ struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata;
+ int ret;
+
+ ret = pdata->dwmac_setup(dev, edata);
+ if (ret)
+ return ret;
+
+ return designware_eth_probe(dev);
+}
+
+static const struct udevice_id dwmac_meson8b_ids[] = {
+ { .compatible = "amlogic,meson-gxbb-dwmac", .data = (ulong)dwmac_setup_gx },
+ { .compatible = "amlogic,meson-axg-dwmac", .data = (ulong)dwmac_setup_axg },
+ { }
+};
+
+U_BOOT_DRIVER(dwmac_meson8b) = {
+ .name = "dwmac_meson8b",
+ .id = UCLASS_ETH,
+ .of_match = dwmac_meson8b_ids,
+ .of_to_plat = dwmac_meson8b_of_to_plat,
+ .probe = dwmac_meson8b_probe,
+ .ops = &designware_eth_ops,
+ .priv_auto = sizeof(struct dw_eth_dev),
+ .plat_auto = sizeof(struct dwmac_meson8b_plat),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index e10db710e6e..b4ede61113f 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -20,14 +20,12 @@ obj-$(CONFIG_ARCH_P1023) += p1023.o
obj-$(CONFIG_ARCH_P2041) += p5020.o
obj-$(CONFIG_ARCH_P3041) += p5020.o
obj-$(CONFIG_ARCH_P4080) += p4080.o
-obj-$(CONFIG_ARCH_P5020) += p5020.o
obj-$(CONFIG_ARCH_P5040) += p5040.o
obj-$(CONFIG_ARCH_T1040) += t1040.o
obj-$(CONFIG_ARCH_T1042) += t1040.o
obj-$(CONFIG_ARCH_T1023) += t1024.o
obj-$(CONFIG_ARCH_T1024) += t1024.o
obj-$(CONFIG_ARCH_T2080) += t2080.o
-obj-$(CONFIG_ARCH_T2081) += t2080.o
obj-$(CONFIG_ARCH_T4240) += t4240.o
obj-$(CONFIG_ARCH_T4160) += t4240.o
obj-$(CONFIG_ARCH_B4420) += b4860.o
diff --git a/drivers/net/mdio_mux_meson_g12a.c b/drivers/net/mdio_mux_meson_g12a.c
new file mode 100644
index 00000000000..b520bf98f06
--- /dev/null
+++ b/drivers/net/mdio_mux_meson_g12a.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2021 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <linux/bitfield.h>
+
+#define ETH_PLL_STS 0x40
+#define ETH_PLL_CTL0 0x44
+#define PLL_CTL0_LOCK_DIG BIT(30)
+#define PLL_CTL0_RST BIT(29)
+#define PLL_CTL0_EN BIT(28)
+#define PLL_CTL0_SEL BIT(23)
+#define PLL_CTL0_N GENMASK(14, 10)
+#define PLL_CTL0_M GENMASK(8, 0)
+#define PLL_LOCK_TIMEOUT 1000000
+#define PLL_MUX_NUM_PARENT 2
+#define ETH_PLL_CTL1 0x48
+#define ETH_PLL_CTL2 0x4c
+#define ETH_PLL_CTL3 0x50
+#define ETH_PLL_CTL4 0x54
+#define ETH_PLL_CTL5 0x58
+#define ETH_PLL_CTL6 0x5c
+#define ETH_PLL_CTL7 0x60
+
+#define ETH_PHY_CNTL0 0x80
+#define EPHY_G12A_ID 0x33010180
+#define ETH_PHY_CNTL1 0x84
+#define PHY_CNTL1_ST_MODE GENMASK(2, 0)
+#define PHY_CNTL1_ST_PHYADD GENMASK(7, 3)
+#define EPHY_DFLT_ADD 8
+#define PHY_CNTL1_MII_MODE GENMASK(15, 14)
+#define EPHY_MODE_RMII 0x1
+#define PHY_CNTL1_CLK_EN BIT(16)
+#define PHY_CNTL1_CLKFREQ BIT(17)
+#define PHY_CNTL1_PHY_ENB BIT(18)
+#define ETH_PHY_CNTL2 0x88
+#define PHY_CNTL2_USE_INTERNAL BIT(5)
+#define PHY_CNTL2_SMI_SRC_MAC BIT(6)
+#define PHY_CNTL2_RX_CLK_EPHY BIT(9)
+
+#define MESON_G12A_MDIO_EXTERNAL_ID 0
+#define MESON_G12A_MDIO_INTERNAL_ID 1
+
+struct mdio_mux_meson_g12a_priv {
+ struct udevice *chip;
+ phys_addr_t phys;
+};
+
+static int meson_g12a_ephy_pll_init(struct mdio_mux_meson_g12a_priv *priv)
+{
+ /* Fire up the PHY PLL */
+ writel(0x29c0040a, priv->phys + ETH_PLL_CTL0);
+ writel(0x927e0000, priv->phys + ETH_PLL_CTL1);
+ writel(0xac5f49e5, priv->phys + ETH_PLL_CTL2);
+ writel(0x00000000, priv->phys + ETH_PLL_CTL3);
+ writel(0x00000000, priv->phys + ETH_PLL_CTL4);
+ writel(0x20200000, priv->phys + ETH_PLL_CTL5);
+ writel(0x0000c002, priv->phys + ETH_PLL_CTL6);
+ writel(0x00000023, priv->phys + ETH_PLL_CTL7);
+ writel(0x39c0040a, priv->phys + ETH_PLL_CTL0);
+ writel(0x19c0040a, priv->phys + ETH_PLL_CTL0);
+
+ return 0;
+}
+
+static int meson_g12a_enable_internal_mdio(struct mdio_mux_meson_g12a_priv *priv)
+{
+ /* Initialize ephy control */
+ writel(EPHY_G12A_ID, priv->phys + ETH_PHY_CNTL0);
+ writel(FIELD_PREP(PHY_CNTL1_ST_MODE, 3) |
+ FIELD_PREP(PHY_CNTL1_ST_PHYADD, EPHY_DFLT_ADD) |
+ FIELD_PREP(PHY_CNTL1_MII_MODE, EPHY_MODE_RMII) |
+ PHY_CNTL1_CLK_EN |
+ PHY_CNTL1_CLKFREQ |
+ PHY_CNTL1_PHY_ENB,
+ priv->phys + ETH_PHY_CNTL1);
+ writel(PHY_CNTL2_USE_INTERNAL |
+ PHY_CNTL2_SMI_SRC_MAC |
+ PHY_CNTL2_RX_CLK_EPHY,
+ priv->phys + ETH_PHY_CNTL2);
+
+ return 0;
+}
+
+static int meson_g12a_enable_external_mdio(struct mdio_mux_meson_g12a_priv *priv)
+{
+ /* Reset the mdio bus mux */
+ writel(0x0, priv->phys + ETH_PHY_CNTL2);
+
+ return 0;
+}
+
+static int mdio_mux_meson_g12a_select(struct udevice *mux, int cur, int sel)
+{
+ struct mdio_mux_meson_g12a_priv *priv = dev_get_priv(mux);
+
+ debug("%s: %x -> %x\n", __func__, (u32)cur, (u32)sel);
+
+ /* if last selection didn't change we're good to go */
+ if (cur == sel)
+ return 0;
+
+ switch (sel) {
+ case MESON_G12A_MDIO_EXTERNAL_ID:
+ return meson_g12a_enable_external_mdio(priv);
+ case MESON_G12A_MDIO_INTERNAL_ID:
+ return meson_g12a_enable_internal_mdio(priv);
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct mdio_mux_ops mdio_mux_meson_g12a_ops = {
+ .select = mdio_mux_meson_g12a_select,
+};
+
+static int mdio_mux_meson_g12a_probe(struct udevice *dev)
+{
+ struct mdio_mux_meson_g12a_priv *priv = dev_get_priv(dev);
+
+ priv->phys = dev_read_addr(dev);
+
+ meson_g12a_ephy_pll_init(priv);
+
+ return 0;
+}
+
+static const struct udevice_id mdio_mux_meson_g12a_ids[] = {
+ { .compatible = "amlogic,g12a-mdio-mux" },
+ { }
+};
+
+U_BOOT_DRIVER(mdio_mux_meson_g12a) = {
+ .name = "mdio_mux_meson_g12a",
+ .id = UCLASS_MDIO_MUX,
+ .of_match = mdio_mux_meson_g12a_ids,
+ .probe = mdio_mux_meson_g12a_probe,
+ .ops = &mdio_mux_meson_g12a_ops,
+ .priv_auto = sizeof(struct mdio_mux_meson_g12a_priv),
+};
diff --git a/drivers/net/mdio_mux_mmioreg.c b/drivers/net/mdio_mux_mmioreg.c
new file mode 100644
index 00000000000..e1a23e40a26
--- /dev/null
+++ b/drivers/net/mdio_mux_mmioreg.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2021 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Based on linux/drivers/net/phy/mdio-mux-mmioreg.c :
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <miiphy.h>
+#include <linux/io.h>
+
+struct mdio_mux_mmioreg_priv {
+ struct udevice *chip;
+ phys_addr_t phys;
+ unsigned int iosize;
+ unsigned int mask;
+};
+
+static int mdio_mux_mmioreg_select(struct udevice *mux, int cur, int sel)
+{
+ struct mdio_mux_mmioreg_priv *priv = dev_get_priv(mux);
+
+ debug("%s: %x -> %x\n", __func__, (u32)cur, (u32)sel);
+
+ /* if last selection didn't change we're good to go */
+ if (cur == sel)
+ return 0;
+
+ switch (priv->iosize) {
+ case sizeof(u8): {
+ u8 x, y;
+
+ x = ioread8((void *)priv->phys);
+ y = (x & ~priv->mask) | (u32)sel;
+ if (x != y) {
+ iowrite8((x & ~priv->mask) | sel, (void *)priv->phys);
+ debug("%s: %02x -> %02x\n", __func__, x, y);
+ }
+
+ break;
+ }
+ case sizeof(u16): {
+ u16 x, y;
+
+ x = ioread16((void *)priv->phys);
+ y = (x & ~priv->mask) | (u32)sel;
+ if (x != y) {
+ iowrite16((x & ~priv->mask) | sel, (void *)priv->phys);
+ debug("%s: %04x -> %04x\n", __func__, x, y);
+ }
+
+ break;
+ }
+ case sizeof(u32): {
+ u32 x, y;
+
+ x = ioread32((void *)priv->phys);
+ y = (x & ~priv->mask) | (u32)sel;
+ if (x != y) {
+ iowrite32((x & ~priv->mask) | sel, (void *)priv->phys);
+ debug("%s: %08x -> %08x\n", __func__, x, y);
+ }
+
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static const struct mdio_mux_ops mdio_mux_mmioreg_ops = {
+ .select = mdio_mux_mmioreg_select,
+};
+
+static int mdio_mux_mmioreg_probe(struct udevice *dev)
+{
+ struct mdio_mux_mmioreg_priv *priv = dev_get_priv(dev);
+ phys_addr_t reg_base, reg_size;
+ u32 reg_mask;
+ int err;
+
+ reg_base = ofnode_get_addr_size_index(dev_ofnode(dev), 0, &reg_size);
+ if (reg_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ if (reg_size != sizeof(u8) &&
+ reg_size != sizeof(u16) &&
+ reg_size != sizeof(u32)) {
+ printf("%s: only 8/16/32-bit registers are supported\n", __func__);
+ return -EINVAL;
+ }
+
+ err = dev_read_u32(dev, "mux-mask", &reg_mask);
+ if (err) {
+ debug("%s: error reading mux-mask property\n", __func__);
+ return err;
+ }
+
+ if (reg_mask >= BIT(reg_size * 8)) {
+ printf("%s: mask doesn't fix in register width\n", __func__);
+ return -EINVAL;
+ }
+
+ priv->phys = reg_base;
+ priv->iosize = reg_size;
+ priv->mask = reg_mask;
+
+ debug("%s: %llx@%lld / %x\n", __func__, reg_base, reg_size, reg_mask);
+
+ return 0;
+}
+
+static const struct udevice_id mdio_mux_mmioreg_ids[] = {
+ { .compatible = "mdio-mux-mmioreg" },
+ { }
+};
+
+U_BOOT_DRIVER(mdio_mux_mmioreg) = {
+ .name = "mdio_mux_mmioreg",
+ .id = UCLASS_MDIO_MUX,
+ .of_match = mdio_mux_mmioreg_ids,
+ .probe = mdio_mux_mmioreg_probe,
+ .ops = &mdio_mux_mmioreg_ops,
+ .priv_auto = sizeof(struct mdio_mux_mmioreg_priv),
+};
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index d69503067d8..070ffa82cb9 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -292,6 +292,7 @@ config PHY_XILINX
config PHY_XILINX_GMII2RGMII
bool "Xilinx GMII to RGMII Ethernet PHYs support"
+ depends on DM_ETH
help
This adds support for Xilinx GMII to RGMII IP core. This IP acts
as bridge between MAC connected over GMII and external phy that
diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c
index 1a38c29469a..1192915ee52 100644
--- a/drivers/net/phy/fixed.c
+++ b/drivers/net/phy/fixed.c
@@ -15,18 +15,42 @@
DECLARE_GLOBAL_DATA_PTR;
-int fixedphy_probe(struct phy_device *phydev)
+static int fixedphy_probe(struct phy_device *phydev)
{
+ /* fixed-link phy must not be reset by core phy code */
+ phydev->flags |= PHY_FLAG_BROKEN_RESET;
+
+ return 0;
+}
+
+static int fixedphy_config(struct phy_device *phydev)
+{
+ ofnode node = phy_get_ofnode(phydev);
struct fixed_link *priv;
- int ofnode = phydev->addr;
+ bool old_binding = false;
+ u32 old_val[5];
u32 val;
+ if (!ofnode_valid(node))
+ return -EINVAL;
+
/* check for mandatory properties within fixed-link node */
- val = fdt_getprop_u32_default_node(gd->fdt_blob,
- ofnode, 0, "speed", 0);
+ val = ofnode_read_u32_default(node, "speed", 0);
+
+ if (!val) {
+ /* try old binding */
+ old_binding = true;
+ if (ofnode_read_u32_array(node, "fixed-link", old_val,
+ ARRAY_SIZE(old_val))) {
+ printf("ERROR: no/invalid <fixed-link> property!\n");
+ return -ENOENT;
+ }
+ val = old_val[2];
+ }
+
if (val != SPEED_10 && val != SPEED_100 && val != SPEED_1000 &&
val != SPEED_2500 && val != SPEED_10000) {
- printf("ERROR: no/invalid speed given in fixed-link node!");
+ printf("ERROR: no/invalid speed given in fixed-link node!\n");
return -EINVAL;
}
@@ -38,17 +62,20 @@ int fixedphy_probe(struct phy_device *phydev)
phydev->priv = priv;
priv->link_speed = val;
- priv->duplex = fdtdec_get_bool(gd->fdt_blob, ofnode, "full-duplex");
- priv->pause = fdtdec_get_bool(gd->fdt_blob, ofnode, "pause");
- priv->asym_pause = fdtdec_get_bool(gd->fdt_blob, ofnode, "asym-pause");
-
- /* fixed-link phy must not be reset by core phy code */
- phydev->flags |= PHY_FLAG_BROKEN_RESET;
+ if (!old_binding) {
+ priv->duplex = ofnode_read_bool(node, "full-duplex");
+ priv->pause = ofnode_read_bool(node, "pause");
+ priv->asym_pause = ofnode_read_bool(node, "asym-pause");
+ } else {
+ priv->duplex = old_val[1];
+ priv->pause = old_val[3];
+ priv->asym_pause = old_val[4];
+ }
return 0;
}
-int fixedphy_startup(struct phy_device *phydev)
+static int fixedphy_startup(struct phy_device *phydev)
{
struct fixed_link *priv = phydev->priv;
@@ -61,7 +88,7 @@ int fixedphy_startup(struct phy_device *phydev)
return 0;
}
-int fixedphy_shutdown(struct phy_device *phydev)
+static int fixedphy_shutdown(struct phy_device *phydev)
{
return 0;
}
@@ -72,6 +99,7 @@ static struct phy_driver fixedphy_driver = {
.name = "Fixed PHY",
.features = PHY_GBIT_FEATURES | SUPPORTED_MII,
.probe = fixedphy_probe,
+ .config = fixedphy_config,
.startup = fixedphy_startup,
.shutdown = fixedphy_shutdown,
};
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 89e3076bfd2..dcdef9e661d 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -18,6 +18,7 @@
#include <phy.h>
#include <errno.h>
#include <asm/global_data.h>
+#include <dm/of_extra.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
@@ -942,34 +943,25 @@ void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev)
}
#ifdef CONFIG_PHY_XILINX_GMII2RGMII
-#ifdef CONFIG_DM_ETH
static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
struct udevice *dev,
phy_interface_t interface)
-#else
-static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
- struct eth_device *dev,
- phy_interface_t interface)
-#endif
{
struct phy_device *phydev = NULL;
- int sn = dev_of_offset(dev);
- int off;
-
- while (sn > 0) {
- off = fdt_node_offset_by_compatible(gd->fdt_blob, sn,
- "xlnx,gmii-to-rgmii-1.0");
- if (off > 0) {
- phydev = phy_device_create(bus, off,
+ ofnode node = dev_ofnode(dev);
+
+ while (ofnode_valid(node)) {
+ node = ofnode_by_compatible(node, "xlnx,gmii-to-rgmii-1.0");
+ if (ofnode_valid(node)) {
+ phydev = phy_device_create(bus, 0,
PHY_GMII2RGMII_ID, false,
interface);
+ if (phydev)
+ phydev->node = node;
break;
}
- if (off == -FDT_ERR_NOTFOUND)
- sn = fdt_first_subnode(gd->fdt_blob, sn);
- else
- printf("%s: Error finding compat string:%d\n",
- __func__, off);
+
+ node = ofnode_first_subnode(node);
}
return phydev;
@@ -988,6 +980,7 @@ static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
struct phy_device *fixed_phy_create(ofnode node)
{
phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
+ struct phy_device *phydev;
const char *if_str;
ofnode subnode;
@@ -1004,33 +997,25 @@ struct phy_device *fixed_phy_create(ofnode node)
return NULL;
}
- return phy_device_create(NULL, ofnode_to_offset(subnode), PHY_FIXED_ID,
- false, interface);
+ phydev = phy_device_create(NULL, 0, PHY_FIXED_ID, false, interface);
+ if (phydev)
+ phydev->node = subnode;
+
+ return phydev;
}
-#ifdef CONFIG_DM_ETH
static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
struct udevice *dev,
phy_interface_t interface)
-#else
-static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
- struct eth_device *dev,
- phy_interface_t interface)
-#endif
{
+ ofnode node = dev_ofnode(dev), subnode;
struct phy_device *phydev = NULL;
- int sn;
- const char *name;
-
- sn = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev));
- while (sn > 0) {
- name = fdt_get_name(gd->fdt_blob, sn, NULL);
- if (name && strcmp(name, "fixed-link") == 0) {
- phydev = phy_device_create(bus, sn, PHY_FIXED_ID, false,
- interface);
- break;
- }
- sn = fdt_next_subnode(gd->fdt_blob, sn);
+
+ if (ofnode_phy_is_fixed_link(node, &subnode)) {
+ phydev = phy_device_create(bus, 0, PHY_FIXED_ID,
+ false, interface);
+ if (phydev)
+ phydev->node = subnode;
}
return phydev;
diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c
index 74105c0b7d6..635c0570efe 100644
--- a/drivers/net/phy/xilinx_gmii2rgmii.c
+++ b/drivers/net/phy/xilinx_gmii2rgmii.c
@@ -18,9 +18,38 @@ DECLARE_GLOBAL_DATA_PTR;
static int xilinxgmiitorgmii_config(struct phy_device *phydev)
{
- struct phy_device *ext_phydev = phydev->priv;
+ ofnode node = phy_get_ofnode(phydev);
+ struct phy_device *ext_phydev;
+ struct ofnode_phandle_args phandle;
+ int ext_phyaddr = -1;
+ int ret;
debug("%s\n", __func__);
+
+ if (!ofnode_valid(node))
+ return -EINVAL;
+
+ phydev->addr = ofnode_read_u32_default(node, "reg", -1);
+ ret = ofnode_parse_phandle_with_args(node, "phy-handle",
+ NULL, 0, 0, &phandle);
+ if (ret)
+ return ret;
+
+ ext_phyaddr = ofnode_read_u32_default(phandle.node, "reg", -1);
+ ext_phydev = phy_find_by_mask(phydev->bus,
+ 1 << ext_phyaddr,
+ PHY_INTERFACE_MODE_RGMII);
+ if (!ext_phydev) {
+ printf("%s, No external phy device found\n", __func__);
+ return -EINVAL;
+ }
+
+ ext_phydev->node = phandle.node;
+ phydev->priv = ext_phydev;
+
+ debug("%s, gmii2rgmmi:0x%x, extphy:0x%x\n", __func__, phydev->addr,
+ ext_phyaddr);
+
if (ext_phydev->drv->config)
ext_phydev->drv->config(ext_phydev);
@@ -83,11 +112,6 @@ static int xilinxgmiitorgmii_startup(struct phy_device *phydev)
static int xilinxgmiitorgmii_probe(struct phy_device *phydev)
{
- int ofnode = phydev->addr;
- u32 phy_of_handle;
- int ext_phyaddr = -1;
- struct phy_device *ext_phydev;
-
debug("%s\n", __func__);
if (phydev->interface != PHY_INTERFACE_MODE_GMII) {
@@ -95,31 +119,6 @@ static int xilinxgmiitorgmii_probe(struct phy_device *phydev)
return -EINVAL;
}
- /*
- * Read the phy address again as the one we read in ethernet driver
- * was overwritten for the purpose of storing the ofnode
- */
- phydev->addr = fdtdec_get_int(gd->fdt_blob, ofnode, "reg", -1);
- phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, ofnode,
- "phy-handle");
- if (phy_of_handle > 0)
- ext_phyaddr = fdtdec_get_int(gd->fdt_blob,
- phy_of_handle,
- "reg", -1);
- ext_phydev = phy_find_by_mask(phydev->bus,
- 1 << ext_phyaddr,
- PHY_INTERFACE_MODE_RGMII);
- if (!ext_phydev) {
- printf("%s, No external phy device found\n", __func__);
- return -EINVAL;
- }
-
- ext_phydev->node = offset_to_ofnode(phy_of_handle);
- phydev->priv = ext_phydev;
-
- debug("%s, gmii2rgmmi:0x%x, extphy:0x%x\n", __func__, phydev->addr,
- ext_phyaddr);
-
phydev->flags |= PHY_FLAG_BROKEN_RESET;
return 0;
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index ec486893725..c68e4b7fb5e 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -707,11 +707,7 @@ static int init_phy(struct tsec_private *priv)
tsec_configure_serdes(priv);
#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_MDIO)
- if (ofnode_valid(ofnode_find_subnode(dev_ofnode(priv->dev),
- "fixed-link")))
- phydev = phy_connect(NULL, 0, priv->dev, priv->interface);
- else
- phydev = dm_eth_phy_connect(priv->dev);
+ phydev = dm_eth_phy_connect(priv->dev);
#else
phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
priv->interface);
@@ -830,14 +826,40 @@ int tsec_probe(struct udevice *dev)
u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
struct tsec_data *data;
const char *phy_mode;
+ ofnode parent, child;
fdt_addr_t reg;
- ofnode parent;
int ret;
data = (struct tsec_data *)dev_get_driver_data(dev);
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
- priv->regs = dev_remap_addr(dev);
+ if (pdata->iobase == FDT_ADDR_T_NONE) {
+ ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+ if (strncmp(ofnode_get_name(child), "queue-group",
+ strlen("queue-group")))
+ continue;
+
+ reg = ofnode_get_addr(child);
+ if (reg == FDT_ADDR_T_NONE) {
+ printf("No 'reg' property of <queue-group>\n");
+ return -ENOENT;
+ }
+ pdata->iobase = reg;
+
+ /*
+ * if there are multiple queue groups,
+ * only the first one is used.
+ */
+ break;
+ }
+
+ if (!ofnode_valid(child)) {
+ printf("No child node for <queue-group>?\n");
+ return -ENOENT;
+ }
+ }
+
+ priv->regs = map_physmem(pdata->iobase, 0, MAP_NOCACHE);
ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
&phandle_args);
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index baf06a2ad89..ff599822673 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -454,14 +454,6 @@ static int zynq_gem_init(struct udevice *dev)
priv->int_pcs) {
nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
ZYNQ_GEM_NWCFG_PCS_SEL;
-#ifdef CONFIG_ARM64
- if (priv->phydev->phy_id != PHY_FIXED_ID)
- writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
- &regs->pcscntrl);
- else
- writel(readl(&regs->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
- &regs->pcscntrl);
-#endif
}
switch (priv->phydev->speed) {
@@ -480,6 +472,23 @@ static int zynq_gem_init(struct udevice *dev)
break;
}
+#ifdef CONFIG_ARM64
+ if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
+ priv->int_pcs) {
+ /*
+ * Disable AN for fixed link configuration, enable otherwise.
+ * Must be written after PCS_SEL is set in nwconfig,
+ * otherwise writes will not take effect.
+ */
+ if (priv->phydev->phy_id != PHY_FIXED_ID)
+ writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
+ &regs->pcscntrl);
+ else
+ writel(readl(&regs->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
+ &regs->pcscntrl);
+ }
+#endif
+
ret = clk_set_rate(&priv->tx_clk, clk_rate);
if (IS_ERR_VALUE(ret)) {
dev_err(dev, "failed to set tx clock rate\n");
generated by cgit v1.2.3 (git 2.0.4) at 2025-09-30 10:24:42 +0000