diff options
Diffstat (limited to 'drivers/net')
171 files changed, 3262 insertions, 239 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index b2d7b499766..69ae7c07508 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -193,6 +193,24 @@ config CALXEDA_XGMAC This driver supports the XGMAC in Calxeda Highbank and Midway machines. +config DWC_ETH_XGMAC + bool "Synopsys DWC Ethernet XGMAC device support" + select PHYLIB + help + This driver supports the Synopsys Designware Ethernet XGMAC (10G + Ethernet MAC) IP block. The IP supports many options for bus type, + clocking/reset structure, and feature list. + +config DWC_ETH_XGMAC_SOCFPGA + bool "Synopsys DWC Ethernet XGMAC device support for SOCFPGA" + select REGMAP + select SYSCON + depends on DWC_ETH_XGMAC + default y if TARGET_SOCFPGA_AGILEX5 + help + The Synopsys Designware Ethernet XGMAC IP block with specific + configuration used in Intel SoC FPGA chip. + config DRIVER_DM9000 bool "Davicom DM9000 controller driver" help @@ -307,6 +325,14 @@ config EEPRO100 This driver supports Intel(R) PRO/100 82557/82559/82559ER fast ethernet family of adapters. +config ESSEDMA + bool "Qualcomm ESS Edma support" + depends on DM_ETH && ARCH_IPQ40XX + select PHYLIB + help + This driver supports ethernet DMA adapter found in + Qualcomm IPQ40xx series SoC-s. + config ETH_SANDBOX depends on SANDBOX default y diff --git a/drivers/net/Makefile b/drivers/net/Makefile index dc3404519d6..425dd721f9d 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -22,11 +22,14 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o +obj-$(CONFIG_DWC_ETH_XGMAC) += dwc_eth_xgmac.o +obj-$(CONFIG_DWC_ETH_XGMAC_SOCFPGA) += dwc_eth_xgmac_socfpga.o obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o obj-$(CONFIG_DWC_ETH_QOS_STM32) += dwc_eth_qos_stm32.o obj-$(CONFIG_E1000) += e1000.o obj-$(CONFIG_E1000_SPI) += e1000_spi.o obj-$(CONFIG_EEPRO100) += eepro100.o +obj-$(CONFIG_ESSEDMA) += essedma.o obj-$(CONFIG_ETHOC) += ethoc.o obj-$(CONFIG_ETH_DESIGNWARE) += designware.o obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c index da1f3f45808..059a65d4661 100644 --- a/drivers/net/ag7xxx.c +++ b/drivers/net/ag7xxx.c @@ -6,7 +6,6 @@ * Copyright (C) 2019 Rosy Song <rosysong@rosinson.com> */ -#include <common.h> #include <clock_legacy.h> #include <cpu_func.h> #include <dm.h> diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c index e2340936fa6..c57aafd0026 100644 --- a/drivers/net/altera_tse.c +++ b/drivers/net/altera_tse.c @@ -8,7 +8,6 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <errno.h> diff --git a/drivers/net/aspeed_mdio.c b/drivers/net/aspeed_mdio.c index a99715a7282..f2e4392aa9a 100644 --- a/drivers/net/aspeed_mdio.c +++ b/drivers/net/aspeed_mdio.c @@ -7,7 +7,6 @@ * This file is inspired from the Linux kernel driver drivers/net/phy/mdio-aspeed.c */ -#include <common.h> #include <dm.h> #include <log.h> #include <miiphy.h> diff --git a/drivers/net/bcm-sf2-eth-gmac.c b/drivers/net/bcm-sf2-eth-gmac.c index cbe1e85222f..ba244b4a26e 100644 --- a/drivers/net/bcm-sf2-eth-gmac.c +++ b/drivers/net/bcm-sf2-eth-gmac.c @@ -11,7 +11,6 @@ #endif #include <config.h> -#include <common.h> #include <cpu_func.h> #include <log.h> #include <malloc.h> diff --git a/drivers/net/bcm-sf2-eth-gmac.h b/drivers/net/bcm-sf2-eth-gmac.h index 477667f4eaa..ac5e45d4f90 100644 --- a/drivers/net/bcm-sf2-eth-gmac.h +++ b/drivers/net/bcm-sf2-eth-gmac.h @@ -18,7 +18,6 @@ #define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100) #define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188) - #define GMAC_DMA_PTR_OFFSET 0x04 #define GMAC_DMA_ADDR_LOW_OFFSET 0x08 #define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c diff --git a/drivers/net/bcm-sf2-eth.c b/drivers/net/bcm-sf2-eth.c index 1524f5c9989..c10719c6b51 100644 --- a/drivers/net/bcm-sf2-eth.c +++ b/drivers/net/bcm-sf2-eth.c @@ -3,7 +3,6 @@ * Copyright 2014 Broadcom Corporation. */ -#include <common.h> #include <log.h> #include <malloc.h> #include <net.h> diff --git a/drivers/net/bcm6348-eth.c b/drivers/net/bcm6348-eth.c index 15a94f6ce9a..f87db4ab46e 100644 --- a/drivers/net/bcm6348-eth.c +++ b/drivers/net/bcm6348-eth.c @@ -6,7 +6,6 @@ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> */ -#include <common.h> #include <clk.h> #include <dm.h> #include <dma.h> diff --git a/drivers/net/bcm6368-eth.c b/drivers/net/bcm6368-eth.c index 9679a45b075..0601fcc42f5 100644 --- a/drivers/net/bcm6368-eth.c +++ b/drivers/net/bcm6368-eth.c @@ -6,7 +6,6 @@ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> */ -#include <common.h> #include <clk.h> #include <dm.h> #include <dma.h> diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c index 4e1f8ed7a4a..a0264dc386d 100644 --- a/drivers/net/bcmgenet.c +++ b/drivers/net/bcmgenet.c @@ -360,6 +360,10 @@ static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet, int length) { struct bcmgenet_eth_priv *priv = dev_get_priv(dev); + void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE; + u32 addr = readl(desc_base + DMA_DESC_ADDRESS_LO); + + flush_dcache_range(addr, addr + RX_BUF_LENGTH); /* Tell the MAC we have consumed that last receive buffer. */ priv->c_index = (priv->c_index + 1) & 0xFFFF; diff --git a/drivers/net/bnxt/bnxt.c b/drivers/net/bnxt/bnxt.c index 1c9a9962408..96e804e8cac 100644 --- a/drivers/net/bnxt/bnxt.c +++ b/drivers/net/bnxt/bnxt.c @@ -3,8 +3,6 @@ * Copyright 2019-2021 Broadcom. */ -#include <common.h> - #include <asm/io.h> #include <dm.h> #include <linux/delay.h> diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c index eb1e2a756cd..ebb399457fb 100644 --- a/drivers/net/calxedaxgmac.c +++ b/drivers/net/calxedaxgmac.c @@ -3,7 +3,6 @@ * Copyright 2010-2011 Calxeda, Inc. */ -#include <common.h> #include <malloc.h> #include <net.h> #include <linux/compiler.h> diff --git a/drivers/net/cortina_ni.c b/drivers/net/cortina_ni.c index ef6ecd88b0c..79026882800 100644 --- a/drivers/net/cortina_ni.c +++ b/drivers/net/cortina_ni.c @@ -7,7 +7,6 @@ * Ethernet MAC Driver for all supported CAxxxx SoCs */ -#include <common.h> #include <command.h> #include <malloc.h> #include <net.h> diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 4e7af95b41c..ce028f451f1 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include <common.h> #include <asm/io.h> #include <dm.h> #include <malloc.h> diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 682045cea2c..07b0f49ef58 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -8,7 +8,6 @@ * Designware ethernet IP driver for U-Boot */ -#include <common.h> #include <clk.h> #include <cpu_func.h> #include <dm.h> diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 918a38615ad..e47101ccaf6 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -64,7 +64,6 @@ struct eth_mac_regs { #define MII_REGMSK (0x1F << 6) #define MII_ADDRMSK (0x1F << 11) - struct eth_dma_regs { u32 busmode; /* 0x00 */ u32 txpolldemand; /* 0x04 */ diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index bec8d67dad0..9e17f0b9c28 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -49,7 +49,6 @@ * TODO: external MII is not functional, only internal at the moment. */ -#include <common.h> #include <command.h> #include <dm.h> #include <malloc.h> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 32a5d52165a..43f0ec7637d 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -29,7 +29,6 @@ #define LOG_CATEGORY UCLASS_ETH -#include <common.h> #include <clk.h> #include <cpu_func.h> #include <dm.h> @@ -51,6 +50,7 @@ #include <asm/arch/clock.h> #include <asm/mach-imx/sys_proto.h> #endif +#include <linux/bitfield.h> #include <linux/delay.h> #include <linux/printk.h> @@ -147,6 +147,25 @@ static int eqos_mdio_wait_idle(struct eqos_priv *eqos) 1000000, true); } +/* Bitmask common for mdio_read and mdio_write */ +#define EQOS_MDIO_BITFIELD(pa, rda, cr) \ + FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_PA_MASK, pa) | \ + FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_RDA_MASK, rda) | \ + FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_CR_MASK, cr) | \ + EQOS_MAC_MDIO_ADDRESS_GB + +static u32 eqos_mdio_bitfield(struct eqos_priv *eqos, int addr, int devad, int reg) +{ + int cr = eqos->config->config_mac_mdio; + bool c22 = devad == MDIO_DEVAD_NONE ? true : false; + + if (c22) + return EQOS_MDIO_BITFIELD(addr, reg, cr); + else + return EQOS_MDIO_BITFIELD(addr, devad, cr) | + EQOS_MAC_MDIO_ADDRESS_C45E; +} + static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, int mdio_reg) { @@ -164,15 +183,17 @@ static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, } val = readl(&eqos->mac_regs->mdio_address); - val &= EQOS_MAC_MDIO_ADDRESS_SKAP | - EQOS_MAC_MDIO_ADDRESS_C45E; - val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | - (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | - (eqos->config->config_mac_mdio << - EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | - (EQOS_MAC_MDIO_ADDRESS_GOC_READ << - EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | - EQOS_MAC_MDIO_ADDRESS_GB; + val &= EQOS_MAC_MDIO_ADDRESS_SKAP; + + val |= eqos_mdio_bitfield(eqos, mdio_addr, mdio_devad, mdio_reg) | + FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_GOC_MASK, + EQOS_MAC_MDIO_ADDRESS_GOC_READ); + + if (val & EQOS_MAC_MDIO_ADDRESS_C45E) { + writel(FIELD_PREP(EQOS_MAC_MDIO_DATA_RA_MASK, mdio_reg), + &eqos->mac_regs->mdio_data); + } + writel(val, &eqos->mac_regs->mdio_address); udelay(eqos->config->mdio_wait); @@ -195,7 +216,8 @@ static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, int mdio_reg, u16 mdio_val) { struct eqos_priv *eqos = bus->priv; - u32 val; + u32 v_addr; + u32 v_data; int ret; debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev, @@ -207,20 +229,19 @@ static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, return ret; } - writel(mdio_val, &eqos->mac_regs->mdio_data); + v_addr = readl(&eqos->mac_regs->mdio_address); + v_addr &= EQOS_MAC_MDIO_ADDRESS_SKAP; - val = readl(&eqos->mac_regs->mdio_address); - val &= EQOS_MAC_MDIO_ADDRESS_SKAP | - EQOS_MAC_MDIO_ADDRESS_C45E; - val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | - (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | - (eqos->config->config_mac_mdio << - EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | - (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE << - EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | - EQOS_MAC_MDIO_ADDRESS_GB; - writel(val, &eqos->mac_regs->mdio_address); + v_addr |= eqos_mdio_bitfield(eqos, mdio_addr, mdio_devad, mdio_reg) | + FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_GOC_MASK, + EQOS_MAC_MDIO_ADDRESS_GOC_WRITE); + + v_data = mdio_val; + if (v_addr & EQOS_MAC_MDIO_ADDRESS_C45E) + v_data |= FIELD_PREP(EQOS_MAC_MDIO_DATA_RA_MASK, mdio_reg); + writel(v_data, &eqos->mac_regs->mdio_data); + writel(v_addr, &eqos->mac_regs->mdio_address); udelay(eqos->config->mdio_wait); ret = eqos_mdio_wait_idle(eqos); diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index 8b3d0d464d3..a06390a6982 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -79,19 +79,20 @@ struct eqos_mac_regs { #define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28 #define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3 -#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21 -#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16 -#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8 +#define EQOS_MAC_MDIO_ADDRESS_PA_MASK GENMASK(25, 21) +#define EQOS_MAC_MDIO_ADDRESS_RDA_MASK GENMASK(20, 16) +#define EQOS_MAC_MDIO_ADDRESS_CR_MASK GENMASK(11, 8) #define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2 #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5 #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4) -#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2 +#define EQOS_MAC_MDIO_ADDRESS_GOC_MASK GENMASK(3, 2) #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3 #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1 #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1) #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0) +#define EQOS_MAC_MDIO_DATA_RA_MASK GENMASK(31, 16) #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff #define EQOS_MTL_REGS_BASE 0xd00 diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c index 9c4e3904413..d6bed278ca7 100644 --- a/drivers/net/dwc_eth_qos_imx.c +++ b/drivers/net/dwc_eth_qos_imx.c @@ -3,7 +3,6 @@ * Copyright 2022 NXP */ -#include <common.h> #include <clk.h> #include <cpu_func.h> #include <dm.h> diff --git a/drivers/net/dwc_eth_qos_qcom.c b/drivers/net/dwc_eth_qos_qcom.c index 8178138fc65..77d626393d5 100644 --- a/drivers/net/dwc_eth_qos_qcom.c +++ b/drivers/net/dwc_eth_qos_qcom.c @@ -5,7 +5,6 @@ * Qcom DWMAC specific glue layer */ -#include <common.h> #include <asm/global_data.h> #include <asm/gpio.h> #include <asm/io.h> diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index fa9e513faea..c4557e57988 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -8,7 +8,6 @@ * part in order to simplify future porting of fixes and support for other SoCs. */ -#include <common.h> #include <clk.h> #include <dm.h> #include <dm/device_compat.h> diff --git a/drivers/net/dwc_eth_qos_starfive.c b/drivers/net/dwc_eth_qos_starfive.c index 5be8ac0f1a5..09e714ce76a 100644 --- a/drivers/net/dwc_eth_qos_starfive.c +++ b/drivers/net/dwc_eth_qos_starfive.c @@ -4,7 +4,6 @@ * Author: Yanhong Wang<yanhong.wang@starfivetech.com> */ -#include <common.h> #include <asm/cache.h> #include <asm/gpio.h> #include <clk.h> diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index fbc08bba1d6..cffaa10b705 100644 --- a/drivers/net/dwc_eth_qos_stm32.c +++ b/drivers/net/dwc_eth_qos_stm32.c @@ -266,6 +266,12 @@ static int eqos_probe_resources_stm32(struct udevice *dev) if (ret) dev_warn(dev, "No phy clock provided %d\n", ret); + /* Get reset gpio pin (optional) */ + ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, + &eqos->phy_reset_gpio, GPIOD_IS_OUT); + if (ret) + pr_warn("No phy reset gpio provided: %d\n", ret); + dev_dbg(dev, "%s: OK\n", __func__); return 0; @@ -277,6 +283,21 @@ err_probe: return ret; } +static int eqos_start_resets_stm32(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { + dm_gpio_set_value(&eqos->phy_reset_gpio, 1); + udelay(2); + dm_gpio_set_value(&eqos->phy_reset_gpio, 0); + } + + return 0; +} + static int eqos_remove_resources_stm32(struct udevice *dev) { dev_dbg(dev, "%s:\n", __func__); @@ -292,7 +313,7 @@ static struct eqos_ops eqos_stm32_ops = { .eqos_probe_resources = eqos_probe_resources_stm32, .eqos_remove_resources = eqos_remove_resources_stm32, .eqos_stop_resets = eqos_null_ops, - .eqos_start_resets = eqos_null_ops, + .eqos_start_resets = eqos_start_resets_stm32, .eqos_stop_clks = eqos_stop_clks_stm32, .eqos_start_clks = eqos_start_clks_stm32, .eqos_calibrate_pads = eqos_null_ops, diff --git a/drivers/net/dwc_eth_xgmac.c b/drivers/net/dwc_eth_xgmac.c new file mode 100644 index 00000000000..d3e5f9255f5 --- /dev/null +++ b/drivers/net/dwc_eth_xgmac.c @@ -0,0 +1,1165 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023, Intel Corporation. + * + * Portions based on U-Boot's dwc_eth_qos.c. + */ + +/* + * This driver supports the Synopsys Designware Ethernet XGMAC (10G Ethernet + * MAC) IP block. The IP supports multiple options for bus type, clocking/ + * reset structure, and feature list. + * + * The driver is written such that generic core logic is kept separate from + * configuration-specific logic. Code that interacts with configuration- + * specific resources is split out into separate functions to avoid polluting + * common code. If/when this driver is enhanced to support multiple + * configurations, the core code should be adapted to call all configuration- + * specific functions through function pointers, with the definition of those + * function pointers being supplied by struct udevice_id xgmac_ids[]'s .data + * field. + * + * This configuration uses an AXI master/DMA bus, an AHB slave/register bus, + * contains the DMA, MTL, and MAC sub-blocks, and supports a single RGMII PHY. + * This configuration also has SW control over all clock and reset signals to + * the HW block. + */ + +#define LOG_CATEGORY UCLASS_ETH + +#include <clk.h> +#include <cpu_func.h> +#include <dm.h> +#include <errno.h> +#include <eth_phy.h> +#include <log.h> +#include <malloc.h> +#include <memalign.h> +#include <miiphy.h> +#include <net.h> +#include <netdev.h> +#include <phy.h> +#include <reset.h> +#include <wait_bit.h> +#include <asm/cache.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <linux/delay.h> +#include "dwc_eth_xgmac.h" + +static void *xgmac_alloc_descs(struct xgmac_priv *xgmac, unsigned int num) +{ + return memalign(ARCH_DMA_MINALIGN, num * xgmac->desc_size); +} + +static void xgmac_free_descs(void *descs) +{ + free(descs); +} + +static struct xgmac_desc *xgmac_get_desc(struct xgmac_priv *xgmac, + unsigned int num, bool rx) +{ + return (rx ? xgmac->rx_descs : xgmac->tx_descs) + + (num * xgmac->desc_size); +} + +void xgmac_inval_desc_generic(void *desc) +{ + unsigned long start; + unsigned long end; + + if (!desc) { + pr_err("%s invalid input buffer\n", __func__); + return; + } + + start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN(start + sizeof(struct xgmac_desc), + ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +} + +void xgmac_flush_desc_generic(void *desc) +{ + unsigned long start; + unsigned long end; + + if (!desc) { + pr_err("%s invalid input buffer\n", __func__); + return; + } + + start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN(start + sizeof(struct xgmac_desc), + ARCH_DMA_MINALIGN); + + flush_dcache_range(start, end); +} + +void xgmac_inval_buffer_generic(void *buf, size_t size) +{ + unsigned long start; + unsigned long end; + + if (!buf) { + pr_err("%s invalid input buffer\n", __func__); + return; + } + + start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)buf + size, + ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +} + +void xgmac_flush_buffer_generic(void *buf, size_t size) +{ + unsigned long start; + unsigned long end; + + if (!buf) { + pr_err("%s invalid input buffer\n", __func__); + return; + } + + start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)buf + size, + ARCH_DMA_MINALIGN); + + flush_dcache_range(start, end); +} + +static int xgmac_mdio_wait_idle(struct xgmac_priv *xgmac) +{ + return wait_for_bit_le32(&xgmac->mac_regs->mdio_data, + XGMAC_MAC_MDIO_ADDRESS_SBUSY, false, + XGMAC_TIMEOUT_100MS, true); +} + +static int xgmac_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, + int mdio_reg) +{ + struct xgmac_priv *xgmac = bus->priv; + u32 val; + u32 hw_addr; + int ret; + + debug("%s(dev=%p, addr=0x%x, reg=%d):\n", __func__, xgmac->dev, mdio_addr, + mdio_reg); + + ret = xgmac_mdio_wait_idle(xgmac); + if (ret) { + pr_err("MDIO not idle at entry: %d\n", ret); + return ret; + } + + /* Set clause 22 format */ + val = BIT(mdio_addr); + writel(val, &xgmac->mac_regs->mdio_clause_22_port); + + hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | + (mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK); + + val = xgmac->config->config_mac_mdio << + XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT; + + val |= XGMAC_MAC_MDIO_ADDRESS_SADDR | + XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_READ | + XGMAC_MAC_MDIO_ADDRESS_SBUSY; + + ret = xgmac_mdio_wait_idle(xgmac); + if (ret) { + pr_err("MDIO not idle at entry: %d\n", ret); + return ret; + } + + writel(hw_addr, &xgmac->mac_regs->mdio_address); + writel(val, &xgmac->mac_regs->mdio_data); + + ret = xgmac_mdio_wait_idle(xgmac); + if (ret) { + pr_err("MDIO read didn't complete: %d\n", ret); + return ret; + } + + val = readl(&xgmac->mac_regs->mdio_data); + val &= XGMAC_MAC_MDIO_DATA_GD_MASK; + + debug("%s: val=0x%x\n", __func__, val); + + return val; +} + +static int xgmac_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, + int mdio_reg, u16 mdio_val) +{ + struct xgmac_priv *xgmac = bus->priv; + u32 val; + u32 hw_addr; + int ret; + + debug("%s(dev=%p, addr=0x%x, reg=%d, val=0x%x):\n", __func__, xgmac->dev, + mdio_addr, mdio_reg, mdio_val); + + ret = xgmac_mdio_wait_idle(xgmac); + if (ret) { + pr_err("MDIO not idle at entry: %d\n", ret); + return ret; + } + + /* Set clause 22 format */ + val = BIT(mdio_addr); + writel(val, &xgmac->mac_regs->mdio_clause_22_port); + + hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | + (mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK); + + hw_addr |= (mdio_reg >> XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) << + XGMAC_MAC_MDIO_ADDRESS_DA_SHIFT; + + val = (xgmac->config->config_mac_mdio << + XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT); + + val |= XGMAC_MAC_MDIO_ADDRESS_SADDR | + mdio_val | XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_WRITE | + XGMAC_MAC_MDIO_ADDRESS_SBUSY; + + ret = xgmac_mdio_wait_idle(xgmac); + if (ret) { + pr_err("MDIO not idle at entry: %d\n", ret); + return ret; + } + + writel(hw_addr, &xgmac->mac_regs->mdio_address); + writel(val, &xgmac->mac_regs->mdio_data); + + ret = xgmac_mdio_wait_idle(xgmac); + if (ret) { + pr_err("MDIO write didn't complete: %d\n", ret); + return ret; + } + + return 0; +} + +static int xgmac_set_full_duplex(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + clrbits_le32(&xgmac->mac_regs->mac_extended_conf, XGMAC_MAC_EXT_CONF_HD); + + return 0; +} + +static int xgmac_set_half_duplex(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + setbits_le32(&xgmac->mac_regs->mac_extended_conf, XGMAC_MAC_EXT_CONF_HD); + + /* WAR: Flush TX queue when switching to half-duplex */ + setbits_le32(&xgmac->mtl_regs->txq0_operation_mode, + XGMAC_MTL_TXQ0_OPERATION_MODE_FTQ); + + return 0; +} + +static int xgmac_set_gmii_speed(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + u32 val; + + debug("%s(dev=%p):\n", __func__, dev); + + val = XGMAC_MAC_CONF_SS_1G_GMII << XGMAC_MAC_CONF_SS_SHIFT; + writel(val, &xgmac->mac_regs->tx_configuration); + + return 0; +} + +static int xgmac_set_mii_speed_100(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + u32 val; + + debug("%s(dev=%p):\n", __func__, dev); + + val = XGMAC_MAC_CONF_SS_100M_MII << XGMAC_MAC_CONF_SS_SHIFT; + writel(val, &xgmac->mac_regs->tx_configuration); + + return 0; +} + +static int xgmac_set_mii_speed_10(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + u32 val; + + debug("%s(dev=%p):\n", __func__, dev); + + val = XGMAC_MAC_CONF_SS_2_10M_MII << XGMAC_MAC_CONF_SS_SHIFT; + writel(val, &xgmac->mac_regs->tx_configuration); + + return 0; +} + +static int xgmac_adjust_link(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + int ret; + bool en_calibration; + + debug("%s(dev=%p):\n", __func__, dev); + + if (xgmac->phy->duplex) + ret = xgmac_set_full_duplex(dev); + else + ret = xgmac_set_half_duplex(dev); + if (ret < 0) { + pr_err("xgmac_set_*_duplex() failed: %d\n", ret); + return ret; + } + + switch (xgmac->phy->speed) { + case SPEED_1000: + en_calibration = true; + ret = xgmac_set_gmii_speed(dev); + break; + case SPEED_100: + en_calibration = true; + ret = xgmac_set_mii_speed_100(dev); + break; + case SPEED_10: + en_calibration = false; + ret = xgmac_set_mii_speed_10(dev); + break; + default: + pr_err("invalid speed %d\n", xgmac->phy->speed); + return -EINVAL; + } + if (ret < 0) { + pr_err("xgmac_set_*mii_speed*() failed: %d\n", ret); + return ret; + } + + if (en_calibration) { + ret = xgmac->config->ops->xgmac_calibrate_pads(dev); + if (ret < 0) { + pr_err("xgmac_calibrate_pads() failed: %d\n", + ret); + return ret; + } + } else { + ret = xgmac->config->ops->xgmac_disable_calibration(dev); + if (ret < 0) { + pr_err("xgmac_disable_calibration() failed: %d\n", + ret); + return ret; + } + } + + return 0; +} + +static int xgmac_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_plat(dev); + struct xgmac_priv *xgmac = dev_get_priv(dev); + u32 val; + + /* + * This function may be called before start() or after stop(). At that + * time, on at least some configurations of the XGMAC HW, all clocks to + * the XGMAC HW block will be stopped, and a reset signal applied. If + * any register access is attempted in this state, bus timeouts or CPU + * hangs may occur. This check prevents that. + * + * A simple solution to this problem would be to not implement + * write_hwaddr(), since start() always writes the MAC address into HW + * anyway. However, it is desirable to implement write_hwaddr() to + * support the case of SW that runs subsequent to U-Boot which expects + * the MAC address to already be programmed into the XGMAC registers, + * which must happen irrespective of whether the U-Boot user (or + * scripts) actually made use of the XGMAC device, and hence + * irrespective of whether start() was ever called. + * + */ + if (!xgmac->config->reg_access_always_ok && !xgmac->reg_access_ok) + return 0; + + /* Update the MAC address */ + val = (plat->enetaddr[5] << 8) | + (plat->enetaddr[4]); + writel(val, &xgmac->mac_regs->address0_high); + val = (plat->enetaddr[3] << 24) | + (plat->enetaddr[2] << 16) | + (plat->enetaddr[1] << 8) | + (plat->enetaddr[0]); + writel(val, &xgmac->mac_regs->address0_low); + return 0; +} + +static int xgmac_read_rom_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct xgmac_priv *xgmac = dev_get_priv(dev); + int ret; + + ret = xgmac->config->ops->xgmac_get_enetaddr(dev); + if (ret < 0) + return ret; + + return !is_valid_ethaddr(pdata->enetaddr); +} + +static int xgmac_get_phy_addr(struct xgmac_priv *priv, struct udevice *dev) +{ + struct ofnode_phandle_args phandle_args; + int reg; + + if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, + &phandle_args)) { + debug("Failed to find phy-handle"); + return -ENODEV; + } + + priv->phy_of_node = phandle_args.node; + + reg = ofnode_read_u32_default(phandle_args.node, "reg", 0); + + return reg; +} + +static int xgmac_start(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + int ret, i; + u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl; + ulong last_rx_desc; + ulong desc_pad; + + struct xgmac_desc *tx_desc = NULL; + struct xgmac_desc *rx_desc = NULL; + int addr = -1; + + debug("%s(dev=%p):\n", __func__, dev); + + xgmac->tx_desc_idx = 0; + xgmac->rx_desc_idx = 0; + + ret = xgmac->config->ops->xgmac_start_resets(dev); + if (ret < 0) { + pr_err("xgmac_start_resets() failed: %d\n", ret); + goto err; + } + + xgmac->reg_access_ok = true; + + ret = wait_for_bit_le32(&xgmac->dma_regs->mode, + XGMAC_DMA_MODE_SWR, false, + xgmac->config->swr_wait, false); + if (ret) { + pr_err("XGMAC_DMA_MODE_SWR stuck: %d\n", ret); + goto err_stop_resets; + } + + ret = xgmac->config->ops->xgmac_calibrate_pads(dev); + if (ret < 0) { + pr_err("xgmac_calibrate_pads() failed: %d\n", ret); + goto err_stop_resets; + } + + /* + * if PHY was already connected and configured, + * don't need to reconnect/reconfigure again + */ + if (!xgmac->phy) { + addr = xgmac_get_phy_addr(xgmac, dev); + xgmac->phy = phy_connect(xgmac->mii, addr, dev, + xgmac->config->interface(dev)); + if (!xgmac->phy) { + pr_err("phy_connect() failed\n"); + goto err_stop_resets; + } + + if (xgmac->max_speed) { + ret = phy_set_supported(xgmac->phy, xgmac->max_speed); + if (ret) { + pr_err("phy_set_supported() failed: %d\n", ret); + goto err_shutdown_phy; + } + } + + xgmac->phy->node = xgmac->phy_of_node; + ret = phy_config(xgmac->phy); + if (ret < 0) { + pr_err("phy_config() failed: %d\n", ret); + goto err_shutdown_phy; + } + } + + ret = phy_startup(xgmac->phy); + if (ret < 0) { + pr_err("phy_startup() failed: %d\n", ret); + goto err_shutdown_phy; + } + + if (!xgmac->phy->link) { + pr_err("No link\n"); + goto err_shutdown_phy; + } + + ret = xgmac_adjust_link(dev); + if (ret < 0) { + pr_err("xgmac_adjust_link() failed: %d\n", ret); + goto err_shutdown_phy; + } + + /* Configure MTL */ + + /* Enable Store and Forward mode for TX */ + /* Program Tx operating mode */ + setbits_le32(&xgmac->mtl_regs->txq0_operation_mode, + XGMAC_MTL_TXQ0_OPERATION_MODE_TSF | + (XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED << + XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)); + + /* Transmit Queue weight */ + writel(0x10, &xgmac->mtl_regs->txq0_quantum_weight); + + /* Enable Store and Forward mode for RX, since no jumbo frame */ + setbits_le32(&xgmac->mtl_regs->rxq0_operation_mode, + XGMAC_MTL_RXQ0_OPERATION_MODE_RSF); + + /* Transmit/Receive queue fifo size; use all RAM for 1 queue */ + val = readl(&xgmac->mac_regs->hw_feature1); + tx_fifo_sz = (val >> XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & + XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK; + rx_fifo_sz = (val >> XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & + XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK; + + /* + * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting. + * r/tqs is encoded as (n / 256) - 1. + */ + tqs = (128 << tx_fifo_sz) / 256 - 1; + rqs = (128 << rx_fifo_sz) / 256 - 1; + + clrsetbits_le32(&xgmac->mtl_regs->txq0_operation_mode, + XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK << + XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT, + tqs << XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT); + clrsetbits_le32(&xgmac->mtl_regs->rxq0_operation_mode, + XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK << + XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT, + rqs << XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT); + + setbits_le32(&xgmac->mtl_regs->rxq0_operation_mode, + XGMAC_MTL_RXQ0_OPERATION_MODE_EHFC); + + /* Configure MAC */ + clrsetbits_le32(&xgmac->mac_regs->rxq_ctrl0, + XGMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK << + XGMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT, + xgmac->config->config_mac << + XGMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT); + + /* Multicast and Broadcast Queue Enable */ + setbits_le32(&xgmac->mac_regs->rxq_ctrl1, + XGMAC_MAC_RXQ_CTRL1_MCBCQEN); + + /* enable promise mode and receive all mode */ + setbits_le32(&xgmac->mac_regs->mac_packet_filter, + XGMAC_MAC_PACKET_FILTER_RA | + XGMAC_MAC_PACKET_FILTER_PR); + + /* Set TX flow control parameters */ + /* Set Pause Time */ + setbits_le32(&xgmac->mac_regs->q0_tx_flow_ctrl, + XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK << + XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT); + + /* Assign priority for RX flow control */ + clrbits_le32(&xgmac->mac_regs->rxq_ctrl2, + XGMAC_MAC_RXQ_CTRL2_PSRQ0_MASK << + XGMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT); + + /* Enable flow control */ + setbits_le32(&xgmac->mac_regs->q0_tx_flow_ctrl, + XGMAC_MAC_Q0_TX_FLOW_CTRL_TFE); + setbits_le32(&xgmac->mac_regs->rx_flow_ctrl, + XGMAC_MAC_RX_FLOW_CTRL_RFE); + + clrbits_le32(&xgmac->mac_regs->tx_configuration, + XGMAC_MAC_CONF_JD); + + clrbits_le32(&xgmac->mac_regs->rx_configuration, + XGMAC_MAC_CONF_JE | + XGMAC_MAC_CONF_GPSLCE | + XGMAC_MAC_CONF_WD); + + setbits_le32(&xgmac->mac_regs->rx_configuration, + XGMAC_MAC_CONF_ACS | + XGMAC_MAC_CONF_CST); + + ret = xgmac_write_hwaddr(dev); + if (ret < 0) { + pr_err("xgmac_write_hwaddr() failed: %d\n", ret); + goto err; + } + + /* Configure DMA */ + clrsetbits_le32(&xgmac->dma_regs->sysbus_mode, + XGMAC_DMA_SYSBUS_MODE_AAL, + XGMAC_DMA_SYSBUS_MODE_EAME | + XGMAC_DMA_SYSBUS_MODE_UNDEF); + + /* Enable OSP mode */ + setbits_le32(&xgmac->dma_regs->ch0_tx_control, + XGMAC_DMA_CH0_TX_CONTROL_OSP); + + /* RX buffer size. Must be a multiple of bus width */ + clrsetbits_le32(&xgmac->dma_regs->ch0_rx_control, + XGMAC_DMA_CH0_RX_CONTROL_RBSZ_MASK << + XGMAC_DMA_CH0_RX_CONTROL_RBSZ_SHIFT, + XGMAC_MAX_PACKET_SIZE << + XGMAC_DMA_CH0_RX_CONTROL_RBSZ_SHIFT); + + desc_pad = (xgmac->desc_size - sizeof(struct xgmac_desc)) / + xgmac->config->axi_bus_width; + + setbits_le32(&xgmac->dma_regs->ch0_control, + XGMAC_DMA_CH0_CONTROL_PBLX8 | + (desc_pad << XGMAC_DMA_CH0_CONTROL_DSL_SHIFT)); + + /* + * Burst length must be < 1/2 FIFO size. + * FIFO size in tqs is encoded as (n / 256) - 1. + * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes. + * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1. + */ + pbl = tqs + 1; + if (pbl > 32) + pbl = 32; + + clrsetbits_le32(&xgmac->dma_regs->ch0_tx_control, + XGMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK << + XGMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT, + pbl << XGMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT); + + clrsetbits_le32(&xgmac->dma_regs->ch0_rx_control, + XGMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK << + XGMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT, + 8 << XGMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT); + + /* DMA performance configuration */ + val = (XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK << + XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) | + (XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK << + XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT) | + XGMAC_DMA_SYSBUS_MODE_EAME | + XGMAC_DMA_SYSBUS_MODE_BLEN16 | + XGMAC_DMA_SYSBUS_MODE_BLEN8 | + XGMAC_DMA_SYSBUS_MODE_BLEN4 | + XGMAC_DMA_SYSBUS_MODE_BLEN32; + + writel(val, &xgmac->dma_regs->sysbus_mode); + + /* Set up descriptors */ + + memset(xgmac->tx_descs, 0, xgmac->desc_size * XGMAC_DESCRIPTORS_TX); + memset(xgmac->rx_descs, 0, xgmac->desc_size * XGMAC_DESCRIPTORS_RX); + + for (i = 0; i < XGMAC_DESCRIPTORS_TX; i++) { + tx_desc = (struct xgmac_desc *)xgmac_get_desc(xgmac, i, false); + + xgmac->config->ops->xgmac_flush_desc(tx_desc); + } + + for (i = 0; i < XGMAC_DESCRIPTORS_RX; i++) { + rx_desc = (struct xgmac_desc *)xgmac_get_desc(xgmac, i, true); + + rx_desc->des0 = (uintptr_t)(xgmac->rx_dma_buf + + (i * XGMAC_MAX_PACKET_SIZE)); + rx_desc->des3 = XGMAC_DESC3_OWN; + /* Flush the cache to the memory */ + mb(); + xgmac->config->ops->xgmac_flush_desc(rx_desc); + xgmac->config->ops->xgmac_inval_buffer(xgmac->rx_dma_buf + + (i * XGMAC_MAX_PACKET_SIZE), + XGMAC_MAX_PACKET_SIZE); + } + + writel(0, &xgmac->dma_regs->ch0_txdesc_list_haddress); + writel((ulong)xgmac_get_desc(xgmac, 0, false), + &xgmac->dma_regs->ch0_txdesc_list_address); + writel(XGMAC_DESCRIPTORS_TX - 1, + &xgmac->dma_regs->ch0_txdesc_ring_length); + writel(0, &xgmac->dma_regs->ch0_rxdesc_list_haddress); + writel((ulong)xgmac_get_desc(xgmac, 0, true), + &xgmac->dma_regs->ch0_rxdesc_list_address); + writel(XGMAC_DESCRIPTORS_RX - 1, + &xgmac->dma_regs->ch0_rxdesc_ring_length); + + /* Enable everything */ + setbits_le32(&xgmac->dma_regs->ch0_tx_control, + XGMAC_DMA_CH0_TX_CONTROL_ST); + setbits_le32(&xgmac->dma_regs->ch0_rx_control, + XGMAC_DMA_CH0_RX_CONTROL_SR); + setbits_le32(&xgmac->mac_regs->tx_configuration, + XGMAC_MAC_CONF_TE); + setbits_le32(&xgmac->mac_regs->rx_configuration, + XGMAC_MAC_CONF_RE); + + /* TX tail pointer not written until we need to TX a packet */ + /* + * Point RX tail pointer at last descriptor. Ideally, we'd point at the + * first descriptor, implying all descriptors were available. However, + * that's not distinguishable from none of the descriptors being + * available. + */ + last_rx_desc = (ulong)xgmac_get_desc(xgmac, XGMAC_DESCRIPTORS_RX - 1, true); + writel(last_rx_desc, &xgmac->dma_regs->ch0_rxdesc_tail_pointer); + + xgmac->started = true; + + debug("%s: OK\n", __func__); + return 0; + +err_shutdown_phy: + phy_shutdown(xgmac->phy); +err_stop_resets: + xgmac->config->ops->xgmac_stop_resets(dev); +err: + pr_err("FAILED: %d\n", ret); + return ret; +} + +static void xgmac_stop(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + unsigned long start_time; + u32 val; + u32 trcsts; + u32 txqsts; + u32 prxq; + u32 rxqsts; + + debug("%s(dev=%p):\n", __func__, dev); + + if (!xgmac->started) + return; + xgmac->started = false; + xgmac->reg_access_ok = false; + + /* Disable TX DMA */ + clrbits_le32(&xgmac->dma_regs->ch0_tx_control, + XGMAC_DMA_CH0_TX_CONTROL_ST); + + /* Wait for TX all packets to drain out of MTL */ + start_time = get_timer(0); + + while (get_timer(start_time) < XGMAC_TIMEOUT_100MS) { + val = readl(&xgmac->mtl_regs->txq0_debug); + + trcsts = (val >> XGMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) & + XGMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK; + + txqsts = val & XGMAC_MTL_TXQ0_DEBUG_TXQSTS; + + if (trcsts != XGMAC_MTL_TXQ0_DEBUG_TRCSTS_READ_STATE && !txqsts) + break; + } + + /* Turn off MAC TX and RX */ + clrbits_le32(&xgmac->mac_regs->tx_configuration, + XGMAC_MAC_CONF_RE); + clrbits_le32(&xgmac->mac_regs->rx_configuration, + XGMAC_MAC_CONF_RE); + + /* Wait for all RX packets to drain out of MTL */ + start_time = get_timer(0); + + while (get_timer(start_time) < XGMAC_TIMEOUT_100MS) { + val = readl(&xgmac->mtl_regs->rxq0_debug); + + prxq = (val >> XGMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) & + XGMAC_MTL_RXQ0_DEBUG_PRXQ_MASK; + + rxqsts = (val >> XGMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) & + XGMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK; + + if (!prxq && !rxqsts) + break; + } + + /* Turn off RX DMA */ + clrbits_le32(&xgmac->dma_regs->ch0_rx_control, + XGMAC_DMA_CH0_RX_CONTROL_SR); + + if (xgmac->phy) + phy_shutdown(xgmac->phy); + + xgmac->config->ops->xgmac_stop_resets(dev); + + debug("%s: OK\n", __func__); +} + +static int xgmac_send(struct udevice *dev, void *packet, int length) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + struct xgmac_desc *tx_desc; + unsigned long start_time; + + debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet, + length); + + memcpy(xgmac->tx_dma_buf, packet, length); + xgmac->config->ops->xgmac_flush_buffer(xgmac->tx_dma_buf, length); + + tx_desc = xgmac_get_desc(xgmac, xgmac->tx_desc_idx, false); + xgmac->tx_desc_idx++; + xgmac->tx_desc_idx %= XGMAC_DESCRIPTORS_TX; + + tx_desc->des0 = (ulong)xgmac->tx_dma_buf; + tx_desc->des1 = 0; + tx_desc->des2 = length; + /* + * Make sure that if HW sees the _OWN write below, it will see all the + * writes to the rest of the descriptor too. + */ + mb(); + tx_desc->des3 = XGMAC_DESC3_OWN | XGMAC_DESC3_FD | XGMAC_DESC3_LD | length; + xgmac->config->ops->xgmac_flush_desc(tx_desc); + + writel((ulong)xgmac_get_desc(xgmac, xgmac->tx_desc_idx, false), + &xgmac->dma_regs->ch0_txdesc_tail_pointer); + + start_time = get_timer(0); + + while (get_timer(start_time) < XGMAC_TIMEOUT_100MS) { + xgmac->config->ops->xgmac_inval_desc(tx_desc); + if (!(readl(&tx_desc->des3) & XGMAC_DESC3_OWN)) + return 0; + } + debug("%s: TX timeout\n", __func__); + + return -ETIMEDOUT; +} + +static int xgmac_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + struct xgmac_desc *rx_desc; + int length; + + debug("%s(dev=%p, flags=0x%x):\n", __func__, dev, flags); + + rx_desc = xgmac_get_desc(xgmac, xgmac->rx_desc_idx, true); + xgmac->config->ops->xgmac_inval_desc(rx_desc); + if (rx_desc->des3 & XGMAC_DESC3_OWN) { + debug("%s: RX packet not available\n", __func__); + return -EAGAIN; + } + + *packetp = xgmac->rx_dma_buf + + (xgmac->rx_desc_idx * XGMAC_MAX_PACKET_SIZE); + length = rx_desc->des3 & XGMAC_RDES3_PKT_LENGTH_MASK; + debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length); + + xgmac->config->ops->xgmac_inval_buffer(*packetp, length); + + return length; +} + +static int xgmac_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + u32 idx, idx_mask = xgmac->desc_per_cacheline - 1; + uchar *packet_expected; + struct xgmac_desc *rx_desc; + + debug("%s(packet=%p, length=%d)\n", __func__, packet, length); + + packet_expected = xgmac->rx_dma_buf + + (xgmac->rx_desc_idx * XGMAC_MAX_PACKET_SIZE); + if (packet != packet_expected) { + debug("%s: Unexpected packet (expected %p)\n", __func__, + packet_expected); + return -EINVAL; + } + + xgmac->config->ops->xgmac_inval_buffer(packet, length); + + if ((xgmac->rx_desc_idx & idx_mask) == idx_mask) { + for (idx = xgmac->rx_desc_idx - idx_mask; + idx <= xgmac->rx_desc_idx; + idx++) { + rx_desc = xgmac_get_desc(xgmac, idx, true); + rx_desc->des0 = 0; + /* Flush the cache to the memory */ + mb(); + xgmac->config->ops->xgmac_flush_desc(rx_desc); + xgmac->config->ops->xgmac_inval_buffer(packet, length); + rx_desc->des0 = (u32)(ulong)(xgmac->rx_dma_buf + + (idx * XGMAC_MAX_PACKET_SIZE)); + rx_desc->des1 = 0; + rx_desc->des2 = 0; + /* + * Make sure that if HW sees the _OWN write below, + * it will see all the writes to the rest of the + * descriptor too. + */ + mb(); + rx_desc->des3 = XGMAC_DESC3_OWN; + xgmac->config->ops->xgmac_flush_desc(rx_desc); + } + writel((ulong)rx_desc, &xgmac->dma_regs->ch0_rxdesc_tail_pointer); + } + + xgmac->rx_desc_idx++; + xgmac->rx_desc_idx %= XGMAC_DESCRIPTORS_RX; + + return 0; +} + +static int xgmac_probe_resources_core(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + unsigned int desc_step; + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + /* Maximum distance between neighboring descriptors, in Bytes. */ + desc_step = sizeof(struct xgmac_desc); + + if (desc_step < ARCH_DMA_MINALIGN) { + /* + * The hardware implementation cannot place one descriptor + * per cacheline, it is necessary to place multiple descriptors + * per cacheline in memory and do cache management carefully. + */ + xgmac->desc_size = BIT(fls(desc_step) - 1); + } else { + xgmac->desc_size = ALIGN(sizeof(struct xgmac_desc), + (unsigned int)ARCH_DMA_MINALIGN); + } + xgmac->desc_per_cacheline = ARCH_DMA_MINALIGN / xgmac->desc_size; + + xgmac->tx_descs = xgmac_alloc_descs(xgmac, XGMAC_DESCRIPTORS_TX); + if (!xgmac->tx_descs) { + debug("%s: xgmac_alloc_descs(tx) failed\n", __func__); + ret = -ENOMEM; + goto err; + } + + xgmac->rx_descs = xgmac_alloc_descs(xgmac, XGMAC_DESCRIPTORS_RX); + if (!xgmac->rx_descs) { + debug("%s: xgmac_alloc_descs(rx) failed\n", __func__); + ret = -ENOMEM; + goto err_free_tx_descs; + } + + xgmac->tx_dma_buf = memalign(XGMAC_BUFFER_ALIGN, XGMAC_MAX_PACKET_SIZE); + if (!xgmac->tx_dma_buf) { + debug("%s: memalign(tx_dma_buf) failed\n", __func__); + ret = -ENOMEM; + goto err_free_descs; + } + debug("%s: tx_dma_buf=%p\n", __func__, xgmac->tx_dma_buf); + + xgmac->rx_dma_buf = memalign(XGMAC_BUFFER_ALIGN, XGMAC_RX_BUFFER_SIZE); + if (!xgmac->rx_dma_buf) { + debug("%s: memalign(rx_dma_buf) failed\n", __func__); + ret = -ENOMEM; + goto err_free_tx_dma_buf; + } + debug("%s: rx_dma_buf=%p\n", __func__, xgmac->rx_dma_buf); + + xgmac->rx_pkt = malloc(XGMAC_MAX_PACKET_SIZE); + if (!xgmac->rx_pkt) { + debug("%s: malloc(rx_pkt) failed\n", __func__); + ret = -ENOMEM; + goto err_free_rx_dma_buf; + } + debug("%s: rx_pkt=%p\n", __func__, xgmac->rx_pkt); + + xgmac->config->ops->xgmac_inval_buffer(xgmac->rx_dma_buf, + XGMAC_MAX_PACKET_SIZE * XGMAC_DESCRIPTORS_RX); + + debug("%s: OK\n", __func__); + return 0; + +err_free_rx_dma_buf: + free(xgmac->rx_dma_buf); +err_free_tx_dma_buf: + free(xgmac->tx_dma_buf); +err_free_descs: + xgmac_free_descs(xgmac->rx_descs); +err_free_tx_descs: + xgmac_free_descs(xgmac->tx_descs); +err: + + debug("%s: returns %d\n", __func__, ret); + return ret; +} + +static int xgmac_remove_resources_core(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + free(xgmac->rx_pkt); + free(xgmac->rx_dma_buf); + free(xgmac->tx_dma_buf); + xgmac_free_descs(xgmac->rx_descs); + xgmac_free_descs(xgmac->tx_descs); + + debug("%s: OK\n", __func__); + return 0; +} + +/* board-specific Ethernet Interface initializations. */ +__weak int board_interface_eth_init(struct udevice *dev, + phy_interface_t interface_type) +{ + return 0; +} + +static int xgmac_probe(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + xgmac->dev = dev; + xgmac->config = (void *)dev_get_driver_data(dev); + + xgmac->regs = dev_read_addr(dev); + if (xgmac->regs == FDT_ADDR_T_NONE) { + pr_err("dev_read_addr() failed\n"); + return -ENODEV; + } + xgmac->mac_regs = (void *)(xgmac->regs + XGMAC_MAC_REGS_BASE); + xgmac->mtl_regs = (void *)(xgmac->regs + XGMAC_MTL_REGS_BASE); + xgmac->dma_regs = (void *)(xgmac->regs + XGMAC_DMA_REGS_BASE); + + xgmac->max_speed = dev_read_u32_default(dev, "max-speed", 0); + + ret = xgmac_probe_resources_core(dev); + if (ret < 0) { + pr_err("xgmac_probe_resources_core() failed: %d\n", ret); + return ret; + } + + ret = xgmac->config->ops->xgmac_probe_resources(dev); + if (ret < 0) { + pr_err("xgmac_probe_resources() failed: %d\n", ret); + goto err_remove_resources_core; + } + + ret = xgmac->config->ops->xgmac_start_clks(dev); + if (ret < 0) { + pr_err("xgmac_start_clks() failed: %d\n", ret); + return ret; + } + + if (IS_ENABLED(CONFIG_DM_ETH_PHY)) + xgmac->mii = eth_phy_get_mdio_bus(dev); + + if (!xgmac->mii) { + xgmac->mii = mdio_alloc(); + if (!xgmac->mii) { + pr_err("mdio_alloc() failed\n"); + ret = -ENOMEM; + goto err_stop_clks; + } + xgmac->mii->read = xgmac_mdio_read; + xgmac->mii->write = xgmac_mdio_write; + xgmac->mii->priv = xgmac; + strcpy(xgmac->mii->name, dev->name); + + ret = mdio_register(xgmac->mii); + if (ret < 0) { + pr_err("mdio_register() failed: %d\n", ret); + goto err_free_mdio; + } + } + + if (IS_ENABLED(CONFIG_DM_ETH_PHY)) + eth_phy_set_mdio_bus(dev, xgmac->mii); + + debug("%s: OK\n", __func__); + return 0; + +err_free_mdio: + mdio_free(xgmac->mii); +err_stop_clks: + xgmac->config->ops->xgmac_stop_clks(dev); +err_remove_resources_core: + xgmac_remove_resources_core(dev); + + debug("%s: returns %d\n", __func__, ret); + return ret; +} + +static int xgmac_remove(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + mdio_unregister(xgmac->mii); + mdio_free(xgmac->mii); + xgmac->config->ops->xgmac_stop_clks(dev); + xgmac->config->ops->xgmac_remove_resources(dev); + + xgmac_remove_resources_core(dev); + + debug("%s: OK\n", __func__); + return 0; +} + +int xgmac_null_ops(struct udevice *dev) +{ + return 0; +} + +static const struct eth_ops xgmac_ops = { + .start = xgmac_start, + .stop = xgmac_stop, + .send = xgmac_send, + .recv = xgmac_recv, + .free_pkt = xgmac_free_pkt, + .write_hwaddr = xgmac_write_hwaddr, + .read_rom_hwaddr = xgmac_read_rom_hwaddr, +}; + +static const struct udevice_id xgmac_ids[] = { + { + .compatible = "intel,socfpga-dwxgmac", + .data = (ulong)&xgmac_socfpga_config + }, + { } +}; + +U_BOOT_DRIVER(eth_xgmac) = { + .name = "eth_xgmac", + .id = UCLASS_ETH, + .of_match = of_match_ptr(xgmac_ids), + .probe = xgmac_probe, + .remove = xgmac_remove, + .ops = &xgmac_ops, + .priv_auto = sizeof(struct xgmac_priv), + .plat_auto = sizeof(struct eth_pdata), +}; diff --git a/drivers/net/dwc_eth_xgmac.h b/drivers/net/dwc_eth_xgmac.h new file mode 100644 index 00000000000..259f815f3f2 --- /dev/null +++ b/drivers/net/dwc_eth_xgmac.h @@ -0,0 +1,298 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2023 Intel Coporation. + */ + +#include <phy_interface.h> +#include <linux/bitops.h> + +/* Core registers */ + +#define XGMAC_MAC_REGS_BASE 0x000 + +struct xgmac_mac_regs { + u32 tx_configuration; /* 0x000 */ + u32 rx_configuration; /* 0x004 */ + u32 mac_packet_filter; /* 0x008 */ + u32 unused_00c[(0x070 - 0x00c) / 4]; /* 0x00c */ + u32 q0_tx_flow_ctrl; /* 0x070 */ + u32 unused_070[(0x090 - 0x074) / 4]; /* 0x074 */ + u32 rx_flow_ctrl; /* 0x090 */ + u32 unused_094[(0x0a0 - 0x094) / 4]; /* 0x094 */ + u32 rxq_ctrl0; /* 0x0a0 */ + u32 rxq_ctrl1; /* 0x0a4 */ + u32 rxq_ctrl2; /* 0x0a8 */ + u32 unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */ + u32 us_tic_counter; /* 0x0dc */ + u32 unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */ + u32 hw_feature0; /* 0x11c */ + u32 hw_feature1; /* 0x120 */ + u32 hw_feature2; /* 0x124 */ + u32 hw_feature3; /* 0x128 */ + u32 hw_feature4; /* 0x12c */ + u32 unused_130[(0x140 - 0x130) / 4]; /* 0x130 */ + u32 mac_extended_conf; /* 0x140 */ + u32 unused_144[(0x200 - 0x144) / 4]; /* 0x144 */ + u32 mdio_address; /* 0x200 */ + u32 mdio_data; /* 0x204 */ + u32 mdio_cont_write_addr; /* 0x208 */ + u32 mdio_cont_write_data; /* 0x20c */ + u32 mdio_cont_scan_port_enable; /* 0x210 */ + u32 mdio_intr_status; /* 0x214 */ + u32 mdio_intr_enable; /* 0x218 */ + u32 mdio_port_cnct_dsnct_status; /* 0x21c */ + u32 mdio_clause_22_port; /* 0x220 */ + u32 unused_224[(0x300 - 0x224) / 4]; /* 0x224 */ + u32 address0_high; /* 0x300 */ + u32 address0_low; /* 0x304 */ +}; + +#define XGMAC_TIMEOUT_100MS 100000 +#define XGMAC_MAC_CONF_SS_SHIFT 29 +#define XGMAC_MAC_CONF_SS_10G_XGMII 0 +#define XGMAC_MAC_CONF_SS_2_5G_GMII 2 +#define XGMAC_MAC_CONF_SS_1G_GMII 3 +#define XGMAC_MAC_CONF_SS_100M_MII 4 +#define XGMAC_MAC_CONF_SS_5G_XGMII 5 +#define XGMAC_MAC_CONF_SS_2_5G_XGMII 6 +#define XGMAC_MAC_CONF_SS_2_10M_MII 7 + +#define XGMAC_MAC_CONF_JD BIT(16) +#define XGMAC_MAC_CONF_JE BIT(8) +#define XGMAC_MAC_CONF_WD BIT(7) +#define XGMAC_MAC_CONF_GPSLCE BIT(6) +#define XGMAC_MAC_CONF_CST BIT(2) +#define XGMAC_MAC_CONF_ACS BIT(1) +#define XGMAC_MAC_CONF_TE BIT(0) +#define XGMAC_MAC_CONF_RE BIT(0) + +#define XGMAC_MAC_EXT_CONF_HD BIT(24) + +#define XGMAC_MAC_PACKET_FILTER_RA BIT(31) +#define XGMAC_MAC_PACKET_FILTER_PR BIT(0) + +#define XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 +#define XGMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK GENMASK(15, 0) +#define XGMAC_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1) + +#define XGMAC_MAC_RX_FLOW_CTRL_RFE BIT(0) +#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0 +#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK GENMASK(1, 0) +#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0 +#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2 +#define XGMAC_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1 + +#define XGMAC_MAC_RXQ_CTRL1_MCBCQEN BIT(15) + +#define XGMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0 +#define XGMAC_MAC_RXQ_CTRL2_PSRQ0_MASK GENMASK(7, 0) + +#define XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6 +#define XGMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK GENMASK(4, 0) +#define XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0 +#define XGMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK GENMASK(4, 0) + +#define XGMAC_MDIO_SINGLE_CMD_SHIFT 16 +#define XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_READ 3 << XGMAC_MDIO_SINGLE_CMD_SHIFT +#define XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_WRITE BIT(16) +#define XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT 16 +#define XGMAC_MAC_MDIO_ADDRESS_PA_MASK GENMASK(15, 0) +#define XGMAC_MAC_MDIO_ADDRESS_DA_SHIFT 21 +#define XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT 19 +#define XGMAC_MAC_MDIO_ADDRESS_CR_100_150 0 +#define XGMAC_MAC_MDIO_ADDRESS_CR_150_250 1 +#define XGMAC_MAC_MDIO_ADDRESS_CR_250_300 2 +#define XGMAC_MAC_MDIO_ADDRESS_CR_300_350 3 +#define XGMAC_MAC_MDIO_ADDRESS_CR_350_400 4 +#define XGMAC_MAC_MDIO_ADDRESS_CR_400_500 5 +#define XGMAC_MAC_MDIO_ADDRESS_SADDR BIT(18) +#define XGMAC_MAC_MDIO_ADDRESS_SBUSY BIT(22) +#define XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK GENMASK(4, 0) +#define XGMAC_MAC_MDIO_DATA_GD_MASK GENMASK(15, 0) + +/* MTL Registers */ + +#define XGMAC_MTL_REGS_BASE 0x1000 + +struct xgmac_mtl_regs { + u32 mtl_operation_mode; /* 0x1000 */ + u32 unused_1004[(0x1030 - 0x1004) / 4]; /* 0x1004 */ + u32 mtl_rxq_dma_map0; /* 0x1030 */ + u32 mtl_rxq_dma_map1; /* 0x1034 */ + u32 mtl_rxq_dma_map2; /* 0x1038 */ + u32 mtl_rxq_dma_map3; /* 0x103c */ + u32 mtl_tc_prty_map0; /* 0x1040 */ + u32 mtl_tc_prty_map1; /* 0x1044 */ + u32 unused_1048[(0x1100 - 0x1048) / 4]; /* 0x1048 */ + u32 txq0_operation_mode; /* 0x1100 */ + u32 unused_1104; /* 0x1104 */ + u32 txq0_debug; /* 0x1108 */ + u32 unused_100c[(0x1118 - 0x110c) / 4]; /* 0x110c */ + u32 txq0_quantum_weight; /* 0x1118 */ + u32 unused_111c[(0x1140 - 0x111c) / 4]; /* 0x111c */ + u32 rxq0_operation_mode; /* 0x1140 */ + u32 unused_1144; /* 0x1144 */ + u32 rxq0_debug; /* 0x1148 */ +}; + +#define XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16 +#define XGMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK GENMASK(8, 0) +#define XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2 +#define XGMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2 +#define XGMAC_MTL_TXQ0_OPERATION_MODE_TSF BIT(1) +#define XGMAC_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0) + +#define XGMAC_MTL_TXQ0_DEBUG_TXQSTS BIT(4) +#define XGMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1 +#define XGMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK GENMASK(2, 0) +#define XGMAC_MTL_TXQ0_DEBUG_TRCSTS_READ_STATE 0x1 + +#define XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 16 +#define XGMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK GENMASK(9, 0) +#define XGMAC_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7) +#define XGMAC_MTL_RXQ0_OPERATION_MODE_RSF BIT(5) + +#define XGMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16 +#define XGMAC_MTL_RXQ0_DEBUG_PRXQ_MASK GENMASK(14, 0) +#define XGMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4 +#define XGMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK GENMASK(1, 0) + +/* DMA Registers */ + +#define XGMAC_DMA_REGS_BASE 0x3000 + +struct xgmac_dma_regs { + u32 mode; /* 0x3000 */ + u32 sysbus_mode; /* 0x3004 */ + u32 unused_3008[(0x3100 - 0x3008) / 4]; /* 0x3008 */ + u32 ch0_control; /* 0x3100 */ + u32 ch0_tx_control; /* 0x3104 */ + u32 ch0_rx_control; /* 0x3108 */ + u32 slot_func_control_status; /* 0x310c */ + u32 ch0_txdesc_list_haddress; /* 0x3110 */ + u32 ch0_txdesc_list_address; /* 0x3114 */ + u32 ch0_rxdesc_list_haddress; /* 0x3118 */ + u32 ch0_rxdesc_list_address; /* 0x311c */ + u32 unused_3120; /* 0x3120 */ + u32 ch0_txdesc_tail_pointer; /* 0x3124 */ + u32 unused_3128; /* 0x3128 */ + u32 ch0_rxdesc_tail_pointer; /* 0x312c */ + u32 ch0_txdesc_ring_length; /* 0x3130 */ + u32 ch0_rxdesc_ring_length; /* 0x3134 */ + u32 unused_3138[(0x3160 - 0x3138) / 4]; /* 0x3138 */ + u32 ch0_status; /* 0x3160 */ +}; + +#define XGMAC_DMA_MODE_SWR BIT(0) +#define XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT 24 +#define XGMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK GENMASK(4, 0) +#define XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16 +#define XGMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK GENMASK(4, 0) +#define XGMAC_DMA_SYSBUS_MODE_AAL BIT(12) +#define XGMAC_DMA_SYSBUS_MODE_EAME BIT(11) +#define XGMAC_DMA_SYSBUS_MODE_BLEN32 BIT(4) +#define XGMAC_DMA_SYSBUS_MODE_BLEN16 BIT(3) +#define XGMAC_DMA_SYSBUS_MODE_BLEN8 BIT(2) +#define XGMAC_DMA_SYSBUS_MODE_BLEN4 BIT(1) +#define XGMAC_DMA_SYSBUS_MODE_UNDEF BIT(0) + +#define XGMAC_DMA_CH0_CONTROL_DSL_SHIFT 18 +#define XGMAC_DMA_CH0_CONTROL_PBLX8 BIT(16) + +#define XGMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16 +#define XGMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK GENMASK(5, 0) +#define XGMAC_DMA_CH0_TX_CONTROL_OSP BIT(4) +#define XGMAC_DMA_CH0_TX_CONTROL_ST BIT(0) + +#define XGMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16 +#define XGMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK GENMASK(5, 0) +#define XGMAC_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 4 +#define XGMAC_DMA_CH0_RX_CONTROL_RBSZ_MASK GENMASK(10, 0) +#define XGMAC_DMA_CH0_RX_CONTROL_SR BIT(0) + +/* Descriptors */ +#define XGMAC_DESCRIPTORS_TX 8 +#define XGMAC_DESCRIPTORS_RX 8 +#define XGMAC_BUFFER_ALIGN ARCH_DMA_MINALIGN +#define XGMAC_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN) +#define XGMAC_RX_BUFFER_SIZE (XGMAC_DESCRIPTORS_RX * XGMAC_MAX_PACKET_SIZE) + +#define XGMAC_RDES3_PKT_LENGTH_MASK GENMASK(13, 0) + +struct xgmac_desc { + u32 des0; + u32 des1; + u32 des2; + u32 des3; +}; + +#define XGMAC_DESC3_OWN BIT(31) +#define XGMAC_DESC3_FD BIT(29) +#define XGMAC_DESC3_LD BIT(28) + +#define XGMAC_AXI_WIDTH_32 4 +#define XGMAC_AXI_WIDTH_64 8 +#define XGMAC_AXI_WIDTH_128 16 + +struct xgmac_config { + bool reg_access_always_ok; + int swr_wait; + int config_mac; + int config_mac_mdio; + unsigned int axi_bus_width; + phy_interface_t (*interface)(const struct udevice *dev); + struct xgmac_ops *ops; +}; + +struct xgmac_ops { + void (*xgmac_inval_desc)(void *desc); + void (*xgmac_flush_desc)(void *desc); + void (*xgmac_inval_buffer)(void *buf, size_t size); + void (*xgmac_flush_buffer)(void *buf, size_t size); + int (*xgmac_probe_resources)(struct udevice *dev); + int (*xgmac_remove_resources)(struct udevice *dev); + int (*xgmac_stop_resets)(struct udevice *dev); + int (*xgmac_start_resets)(struct udevice *dev); + int (*xgmac_stop_clks)(struct udevice *dev); + int (*xgmac_start_clks)(struct udevice *dev); + int (*xgmac_calibrate_pads)(struct udevice *dev); + int (*xgmac_disable_calibration)(struct udevice *dev); + int (*xgmac_get_enetaddr)(struct udevice *dev); +}; + +struct xgmac_priv { + struct udevice *dev; + const struct xgmac_config *config; + fdt_addr_t regs; + struct xgmac_mac_regs *mac_regs; + struct xgmac_mtl_regs *mtl_regs; + struct xgmac_dma_regs *dma_regs; + struct reset_ctl reset_ctl; + struct reset_ctl_bulk reset_bulk; + struct clk clk_common; + struct mii_dev *mii; + struct phy_device *phy; + ofnode phy_of_node; + void *syscon_phy; + u32 syscon_phy_regshift; + u32 max_speed; + void *tx_descs; + void *rx_descs; + int tx_desc_idx, rx_desc_idx; + unsigned int desc_size; + unsigned int desc_per_cacheline; + void *tx_dma_buf; + void *rx_dma_buf; + void *rx_pkt; + bool started; + bool reg_access_ok; + bool clk_ck_enabled; +}; + +void xgmac_inval_desc_generic(void *desc); +void xgmac_flush_desc_generic(void *desc); +void xgmac_inval_buffer_generic(void *buf, size_t size); +void xgmac_flush_buffer_generic(void *buf, size_t size); +int xgmac_null_ops(struct udevice *dev); + +extern struct xgmac_config xgmac_socfpga_config; diff --git a/drivers/net/dwc_eth_xgmac_socfpga.c b/drivers/net/dwc_eth_xgmac_socfpga.c new file mode 100644 index 00000000000..270c1b0ca6c --- /dev/null +++ b/drivers/net/dwc_eth_xgmac_socfpga.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023, Intel Corporation + */ +#include <clk.h> +#include <cpu_func.h> +#include <dm.h> +#include <errno.h> +#include <eth_phy.h> +#include <log.h> +#include <malloc.h> +#include <memalign.h> +#include <miiphy.h> +#include <net.h> +#include <netdev.h> +#include <phy.h> +#include <reset.h> +#include <wait_bit.h> +#include <asm/arch/secure_reg_helper.h> +#include <asm/arch/system_manager.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/cache.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <linux/delay.h> +#include <dm/device_compat.h> +#include "dwc_eth_xgmac.h" + +#define SOCFPGA_XGMAC_SYSCON_ARG_COUNT 2 + +static int dwxgmac_socfpga_do_setphy(struct udevice *dev, u32 modereg) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + int ret; + + u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << + xgmac->syscon_phy_regshift; + + if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) { + u32 index = ((u64)xgmac->syscon_phy - socfpga_get_sysmgr_addr() - + SYSMGR_SOC64_EMAC0) >> 2; + + u32 id = SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 + index; + + ret = socfpga_secure_reg_update32(id, + modemask, + modereg << + xgmac->syscon_phy_regshift); + if (ret) { + dev_err(dev, "Failed to set PHY register via SMC call\n"); + return ret; + } + + } else { + clrsetbits_le32(xgmac->phy, modemask, modereg); + } + + return 0; +} + +static int xgmac_probe_resources_socfpga(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + struct regmap *reg_map; + struct ofnode_phandle_args args; + void *range; + phy_interface_t interface; + int ret; + u32 modereg; + + interface = xgmac->config->interface(dev); + + switch (interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + break; + case PHY_INTERFACE_MODE_RMII: + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; + break; + case PHY_INTERFACE_MODE_RGMII: + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + break; + default: + dev_err(dev, "Unsupported PHY mode\n"); + return -EINVAL; + } + + /* Get PHY syscon */ + ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL, + SOCFPGA_XGMAC_SYSCON_ARG_COUNT, + 0, &args); + + if (ret) { + dev_err(dev, "Failed to get syscon: %d\n", ret); + return ret; + } + + if (args.args_count != SOCFPGA_XGMAC_SYSCON_ARG_COUNT) { + dev_err(dev, "Invalid number of syscon args\n"); + return -EINVAL; + } + + reg_map = syscon_node_to_regmap(args.node); + if (IS_ERR(reg_map)) { + ret = PTR_ERR(reg_map); + dev_err(dev, "Failed to get reg_map: %d\n", ret); + return ret; + } + + range = regmap_get_range(reg_map, 0); + if (!range) { + dev_err(dev, "Failed to get reg_map: %d\n", ret); + return -ENOMEM; + } + + xgmac->syscon_phy = range + args.args[0]; + xgmac->syscon_phy_regshift = args.args[1]; + + /* Get Reset Bulk */ + ret = reset_get_bulk(dev, &xgmac->reset_bulk); + if (ret) { + dev_err(dev, "Failed to get reset: %d\n", ret); + return ret; + } + + ret = reset_assert_bulk(&xgmac->reset_bulk); + if (ret) { + dev_err(dev, "XGMAC failed to assert reset: %d\n", ret); + return ret; + } + + ret = dwxgmac_socfpga_do_setphy(dev, modereg); + if (ret) + return ret; + + ret = reset_deassert_bulk(&xgmac->reset_bulk); + if (ret) { + dev_err(dev, "XGMAC failed to de-assert reset: %d\n", ret); + return ret; + } + + ret = clk_get_by_name(dev, "stmmaceth", &xgmac->clk_common); + if (ret) { + pr_err("clk_get_by_name(stmmaceth) failed: %d", ret); + goto err_probe; + } + return 0; + +err_probe: + debug("%s: returns %d\n", __func__, ret); + return ret; +} + +static int xgmac_get_enetaddr_socfpga(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct xgmac_priv *xgmac = dev_get_priv(dev); + u32 hi_addr, lo_addr; + + debug("%s(dev=%p):\n", __func__, dev); + + /* Read the MAC Address from the hardawre */ + hi_addr = readl(&xgmac->mac_regs->address0_high); + lo_addr = readl(&xgmac->mac_regs->address0_low); + + pdata->enetaddr[0] = lo_addr & 0xff; + pdata->enetaddr[1] = (lo_addr >> 8) & 0xff; + pdata->enetaddr[2] = (lo_addr >> 16) & 0xff; + pdata->enetaddr[3] = (lo_addr >> 24) & 0xff; + pdata->enetaddr[4] = hi_addr & 0xff; + pdata->enetaddr[5] = (hi_addr >> 8) & 0xff; + + return !is_valid_ethaddr(pdata->enetaddr); +} + +static int xgmac_start_resets_socfpga(struct udevice *dev) +{ + struct xgmac_priv *xgmac = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + ret = reset_assert_bulk(&xgmac->reset_bulk); + if (ret < 0) { + pr_err("xgmac reset assert failed: %d", ret); + return ret; + } + + udelay(2); + + ret = reset_deassert_bulk(&xgmac->reset_bulk); + if (ret < 0) { + pr_err("xgmac reset de-assert failed: %d", ret); + return ret; + } + + return 0; +} + +static struct xgmac_ops xgmac_socfpga_ops = { + .xgmac_inval_desc = xgmac_inval_desc_generic, + .xgmac_flush_desc = xgmac_flush_desc_generic, + .xgmac_inval_buffer = xgmac_inval_buffer_generic, + .xgmac_flush_buffer = xgmac_flush_buffer_generic, + .xgmac_probe_resources = xgmac_probe_resources_socfpga, + .xgmac_remove_resources = xgmac_null_ops, + .xgmac_stop_resets = xgmac_null_ops, + .xgmac_start_resets = xgmac_start_resets_socfpga, + .xgmac_stop_clks = xgmac_null_ops, + .xgmac_start_clks = xgmac_null_ops, + .xgmac_calibrate_pads = xgmac_null_ops, + .xgmac_disable_calibration = xgmac_null_ops, + .xgmac_get_enetaddr = xgmac_get_enetaddr_socfpga, +}; + +struct xgmac_config __maybe_unused xgmac_socfpga_config = { + .reg_access_always_ok = false, + .swr_wait = 50, + .config_mac = XGMAC_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, + .config_mac_mdio = XGMAC_MAC_MDIO_ADDRESS_CR_350_400, + .axi_bus_width = XGMAC_AXI_WIDTH_64, + .interface = dev_read_phy_mode, + .ops = &xgmac_socfpga_ops +}; diff --git a/drivers/net/dwmac_meson8b.c b/drivers/net/dwmac_meson8b.c index 871171e1be5..fde4aabbace 100644 --- a/drivers/net/dwmac_meson8b.c +++ b/drivers/net/dwmac_meson8b.c @@ -3,7 +3,6 @@ * Copyright (C) 2021 BayLibre, SAS */ -#include <common.h> #include <asm/io.h> #include <dm.h> #include <phy.h> diff --git a/drivers/net/dwmac_s700.c b/drivers/net/dwmac_s700.c index 744b58bdd1a..969d247b4f3 100644 --- a/drivers/net/dwmac_s700.c +++ b/drivers/net/dwmac_s700.c @@ -5,7 +5,6 @@ * Actions DWMAC specific glue layer */ -#include <common.h> #include <asm/global_data.h> #include <asm/io.h> #include <dm.h> diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index 82fdff51dac..bba3fc4d34b 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -5,7 +5,6 @@ * Altera SoCFPGA EMAC extras */ -#include <common.h> #include <asm/arch/secure_reg_helper.h> #include <asm/arch/system_manager.h> #include <asm/io.h> diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 4e7ba666770..8f432b8637b 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -7,10 +7,8 @@ tested on both gig copper and gig fiber boards ***************************************************************************/ /******************************************************************************* - Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. - Contact Information: Linux NICS <linux.nics@intel.com> Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 @@ -29,7 +27,6 @@ tested on both gig copper and gig fiber boards * Copyright 2011 Freescale Semiconductor, Inc. */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <dm.h> @@ -108,6 +105,12 @@ static struct pci_device_id e1000_supported[] = { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_K) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_LMVP) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_LM) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_V) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_IT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I226_UNPROGRAMMED) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) }, { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) }, @@ -1569,6 +1572,12 @@ e1000_set_mac_type(struct e1000_hw *hw) case E1000_DEV_ID_ICH8_IGP_M: hw->mac_type = e1000_ich8lan; break; + case PCI_DEVICE_ID_INTEL_I226_K: + case PCI_DEVICE_ID_INTEL_I226_LMVP: + case PCI_DEVICE_ID_INTEL_I226_LM: + case PCI_DEVICE_ID_INTEL_I226_V: + case PCI_DEVICE_ID_INTEL_I226_IT: + case PCI_DEVICE_ID_INTEL_I226_UNPROGRAMMED: case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED: case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED: case PCI_DEVICE_ID_INTEL_I210_COPPER: @@ -1731,7 +1740,6 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw) reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); - switch (hw->mac_type) { case e1000_igb: /* IGB is cool */ return; @@ -2583,7 +2591,6 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) return ret_val; } - } else { if (hw->mac_type == e1000_ich8lan) { @@ -4843,6 +4850,8 @@ static int e1000_set_phy_type (struct e1000_hw *hw) hw->phy_type = e1000_phy_igb; break; case I225_I_PHY_ID: + case I226_LM_PHY_ID: + case I226_I_PHY_ID: hw->phy_type = e1000_phy_igc; break; /* Fall Through */ @@ -4954,6 +4963,10 @@ e1000_detect_gig_phy(struct e1000_hw *hw) match = true; if (hw->phy_id == I225_I_PHY_ID) match = true; + if (hw->phy_id == I226_LM_PHY_ID) + match = true; + if (hw->phy_id == I226_I_PHY_ID) + match = true; break; default: DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); @@ -5199,7 +5212,6 @@ e1000_configure_tx(struct e1000_hw *hw) E1000_WRITE_REG(hw, TARC1, tarc); } - e1000_config_collision_dist(hw); /* Setup Transmit Descriptor Settings for eop descriptor */ hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; @@ -5210,7 +5222,6 @@ e1000_configure_tx(struct e1000_hw *hw) else hw->txd_cmd |= E1000_TXD_CMD_RS; - if (hw->mac_type == e1000_igb) { E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index e1311126a3f..5ca720f4609 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /******************************************************************************* - Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. Copyright 2011 Freescale Semiconductor, Inc. @@ -402,7 +401,6 @@ struct e1000_phy_stats { off */ #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ - #define NUM_DEV_IDS 16 #define NODE_ADDRESS_SIZE 6 @@ -1069,7 +1067,6 @@ typedef enum { e1000_ffe_config_blocked } e1000_ffe_config; - /* Structure containing variables used by the shared code (e1000_hw.c) */ struct e1000_hw { const char *name; @@ -2128,7 +2125,6 @@ struct e1000_hw { /* In-Band Control Register (Page 194, Register 18) */ #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */ - /* Bits... * 15-5: page * 4-0: register offset @@ -2421,7 +2417,9 @@ struct e1000_hw { #define BME1000_E_PHY_ID 0x01410CB0 #define I210_I_PHY_ID 0x01410C00 +#define I226_LM_PHY_ID 0x67C9DC10 #define I225_I_PHY_ID 0x67C9DCC0 +#define I226_I_PHY_ID 0x67C9DCD0 /* Miscellaneous PHY bit definitions. */ #define PHY_PREAMBLE 0xFFFFFFFF diff --git a/drivers/net/e1000_spi.c b/drivers/net/e1000_spi.c index 69adf282c73..1e830b99f1d 100644 --- a/drivers/net/e1000_spi.c +++ b/drivers/net/e1000_spi.c @@ -1,9 +1,9 @@ -#include <common.h> #include <command.h> #include <console.h> #include <linux/delay.h> #include "e1000.h" #include <malloc.h> +#include <vsprintf.h> #include <linux/compiler.h> /*----------------------------------------------------------------------- diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index 38d96ab72b6..d18a8d577ca 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> +#include <config.h> #include <asm/io.h> #include <cpu_func.h> #include <malloc.h> diff --git a/drivers/net/essedma.c b/drivers/net/essedma.c new file mode 100644 index 00000000000..fccc5f5a440 --- /dev/null +++ b/drivers/net/essedma.c @@ -0,0 +1,1192 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Sartura Ltd. + * + * Author: Robert Marko <robert.marko@sartura.hr> + * + * Copyright (c) 2021 Toco Technologies FZE <contact@toco.ae> + * Copyright (c) 2021 Gabor Juhos <j4g8y7@gmail.com> + * + * Qualcomm ESS EDMA ethernet driver + */ + +#include <asm/io.h> +#include <clk.h> +#include <cpu_func.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <errno.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <log.h> +#include <miiphy.h> +#include <net.h> +#include <reset.h> + +#include "essedma.h" + +#define EDMA_MAX_PKT_SIZE (PKTSIZE_ALIGN + PKTALIGN) + +#define EDMA_RXQ_ID 0 +#define EDMA_TXQ_ID 0 + +/* descriptor ring */ +struct edma_ring { + u16 count; /* number of descriptors in the ring */ + void *hw_desc; /* descriptor ring virtual address */ + unsigned int hw_size; /* hw descriptor ring length in bytes */ + dma_addr_t dma; /* descriptor ring physical address */ + u16 head; /* next Tx descriptor to fill */ + u16 tail; /* next Tx descriptor to clean */ +}; + +struct ess_switch { + phys_addr_t base; + struct phy_device *phydev[ESS_PORTS_NUM]; + u32 phy_mask; + ofnode ports_node; + phy_interface_t port_wrapper_mode; + int num_phy; +}; + +struct essedma_priv { + phys_addr_t base; + struct udevice *dev; + struct clk ess_clk; + struct reset_ctl ess_rst; + struct udevice *mdio_dev; + struct ess_switch esw; + phys_addr_t psgmii_base; + struct edma_ring tpd_ring; + struct edma_ring rfd_ring; +}; + +static void esw_port_loopback_set(struct ess_switch *esw, int port, + bool enable) +{ + u32 t; + + t = readl(esw->base + ESS_PORT_LOOKUP_CTRL(port)); + if (enable) + t |= ESS_PORT_LOOP_BACK_EN; + else + t &= ~ESS_PORT_LOOP_BACK_EN; + writel(t, esw->base + ESS_PORT_LOOKUP_CTRL(port)); +} + +static void esw_port_loopback_set_all(struct ess_switch *esw, bool enable) +{ + int i; + + for (i = 1; i < ESS_PORTS_NUM; i++) + esw_port_loopback_set(esw, i, enable); +} + +static void ess_reset(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + + reset_assert(&priv->ess_rst); + mdelay(10); + + reset_deassert(&priv->ess_rst); + mdelay(10); +} + +void qca8075_ess_reset(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + struct phy_device *psgmii_phy; + int i, val; + + /* Find the PSGMII PHY */ + psgmii_phy = priv->esw.phydev[priv->esw.num_phy - 1]; + + /* Fix phy psgmii RX 20bit */ + phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x005b); + + /* Reset phy psgmii */ + phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x001b); + + /* Release reset phy psgmii */ + phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x005b); + for (i = 0; i < 100; i++) { + val = phy_read_mmd(psgmii_phy, MDIO_MMD_PMAPMD, 0x28); + if (val & 0x1) + break; + mdelay(1); + } + if (i >= 100) + printf("QCA807x PSGMII PLL_VCO_CALIB Not Ready\n"); + + /* + * Check qca8075 psgmii calibration done end. + * Freeze phy psgmii RX CDR + */ + phy_write(psgmii_phy, MDIO_DEVAD_NONE, 0x1a, 0x2230); + + ess_reset(dev); + + /* Check ipq psgmii calibration done start */ + for (i = 0; i < 100; i++) { + val = readl(priv->psgmii_base + PSGMIIPHY_VCO_CALIBRATION_CTRL_REGISTER_2); + if (val & 0x1) + break; + mdelay(1); + } + if (i >= 100) + printf("PSGMII PLL_VCO_CALIB Not Ready\n"); + + /* + * Check ipq psgmii calibration done end. + * Relesae phy psgmii RX CDR + */ + phy_write(psgmii_phy, MDIO_DEVAD_NONE, 0x1a, 0x3230); + + /* Release phy psgmii RX 20bit */ + phy_write(psgmii_phy, MDIO_DEVAD_NONE, MII_BMCR, 0x005f); +} + +#define PSGMII_ST_NUM_RETRIES 20 +#define PSGMII_ST_PKT_COUNT (4 * 1024) +#define PSGMII_ST_PKT_SIZE 1504 + +/* + * Transmitting one byte over a 1000Mbps link requires 8 ns. + * Additionally, use + 1 ns for safety to compensate latencies + * and such. + */ +#define PSGMII_ST_TRAFFIC_TIMEOUT_NS \ + (PSGMII_ST_PKT_COUNT * PSGMII_ST_PKT_SIZE * (8 + 1)) + +#define PSGMII_ST_TRAFFIC_TIMEOUT \ + DIV_ROUND_UP(PSGMII_ST_TRAFFIC_TIMEOUT_NS, 1000000) + +static bool psgmii_self_test_repeat; + +static void psgmii_st_phy_power_down(struct phy_device *phydev) +{ + int val; + + val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + val |= QCA807X_POWER_DOWN; + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, val); +} + +static void psgmii_st_phy_prepare(struct phy_device *phydev) +{ + int val; + + /* check phydev combo port */ + val = phy_read(phydev, MDIO_DEVAD_NONE, + QCA807X_CHIP_CONFIGURATION); + if (val) { + /* Select copper page */ + val |= QCA807X_MEDIA_PAGE_SELECT; + phy_write(phydev, MDIO_DEVAD_NONE, + QCA807X_CHIP_CONFIGURATION, val); + } + + /* Force no link by power down */ + psgmii_st_phy_power_down(phydev); + + /* Packet number (Non documented) */ + phy_write_mmd(phydev, MDIO_MMD_AN, 0x8021, PSGMII_ST_PKT_COUNT); + phy_write_mmd(phydev, MDIO_MMD_AN, 0x8062, PSGMII_ST_PKT_SIZE); + + /* Fix MDI status */ + val = phy_read(phydev, MDIO_DEVAD_NONE, QCA807X_FUNCTION_CONTROL); + val &= ~QCA807X_MDI_CROSSOVER_MODE_MASK; + val |= FIELD_PREP(QCA807X_MDI_CROSSOVER_MODE_MASK, + QCA807X_MDI_CROSSOVER_MODE_MANUAL_MDI); + val &= ~QCA807X_POLARITY_REVERSAL; + phy_write(phydev, MDIO_DEVAD_NONE, QCA807X_FUNCTION_CONTROL, val); +} + +static void psgmii_st_phy_recover(struct phy_device *phydev) +{ + int val; + + /* Packet number (Non documented) */ + phy_write_mmd(phydev, MDIO_MMD_AN, 0x8021, 0x0); + + /* Disable CRC checker and packet counter */ + val = phy_read_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_CRC_PACKET_COUNTER); + val &= ~QCA807X_MMD7_PACKET_COUNTER_SELFCLR; + val &= ~QCA807X_MMD7_CRC_PACKET_COUNTER_EN; + phy_write_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_CRC_PACKET_COUNTER, val); + + /* Disable traffic (Undocumented) */ + phy_write_mmd(phydev, MDIO_MMD_AN, 0x8020, 0x0); +} + +static void psgmii_st_phy_start_traffic(struct phy_device *phydev) +{ + int val; + + /* Enable CRC checker and packet counter */ + val = phy_read_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_CRC_PACKET_COUNTER); + val |= QCA807X_MMD7_CRC_PACKET_COUNTER_EN; + phy_write_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_CRC_PACKET_COUNTER, val); + + /* Start traffic (Undocumented) */ + phy_write_mmd(phydev, MDIO_MMD_AN, 0x8020, 0xa000); +} + +static bool psgmii_st_phy_check_counters(struct phy_device *phydev) +{ + u32 tx_ok; + + /* + * The number of test packets is limited to 65535 so + * only read the lower 16 bits of the counter. + */ + tx_ok = phy_read_mmd(phydev, MDIO_MMD_AN, + QCA807X_MMD7_VALID_EGRESS_COUNTER_2); + + return (tx_ok == PSGMII_ST_PKT_COUNT); +} + +static void psgmii_st_phy_reset_loopback(struct phy_device *phydev) +{ + /* reset the PHY */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, 0x9000); + + /* enable loopback mode */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, 0x4140); +} + +static inline bool psgmii_st_phy_link_is_up(struct phy_device *phydev) +{ + int val; + + val = phy_read(phydev, MDIO_DEVAD_NONE, QCA807X_PHY_SPECIFIC); + return !!(val & QCA807X_PHY_SPECIFIC_LINK); +} + +static bool psgmii_st_phy_wait(struct ess_switch *esw, u32 mask, + int retries, int delay, + bool (*check)(struct phy_device *)) +{ + int i; + + for (i = 0; i < retries; i++) { + int phy; + + for (phy = 0; phy < esw->num_phy - 1; phy++) { + u32 phybit = BIT(phy); + + if (!(mask & phybit)) + continue; + + if (check(esw->phydev[phy])) + mask &= ~phybit; + } + + if (!mask) + break; + + mdelay(delay); + } + + return (!mask); +} + +static bool psgmii_st_phy_wait_link(struct ess_switch *esw, u32 mask) +{ + return psgmii_st_phy_wait(esw, mask, 100, 10, + psgmii_st_phy_link_is_up); +} + +static bool psgmii_st_phy_wait_tx_complete(struct ess_switch *esw, u32 mask) +{ + return psgmii_st_phy_wait(esw, mask, PSGMII_ST_TRAFFIC_TIMEOUT, 1, + psgmii_st_phy_check_counters); +} + +static bool psgmii_st_run_test_serial(struct ess_switch *esw) +{ + bool result = true; + int i; + + for (i = 0; i < esw->num_phy - 1; i++) { + struct phy_device *phydev = esw->phydev[i]; + + psgmii_st_phy_reset_loopback(phydev); + + psgmii_st_phy_wait_link(esw, BIT(i)); + + psgmii_st_phy_start_traffic(phydev); + + /* wait for the traffic to complete */ + result &= psgmii_st_phy_wait_tx_complete(esw, BIT(i)); + + /* Power down */ + psgmii_st_phy_power_down(phydev); + + if (!result) + break; + } + + return result; +} + +static bool psgmii_st_run_test_parallel(struct ess_switch *esw) +{ + bool result; + int i; + + /* enable loopback mode on all PHYs */ + for (i = 0; i < esw->num_phy - 1; i++) + psgmii_st_phy_reset_loopback(esw->phydev[i]); + + psgmii_st_phy_wait_link(esw, esw->phy_mask); + + /* start traffic on all PHYs parallely */ + for (i = 0; i < esw->num_phy - 1; i++) + psgmii_st_phy_start_traffic(esw->phydev[i]); + + /* wait for the traffic to complete on all PHYs */ + result = psgmii_st_phy_wait_tx_complete(esw, esw->phy_mask); + + /* Power down all PHYs */ + for (i = 0; i < esw->num_phy - 1; i++) + psgmii_st_phy_power_down(esw->phydev[i]); + + return result; +} + +struct psgmii_st_stats { + int succeed; + int failed; + int failed_max; + int failed_cont; +}; + +static void psgmii_st_update_stats(struct psgmii_st_stats *stats, + bool success) +{ + if (success) { + stats->succeed++; + stats->failed_cont = 0; + return; + } + + stats->failed++; + stats->failed_cont++; + if (stats->failed_max < stats->failed_cont) + stats->failed_max = stats->failed_cont; +} + +static void psgmii_self_test(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + struct ess_switch *esw = &priv->esw; + struct psgmii_st_stats stats; + bool result = false; + unsigned long tm; + int i; + + memset(&stats, 0, sizeof(stats)); + + tm = get_timer(0); + + for (i = 0; i < esw->num_phy - 1; i++) + psgmii_st_phy_prepare(esw->phydev[i]); + + for (i = 0; i < PSGMII_ST_NUM_RETRIES; i++) { + qca8075_ess_reset(dev); + + /* enable loopback mode on the switch's ports */ + esw_port_loopback_set_all(esw, true); + + /* run test on each PHYs individually after each other */ + result = psgmii_st_run_test_serial(esw); + + if (result) { + /* run test on each PHYs parallely */ + result = psgmii_st_run_test_parallel(esw); + } + + psgmii_st_update_stats(&stats, result); + + if (psgmii_self_test_repeat) + continue; + + if (result) + break; + } + + for (i = 0; i < esw->num_phy - 1; i++) { + /* Configuration recover */ + psgmii_st_phy_recover(esw->phydev[i]); + + /* Disable loopback */ + phy_write(esw->phydev[i], MDIO_DEVAD_NONE, + QCA807X_FUNCTION_CONTROL, 0x6860); + phy_write(esw->phydev[i], MDIO_DEVAD_NONE, MII_BMCR, 0x9040); + } + + /* disable loopback mode on the switch's ports */ + esw_port_loopback_set_all(esw, false); + + tm = get_timer(tm); + dev_dbg(priv->dev, "\nPSGMII self-test: succeed %d, failed %d (max %d), duration %lu.%03lu secs\n", + stats.succeed, stats.failed, stats.failed_max, + tm / 1000, tm % 1000); +} + +static int ess_switch_disable_lookup(struct ess_switch *esw) +{ + int val; + int i; + + /* Disable port lookup for all ports*/ + for (i = 0; i < ESS_PORTS_NUM; i++) { + int ess_port_vid; + + val = readl(esw->base + ESS_PORT_LOOKUP_CTRL(i)); + val &= ~ESS_PORT_VID_MEM_MASK; + + switch (i) { + case 0: + fallthrough; + case 5: + /* CPU,WAN port -> nothing */ + ess_port_vid = 0; + break; + case 1 ... 4: + /* LAN ports -> all other LAN ports */ + ess_port_vid = GENMASK(4, 1); + ess_port_vid &= ~BIT(i); + break; + default: + return -EINVAL; + } + + val |= FIELD_PREP(ESS_PORT_VID_MEM_MASK, ess_port_vid); + + writel(val, esw->base + ESS_PORT_LOOKUP_CTRL(i)); + } + + /* Set magic value for the global forwarding register 1 */ + writel(0x3e3e3e, esw->base + ESS_GLOBAL_FW_CTRL1); + + return 0; +} + +static int ess_switch_enable_lookup(struct ess_switch *esw) +{ + int val; + int i; + + /* Enable port lookup for all ports*/ + for (i = 0; i < ESS_PORTS_NUM; i++) { + int ess_port_vid; + + val = readl(esw->base + ESS_PORT_LOOKUP_CTRL(i)); + val &= ~ESS_PORT_VID_MEM_MASK; + + switch (i) { + case 0: + /* CPU port -> all other ports */ + ess_port_vid = GENMASK(5, 1); + break; + case 1 ... 4: + /* LAN ports -> CPU and all other LAN ports */ + ess_port_vid = GENMASK(4, 0); + ess_port_vid &= ~BIT(i); + break; + case 5: + /* WAN port -> CPU port only */ + ess_port_vid = BIT(0); + break; + default: + return -EINVAL; + } + + val |= FIELD_PREP(ESS_PORT_VID_MEM_MASK, ess_port_vid); + + writel(val, esw->base + ESS_PORT_LOOKUP_CTRL(i)); + } + + /* Set magic value for the global forwarding register 1 */ + writel(0x3f3f3f, esw->base + ESS_GLOBAL_FW_CTRL1); + + return 0; +} + +static void ess_switch_init(struct ess_switch *esw) +{ + int val = 0; + int i; + + /* Set magic value for the global forwarding register 1 */ + writel(0x3e3e3e, esw->base + ESS_GLOBAL_FW_CTRL1); + + /* Set 1000M speed, full duplex and RX/TX flow control for the CPU port*/ + val &= ~ESS_PORT_SPEED_MASK; + val |= FIELD_PREP(ESS_PORT_SPEED_MASK, ESS_PORT_SPEED_1000); + val |= ESS_PORT_DUPLEX_MODE; + val |= ESS_PORT_TX_FLOW_EN; + val |= ESS_PORT_RX_FLOW_EN; + + writel(val, esw->base + ESS_PORT0_STATUS); + + /* Disable port lookup for all ports*/ + for (i = 0; i < ESS_PORTS_NUM; i++) { + val = readl(esw->base + ESS_PORT_LOOKUP_CTRL(i)); + val &= ~ESS_PORT_VID_MEM_MASK; + + writel(val, esw->base + ESS_PORT_LOOKUP_CTRL(i)); + } + + /* Set HOL settings for all ports*/ + for (i = 0; i < ESS_PORTS_NUM; i++) { + val = 0; + + val |= FIELD_PREP(EG_PORT_QUEUE_NUM_MASK, 30); + if (i == 0 || i == 5) { + val |= FIELD_PREP(EG_PRI5_QUEUE_NUM_MASK, 4); + val |= FIELD_PREP(EG_PRI4_QUEUE_NUM_MASK, 4); + } + val |= FIELD_PREP(EG_PRI3_QUEUE_NUM_MASK, 4); + val |= FIELD_PREP(EG_PRI2_QUEUE_NUM_MASK, 4); + val |= FIELD_PREP(EG_PRI1_QUEUE_NUM_MASK, 4); + val |= FIELD_PREP(EG_PRI0_QUEUE_NUM_MASK, 4); + + writel(val, esw->base + ESS_PORT_HOL_CTRL0(i)); + + val = readl(esw->base + ESS_PORT_HOL_CTRL1(i)); + val &= ~ESS_ING_BUF_NUM_0_MASK; + val |= FIELD_PREP(ESS_ING_BUF_NUM_0_MASK, 6); + + writel(val, esw->base + ESS_PORT_HOL_CTRL1(i)); + } + + /* Give switch some time */ + mdelay(1); + + /* Enable RX and TX MAC-s */ + val = readl(esw->base + ESS_PORT0_STATUS); + val |= ESS_PORT_TXMAC_EN; + val |= ESS_PORT_RXMAC_EN; + + writel(val, esw->base + ESS_PORT0_STATUS); + + /* Set magic value for the global forwarding register 1 */ + writel(0x7f7f7f, esw->base + ESS_GLOBAL_FW_CTRL1); +} + +static int essedma_of_phy(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + struct ess_switch *esw = &priv->esw; + int num_phy = 0, ret = 0; + ofnode node; + int i; + + ofnode_for_each_subnode(node, esw->ports_node) { + struct ofnode_phandle_args phandle_args; + struct phy_device *phydev; + u32 phy_addr; + + if (ofnode_is_enabled(node)) { + if (ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0, + &phandle_args)) { + dev_dbg(priv->dev, "Failed to find phy-handle\n"); + return -ENODEV; + } + + ret = ofnode_read_u32(phandle_args.node, "reg", &phy_addr); + if (ret) { + dev_dbg(priv->dev, "Missing reg property in PHY node %s\n", + ofnode_get_name(phandle_args.node)); + return ret; + } + + phydev = dm_mdio_phy_connect(priv->mdio_dev, phy_addr, + dev, priv->esw.port_wrapper_mode); + if (!phydev) { + dev_dbg(priv->dev, "Failed to find phy on addr %d\n", phy_addr); + return -ENODEV; + } + + phydev->node = phandle_args.node; + ret = phy_config(phydev); + + esw->phydev[num_phy] = phydev; + + num_phy++; + } + } + + esw->num_phy = num_phy; + + for (i = 0; i < esw->num_phy - 1; i++) + esw->phy_mask |= BIT(i); + + return ret; +} + +static int essedma_of_switch(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + int port_wrapper_mode = -1; + + priv->esw.ports_node = ofnode_find_subnode(dev_ofnode(dev), "ports"); + if (!ofnode_valid(priv->esw.ports_node)) { + printf("Failed to find ports node\n"); + return -EINVAL; + } + + port_wrapper_mode = ofnode_read_phy_mode(priv->esw.ports_node); + if (port_wrapper_mode == -1) + return -EINVAL; + + priv->esw.port_wrapper_mode = port_wrapper_mode; + + return essedma_of_phy(dev); +} + +static void ipq40xx_edma_start_rx_tx(struct essedma_priv *priv) +{ + volatile u32 data; + + /* enable RX queues */ + data = readl(priv->base + EDMA_REG_RXQ_CTRL); + data |= EDMA_RXQ_CTRL_EN; + writel(data, priv->base + EDMA_REG_RXQ_CTRL); + + /* enable TX queues */ + data = readl(priv->base + EDMA_REG_TXQ_CTRL); + data |= EDMA_TXQ_CTRL_TXQ_EN; + writel(data, priv->base + EDMA_REG_TXQ_CTRL); +} + +/* + * ipq40xx_edma_init_desc() + * Update descriptor ring size, + * Update buffer and producer/consumer index + */ +static void ipq40xx_edma_init_desc(struct essedma_priv *priv) +{ + struct edma_ring *rfd_ring; + struct edma_ring *etdr; + volatile u32 data = 0; + u16 hw_cons_idx = 0; + + /* Set the base address of every TPD ring. */ + etdr = &priv->tpd_ring; + + /* Update TX descriptor ring base address. */ + writel((u32)(etdr->dma & 0xffffffff), + priv->base + EDMA_REG_TPD_BASE_ADDR_Q(EDMA_TXQ_ID)); + data = readl(priv->base + EDMA_REG_TPD_IDX_Q(EDMA_TXQ_ID)); + + /* Calculate hardware consumer index for Tx. */ + hw_cons_idx = FIELD_GET(EDMA_TPD_CONS_IDX_MASK, data); + etdr->head = hw_cons_idx; + etdr->tail = hw_cons_idx; + data &= ~EDMA_TPD_PROD_IDX_MASK; + data |= hw_cons_idx; + + /* Update producer index for Tx. */ + writel(data, priv->base + EDMA_REG_TPD_IDX_Q(EDMA_TXQ_ID)); + + /* Update SW consumer index register for Tx. */ + writel(hw_cons_idx, + priv->base + EDMA_REG_TX_SW_CONS_IDX_Q(EDMA_TXQ_ID)); + + /* Set TPD ring size. */ + writel((u32)(etdr->count & EDMA_TPD_RING_SIZE_MASK), + priv->base + EDMA_REG_TPD_RING_SIZE); + + /* Configure Rx ring. */ + rfd_ring = &priv->rfd_ring; + + /* Update Receive Free descriptor ring base address. */ + writel((u32)(rfd_ring->dma & 0xffffffff), + priv->base + EDMA_REG_RFD_BASE_ADDR_Q(EDMA_RXQ_ID)); + data = readl(priv->base + EDMA_REG_RFD_BASE_ADDR_Q(EDMA_RXQ_ID)); + + /* Update RFD ring size and RX buffer size. */ + data = (rfd_ring->count & EDMA_RFD_RING_SIZE_MASK) + << EDMA_RFD_RING_SIZE_SHIFT; + data |= (EDMA_MAX_PKT_SIZE & EDMA_RX_BUF_SIZE_MASK) + << EDMA_RX_BUF_SIZE_SHIFT; + writel(data, priv->base + EDMA_REG_RX_DESC0); + + /* Disable TX FIFO low watermark and high watermark */ + writel(0, priv->base + EDMA_REG_TXF_WATER_MARK); + + /* Load all of base address above */ + data = readl(priv->base + EDMA_REG_TX_SRAM_PART); + data |= 1 << EDMA_LOAD_PTR_SHIFT; + writel(data, priv->base + EDMA_REG_TX_SRAM_PART); +} + +static void ipq40xx_edma_init_rfd_ring(struct essedma_priv *priv) +{ + struct edma_ring *erdr = &priv->rfd_ring; + struct edma_rfd *rfds = erdr->hw_desc; + int i; + + for (i = 0; i < erdr->count; i++) + rfds[i].buffer_addr = virt_to_phys(net_rx_packets[i]); + + flush_dcache_range(erdr->dma, erdr->dma + erdr->hw_size); + + /* setup producer index */ + erdr->head = erdr->count - 1; + writel(erdr->head, priv->base + EDMA_REG_RFD_IDX_Q(EDMA_RXQ_ID)); +} + +static void ipq40xx_edma_configure(struct essedma_priv *priv) +{ + u32 tmp; + int i; + + /* Set RSS type */ + writel(IPQ40XX_EDMA_RSS_TYPE_NONE, priv->base + EDMA_REG_RSS_TYPE); + + /* Configure RSS indirection table. + * 128 hash will be configured in the following + * pattern: hash{0,1,2,3} = {Q0,Q2,Q4,Q6} respectively + * and so on + */ + for (i = 0; i < EDMA_NUM_IDT; i++) + writel(EDMA_RSS_IDT_VALUE, priv->base + EDMA_REG_RSS_IDT(i)); + + /* Set RFD burst number */ + tmp = (EDMA_RFD_BURST << EDMA_RXQ_RFD_BURST_NUM_SHIFT); + + /* Set RFD prefetch threshold */ + tmp |= (EDMA_RFD_THR << EDMA_RXQ_RFD_PF_THRESH_SHIFT); + + /* Set RFD in host ring low threshold to generte interrupt */ + tmp |= (EDMA_RFD_LTHR << EDMA_RXQ_RFD_LOW_THRESH_SHIFT); + writel(tmp, priv->base + EDMA_REG_RX_DESC1); + + /* configure reception control data. */ + + /* Set Rx FIFO threshold to start to DMA data to host */ + tmp = EDMA_FIFO_THRESH_128_BYTE; + + /* Set RX remove vlan bit */ + tmp |= EDMA_RXQ_CTRL_RMV_VLAN; + writel(tmp, priv->base + EDMA_REG_RXQ_CTRL); + + /* Configure transmission control data */ + tmp = (EDMA_TPD_BURST << EDMA_TXQ_NUM_TPD_BURST_SHIFT); + tmp |= EDMA_TXQ_CTRL_TPD_BURST_EN; + tmp |= (EDMA_TXF_BURST << EDMA_TXQ_TXF_BURST_NUM_SHIFT); + writel(tmp, priv->base + EDMA_REG_TXQ_CTRL); +} + +static void ipq40xx_edma_stop_rx_tx(struct essedma_priv *priv) +{ + volatile u32 data; + + data = readl(priv->base + EDMA_REG_RXQ_CTRL); + data &= ~EDMA_RXQ_CTRL_EN; + writel(data, priv->base + EDMA_REG_RXQ_CTRL); + data = readl(priv->base + EDMA_REG_TXQ_CTRL); + data &= ~EDMA_TXQ_CTRL_TXQ_EN; + writel(data, priv->base + EDMA_REG_TXQ_CTRL); +} + +static int ipq40xx_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct essedma_priv *priv = dev_get_priv(dev); + struct edma_ring *erdr = &priv->rfd_ring; + struct edma_rrd *rrd; + u32 hw_tail; + u8 *rx_pkt; + + hw_tail = readl(priv->base + EDMA_REG_RFD_IDX_Q(EDMA_RXQ_ID)); + hw_tail = FIELD_GET(EDMA_RFD_CONS_IDX_MASK, hw_tail); + + if (hw_tail == erdr->tail) + return -EAGAIN; + + rx_pkt = net_rx_packets[erdr->tail]; + invalidate_dcache_range((unsigned long)rx_pkt, + (unsigned long)(rx_pkt + EDMA_MAX_PKT_SIZE)); + + rrd = (struct edma_rrd *)rx_pkt; + + /* Check if RRD is valid */ + if (!(rrd->rrd7 & EDMA_RRD7_DESC_VALID)) + return 0; + + *packetp = rx_pkt + EDMA_RRD_SIZE; + + /* get the packet size */ + return rrd->rrd6; +} + +static int ipq40xx_eth_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct essedma_priv *priv = dev_get_priv(dev); + struct edma_ring *erdr; + + erdr = &priv->rfd_ring; + + /* Update the producer index */ + writel(erdr->head, priv->base + EDMA_REG_RFD_IDX_Q(EDMA_RXQ_ID)); + + erdr->head++; + if (erdr->head == erdr->count) + erdr->head = 0; + + /* Update the consumer index */ + erdr->tail++; + if (erdr->tail == erdr->count) + erdr->tail = 0; + + writel(erdr->tail, + priv->base + EDMA_REG_RX_SW_CONS_IDX_Q(EDMA_RXQ_ID)); + + return 0; +} + +static int ipq40xx_eth_start(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + + ipq40xx_edma_init_rfd_ring(priv); + + ipq40xx_edma_start_rx_tx(priv); + ess_switch_enable_lookup(&priv->esw); + + return 0; +} + +/* + * One TPD would be enough for sending a packet, however because the + * minimal cache line size is larger than the size of a TPD it is not + * possible to flush only one at once. To overcome this limitation + * multiple TPDs are used for sending a single packet. + */ +#define EDMA_TPDS_PER_PACKET 4 +#define EDMA_TPD_MIN_BYTES 4 +#define EDMA_MIN_PKT_SIZE (EDMA_TPDS_PER_PACKET * EDMA_TPD_MIN_BYTES) + +#define EDMA_TX_COMPLETE_TIMEOUT 1000000 + +static int ipq40xx_eth_send(struct udevice *dev, void *packet, int length) +{ + struct essedma_priv *priv = dev_get_priv(dev); + struct edma_tpd *first_tpd; + struct edma_tpd *tpds; + int i; + + if (length < EDMA_MIN_PKT_SIZE) + return 0; + + flush_dcache_range((unsigned long)(packet), + (unsigned long)(packet) + + roundup(length, ARCH_DMA_MINALIGN)); + + tpds = priv->tpd_ring.hw_desc; + for (i = 0; i < EDMA_TPDS_PER_PACKET; i++) { + struct edma_tpd *tpd; + void *frag; + + frag = packet + (i * EDMA_TPD_MIN_BYTES); + + /* get the next TPD */ + tpd = &tpds[priv->tpd_ring.head]; + if (i == 0) + first_tpd = tpd; + + /* update the software index */ + priv->tpd_ring.head++; + if (priv->tpd_ring.head == priv->tpd_ring.count) + priv->tpd_ring.head = 0; + + tpd->svlan_tag = 0; + tpd->addr = virt_to_phys(frag); + tpd->word3 = EDMA_PORT_ENABLE_ALL << EDMA_TPD_PORT_BITMAP_SHIFT; + + if (i < (EDMA_TPDS_PER_PACKET - 1)) { + tpd->len = EDMA_TPD_MIN_BYTES; + tpd->word1 = 0; + } else { + tpd->len = length; + tpd->word1 = 1 << EDMA_TPD_EOP_SHIFT; + } + + length -= EDMA_TPD_MIN_BYTES; + } + + /* make sure that memory writing completes */ + wmb(); + + flush_dcache_range((unsigned long)first_tpd, + (unsigned long)first_tpd + + EDMA_TPDS_PER_PACKET * sizeof(struct edma_tpd)); + + /* update the TX producer index */ + writel(priv->tpd_ring.head, + priv->base + EDMA_REG_TPD_IDX_Q(EDMA_TXQ_ID)); + + /* Wait for TX DMA completion */ + for (i = 0; i < EDMA_TX_COMPLETE_TIMEOUT; i++) { + u32 r, prod, cons; + + r = readl(priv->base + EDMA_REG_TPD_IDX_Q(EDMA_TXQ_ID)); + prod = FIELD_GET(EDMA_TPD_PROD_IDX_MASK, r); + cons = FIELD_GET(EDMA_TPD_CONS_IDX_MASK, r); + + if (cons == prod) + break; + + udelay(1); + } + + if (i == EDMA_TX_COMPLETE_TIMEOUT) + printf("TX timeout: packet not sent!\n"); + + /* update the software TX consumer index register */ + writel(priv->tpd_ring.head, + priv->base + EDMA_REG_TX_SW_CONS_IDX_Q(EDMA_TXQ_ID)); + + return 0; +} + +static void ipq40xx_eth_stop(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + + ess_switch_disable_lookup(&priv->esw); + ipq40xx_edma_stop_rx_tx(priv); +} + +static void ipq40xx_edma_free_ring(struct edma_ring *ring) +{ + free(ring->hw_desc); +} + +/* + * Free Tx and Rx rings + */ +static void ipq40xx_edma_free_rings(struct essedma_priv *priv) +{ + ipq40xx_edma_free_ring(&priv->tpd_ring); + ipq40xx_edma_free_ring(&priv->rfd_ring); +} + +/* + * ipq40xx_edma_alloc_ring() + * allocate edma ring descriptor. + */ +static int ipq40xx_edma_alloc_ring(struct edma_ring *erd, + unsigned int desc_size) +{ + erd->head = 0; + erd->tail = 0; + + /* Alloc HW descriptors */ + erd->hw_size = roundup(desc_size * erd->count, + ARCH_DMA_MINALIGN); + + erd->hw_desc = memalign(CONFIG_SYS_CACHELINE_SIZE, erd->hw_size); + if (!erd->hw_desc) + return -ENOMEM; + + memset(erd->hw_desc, 0, erd->hw_size); + erd->dma = virt_to_phys(erd->hw_desc); + + return 0; + +} + +/* + * ipq40xx_allocate_tx_rx_rings() + */ +static int ipq40xx_edma_alloc_tx_rx_rings(struct essedma_priv *priv) +{ + int ret; + + ret = ipq40xx_edma_alloc_ring(&priv->tpd_ring, + sizeof(struct edma_tpd)); + if (ret) + return ret; + + ret = ipq40xx_edma_alloc_ring(&priv->rfd_ring, + sizeof(struct edma_rfd)); + if (ret) + goto err_free_tpd; + + return 0; + +err_free_tpd: + ipq40xx_edma_free_ring(&priv->tpd_ring); + return ret; +} + +static int ipq40xx_eth_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct essedma_priv *priv = dev_get_priv(dev); + unsigned char *mac = pdata->enetaddr; + u32 mac_lo, mac_hi; + + mac_hi = ((u32)mac[0]) << 8 | (u32)mac[1]; + mac_lo = ((u32)mac[2]) << 24 | ((u32)mac[3]) << 16 | + ((u32)mac[4]) << 8 | (u32)mac[5]; + + writel(mac_lo, priv->base + REG_MAC_CTRL0); + writel(mac_hi, priv->base + REG_MAC_CTRL1); + + return 0; +} + +static int edma_init(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + int ret; + + priv->tpd_ring.count = IPQ40XX_EDMA_TX_RING_SIZE; + priv->rfd_ring.count = PKTBUFSRX; + + ret = ipq40xx_edma_alloc_tx_rx_rings(priv); + if (ret) + return -ENOMEM; + + ipq40xx_edma_stop_rx_tx(priv); + + /* Configure EDMA. */ + ipq40xx_edma_configure(priv); + + /* Configure descriptor Ring */ + ipq40xx_edma_init_desc(priv); + + ess_switch_disable_lookup(&priv->esw); + + return 0; +} + +static int essedma_probe(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + int ret; + + priv->dev = dev; + + priv->base = dev_read_addr_name(dev, "edma"); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->psgmii_base = dev_read_addr_name(dev, "psgmii_phy"); + if (priv->psgmii_base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->esw.base = dev_read_addr_name(dev, "base"); + if (priv->esw.base == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = clk_get_by_name(dev, "ess", &priv->ess_clk); + if (ret) + return ret; + + ret = reset_get_by_name(dev, "ess", &priv->ess_rst); + if (ret) + return ret; + + ret = clk_enable(&priv->ess_clk); + if (ret) + return ret; + + ess_reset(dev); + + ret = uclass_get_device_by_driver(UCLASS_MDIO, + DM_DRIVER_GET(ipq4019_mdio), + &priv->mdio_dev); + if (ret) { + dev_dbg(dev, "Cant find IPQ4019 MDIO: %d\n", ret); + goto err; + } + + /* OF switch and PHY parsing and configuration */ + ret = essedma_of_switch(dev); + if (ret) + goto err; + + switch (priv->esw.port_wrapper_mode) { + case PHY_INTERFACE_MODE_PSGMII: + writel(PSGMIIPHY_PLL_VCO_VAL, + priv->psgmii_base + PSGMIIPHY_PLL_VCO_RELATED_CTRL); + writel(PSGMIIPHY_VCO_VAL, priv->psgmii_base + + PSGMIIPHY_VCO_CALIBRATION_CTRL_REGISTER_1); + /* wait for 10ms */ + mdelay(10); + writel(PSGMIIPHY_VCO_RST_VAL, priv->psgmii_base + + PSGMIIPHY_VCO_CALIBRATION_CTRL_REGISTER_1); + break; + case PHY_INTERFACE_MODE_RGMII: + writel(0x1, RGMII_TCSR_ESS_CFG); + writel(0x400, priv->esw.base + ESS_RGMII_CTRL); + break; + default: + printf("Unknown MII interface\n"); + } + + if (priv->esw.port_wrapper_mode == PHY_INTERFACE_MODE_PSGMII) + psgmii_self_test(dev); + + ess_switch_init(&priv->esw); + + ret = edma_init(dev); + if (ret) + goto err; + + return 0; + +err: + reset_assert(&priv->ess_rst); + clk_disable(&priv->ess_clk); + return ret; +} + +static int essedma_remove(struct udevice *dev) +{ + struct essedma_priv *priv = dev_get_priv(dev); + + ipq40xx_edma_free_rings(priv); + + clk_disable(&priv->ess_clk); + reset_assert(&priv->ess_rst); + + return 0; +} + +static const struct eth_ops essedma_eth_ops = { + .start = ipq40xx_eth_start, + .send = ipq40xx_eth_send, + .recv = ipq40xx_eth_recv, + .free_pkt = ipq40xx_eth_free_pkt, + .stop = ipq40xx_eth_stop, + .write_hwaddr = ipq40xx_eth_write_hwaddr, +}; + +static const struct udevice_id essedma_ids[] = { + { .compatible = "qcom,ipq4019-ess", }, + { } +}; + +U_BOOT_DRIVER(essedma) = { + .name = "essedma", + .id = UCLASS_ETH, + .of_match = essedma_ids, + .probe = essedma_probe, + .remove = essedma_remove, + .priv_auto = sizeof(struct essedma_priv), + .plat_auto = sizeof(struct eth_pdata), + .ops = &essedma_eth_ops, + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/net/essedma.h b/drivers/net/essedma.h new file mode 100644 index 00000000000..067cb442fb4 --- /dev/null +++ b/drivers/net/essedma.h @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2020 Sartura Ltd. + * + * Author: Robert Marko <robert.marko@sartura.hr> + * + * Copyright (c) 2021 Toco Technologies FZE <contact@toco.ae> + * Copyright (c) 2021 Gabor Juhos <j4g8y7@gmail.com> + * + * Qualcomm ESS EDMA ethernet driver + */ + +#ifndef _ESSEDMA_ETH_H +#define _ESSEDMA_ETH_H + +#define ESS_PORTS_NUM 6 + +#define ESS_RGMII_CTRL 0x4 + +#define ESS_GLOBAL_FW_CTRL1 0x624 + +#define ESS_PORT0_STATUS 0x7c +#define ESS_PORT_SPEED_MASK GENMASK(1, 0) +#define ESS_PORT_SPEED_1000 3 +#define ESS_PORT_SPEED_100 2 +#define ESS_PORT_SPEED_10 1 +#define ESS_PORT_TXMAC_EN BIT(2) +#define ESS_PORT_RXMAC_EN BIT(3) +#define ESS_PORT_TX_FLOW_EN BIT(4) +#define ESS_PORT_RX_FLOW_EN BIT(5) +#define ESS_PORT_DUPLEX_MODE BIT(6) + +#define ESS_PORT_LOOKUP_CTRL(_p) (0x660 + (_p) * 12) +#define ESS_PORT_LOOP_BACK_EN BIT(21) +#define ESS_PORT_VID_MEM_MASK GENMASK(6, 0) + +#define ESS_PORT_HOL_CTRL0(_p) (0x970 + (_p) * 8) +#define EG_PORT_QUEUE_NUM_MASK GENMASK(29, 24) + +/* Ports 0 and 5 have queues 0-5 + * Ports 1 to 4 have queues 0-3 + */ +#define EG_PRI5_QUEUE_NUM_MASK GENMASK(23, 20) +#define EG_PRI4_QUEUE_NUM_MASK GENMASK(19, 16) +#define EG_PRI3_QUEUE_NUM_MASK GENMASK(15, 12) +#define EG_PRI2_QUEUE_NUM_MASK GENMASK(11, 8) +#define EG_PRI1_QUEUE_NUM_MASK GENMASK(7, 4) +#define EG_PRI0_QUEUE_NUM_MASK GENMASK(3, 0) + +#define ESS_PORT_HOL_CTRL1(_p) (0x974 + (_p) * 8) +#define ESS_ING_BUF_NUM_0_MASK GENMASK(3, 0) + +/* QCA807x PHY registers */ +#define QCA807X_CHIP_CONFIGURATION 0x1f +#define QCA807X_MEDIA_PAGE_SELECT BIT(15) + +#define QCA807X_POWER_DOWN BIT(11) + +#define QCA807X_FUNCTION_CONTROL 0x10 +#define QCA807X_MDI_CROSSOVER_MODE_MASK GENMASK(6, 5) +#define QCA807X_MDI_CROSSOVER_MODE_MANUAL_MDI 0 +#define QCA807X_POLARITY_REVERSAL BIT(1) + +#define QCA807X_PHY_SPECIFIC 0x11 +#define QCA807X_PHY_SPECIFIC_LINK BIT(10) + +#define QCA807X_MMD7_CRC_PACKET_COUNTER 0x8029 +#define QCA807X_MMD7_PACKET_COUNTER_SELFCLR BIT(1) +#define QCA807X_MMD7_CRC_PACKET_COUNTER_EN BIT(0) +#define QCA807X_MMD7_VALID_EGRESS_COUNTER_2 0x802e + +/* PSGMII specific registers */ +#define PSGMIIPHY_VCO_CALIBRATION_CTRL_REGISTER_1 0x9c +#define PSGMIIPHY_VCO_VAL 0x4ada +#define PSGMIIPHY_VCO_RST_VAL 0xada +#define PSGMIIPHY_VCO_CALIBRATION_CTRL_REGISTER_2 0xa0 + +#define PSGMIIPHY_PLL_VCO_RELATED_CTRL 0x78c +#define PSGMIIPHY_PLL_VCO_VAL 0x2803 + +#define RGMII_TCSR_ESS_CFG 0x01953000 + +/* EDMA registers */ +#define IPQ40XX_EDMA_TX_RING_SIZE 8 +#define IPQ40XX_EDMA_RSS_TYPE_NONE 0x1 + +#define EDMA_RSS_TYPE 0 +#define EDMA_TPD_EOP_SHIFT 31 + +/* tpd word 3 bit 18-28 */ +#define EDMA_TPD_PORT_BITMAP_SHIFT 18 + +/* Enable Tx for all ports */ +#define EDMA_PORT_ENABLE_ALL 0x3E + +/* Edma receive consumer index */ +/* x = queue id */ +#define EDMA_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) +/* Edma transmit consumer index */ +#define EDMA_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) +/* TPD Index Register */ +#define EDMA_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) +/* Tx Descriptor Control Register */ +#define EDMA_REG_TPD_RING_SIZE 0x41C +#define EDMA_TPD_RING_SIZE_MASK 0xFFFF + +/* Transmit descriptor base address */ + /* x = queue id */ +#define EDMA_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) +#define EDMA_TPD_PROD_IDX_MASK GENMASK(15, 0) +#define EDMA_TPD_CONS_IDX_MASK GENMASK(31, 16) + +#define EDMA_REG_TX_SRAM_PART 0x400 +#define EDMA_LOAD_PTR_SHIFT 16 + +/* TXQ Control Register */ +#define EDMA_REG_TXQ_CTRL 0x404 +#define EDMA_TXQ_CTRL_TXQ_EN 0x20 +#define EDMA_TXQ_CTRL_TPD_BURST_EN 0x100 +#define EDMA_TXQ_NUM_TPD_BURST_SHIFT 0 +#define EDMA_TXQ_TXF_BURST_NUM_SHIFT 16 +#define EDMA_TXF_BURST 0x100 +#define EDMA_TPD_BURST 5 + +#define EDMA_REG_TXF_WATER_MARK 0x408 + +/* RSS Indirection Register */ +/* x = No. of indirection table */ +#define EDMA_REG_RSS_IDT(x) (0x840 + ((x) << 2)) +#define EDMA_NUM_IDT 16 +#define EDMA_RSS_IDT_VALUE 0x64206420 + +/* RSS Hash Function Type Register */ +#define EDMA_REG_RSS_TYPE 0x894 + +/* x = queue id */ +#define EDMA_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) +/* RFD Index Register */ +#define EDMA_RFD_BURST 8 +#define EDMA_RFD_THR 16 +#define EDMA_RFD_LTHR 0 +#define EDMA_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2)) + +#define EDMA_RFD_CONS_IDX_MASK GENMASK(27, 16) + +/* Rx Descriptor Control Register */ +#define EDMA_REG_RX_DESC0 0xA10 +#define EDMA_RFD_RING_SIZE_MASK 0xFFF +#define EDMA_RX_BUF_SIZE_MASK 0xFFFF +#define EDMA_RFD_RING_SIZE_SHIFT 0 +#define EDMA_RX_BUF_SIZE_SHIFT 16 + +#define EDMA_REG_RX_DESC1 0xA14 +#define EDMA_RXQ_RFD_BURST_NUM_SHIFT 0 +#define EDMA_RXQ_RFD_PF_THRESH_SHIFT 8 +#define EDMA_RXQ_RFD_LOW_THRESH_SHIFT 16 + +/* RXQ Control Register */ +#define EDMA_REG_RXQ_CTRL 0xA18 +#define EDMA_FIFO_THRESH_128_BYTE 0x0 +#define EDMA_RXQ_CTRL_RMV_VLAN 0x00000002 +#define EDMA_RXQ_CTRL_EN 0x0000FF00 + +/* MAC Control Register */ +#define REG_MAC_CTRL0 0xC20 +#define REG_MAC_CTRL1 0xC24 + +/* Transmit Packet Descriptor */ +struct edma_tpd { + u16 len; /* full packet including CRC */ + u16 svlan_tag; /* vlan tag */ + u32 word1; /* byte 4-7 */ + u32 addr; /* address of buffer */ + u32 word3; /* byte 12 */ +}; + +/* Receive Return Descriptor */ +struct edma_rrd { + u16 rrd0; + u16 rrd1; + u16 rrd2; + u16 rrd3; + u16 rrd4; + u16 rrd5; + u16 rrd6; + u16 rrd7; +} __packed; + +#define EDMA_RRD_SIZE sizeof(struct edma_rrd) + +#define EDMA_RRD7_DESC_VALID BIT(15) + +/* Receive Free Descriptor */ +struct edma_rfd { + u32 buffer_addr; /* buffer address */ +}; + +#endif /* _ESSEDMA_ETH_H */ diff --git a/drivers/net/eth-phy-uclass.c b/drivers/net/eth-phy-uclass.c index 9d1e8d38ffa..1dae26878e6 100644 --- a/drivers/net/eth-phy-uclass.c +++ b/drivers/net/eth-phy-uclass.c @@ -5,7 +5,6 @@ #define LOG_CATEGORY UCLASS_ETH_PHY -#include <common.h> #include <dm.h> #include <log.h> #include <net.h> diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index 13fad8119bb..dc7e6f1929f 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -9,7 +9,6 @@ * Copyright (C) 2016 Cadence Design Systems Inc. */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <log.h> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 90af18f80a8..0a0d92bc2cd 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -7,7 +7,6 @@ * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <env.h> diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c index 1c5543e3c87..46a0d38b101 100644 --- a/drivers/net/fm/b4860.c +++ b/drivers/net/fm/b4860.c @@ -3,7 +3,7 @@ * Copyright 2012 Freescale Semiconductor, Inc. * Roy Zang <tie-fei.zang@freescale.com> */ -#include <common.h> +#include <config.h> #include <env.h> #include <phy.h> #include <fm_eth.h> diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c index c51a65cb94f..371d9f07a46 100644 --- a/drivers/net/fm/dtsec.c +++ b/drivers/net/fm/dtsec.c @@ -3,7 +3,6 @@ * Copyright 2009-2011 Freescale Semiconductor, Inc. */ -#include <common.h> #include <asm/types.h> #include <asm/io.h> #include <fsl_dtsec.h> diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 9fd26de0d72..19f3f0fef07 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -4,7 +4,7 @@ * Copyright 2020 NXP * Dave Liu <daveliu@freescale.com> */ -#include <common.h> +#include <config.h> #include <log.h> #include <part.h> #include <asm/io.h> diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c index 3db5c907a2a..41b75761fdd 100644 --- a/drivers/net/fm/ls1043.c +++ b/drivers/net/fm/ls1043.c @@ -2,7 +2,7 @@ /* * Copyright 2015 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <phy.h> #include <fm_eth.h> #include <asm/io.h> diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c index 3b0ee98ddd3..56c5c6846a4 100644 --- a/drivers/net/fm/ls1046.c +++ b/drivers/net/fm/ls1046.c @@ -2,7 +2,7 @@ /* * Copyright 2016 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <phy.h> #include <fm_eth.h> #include <asm/io.h> diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c index eeb67a39a77..37b54626af0 100644 --- a/drivers/net/fm/memac.c +++ b/drivers/net/fm/memac.c @@ -7,7 +7,6 @@ /* MAXFRM - maximum frame length */ #define MAXFRM_MASK 0x0000ffff -#include <common.h> #include <log.h> #include <phy.h> #include <asm/types.h> diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index e0b62b94490..26425d94ae5 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -5,7 +5,6 @@ * Roy Zang <tie-fei.zang@freescale.com> * Some part is taken from tsec.c */ -#include <common.h> #include <miiphy.h> #include <phy.h> #include <asm/io.h> diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c index 9013b276bc9..362bc9f30a1 100644 --- a/drivers/net/fm/p1023.c +++ b/drivers/net/fm/p1023.c @@ -2,7 +2,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <phy.h> #include <fm_eth.h> #include <asm/io.h> diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c index 7ad993221f7..6e63e338e5d 100644 --- a/drivers/net/fm/p4080.c +++ b/drivers/net/fm/p4080.c @@ -2,7 +2,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <phy.h> #include <fm_eth.h> #include <asm/io.h> diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c index f931491b112..4fc1f723a3d 100644 --- a/drivers/net/fm/p5020.c +++ b/drivers/net/fm/p5020.c @@ -2,7 +2,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <phy.h> #include <fm_eth.h> #include <asm/io.h> diff --git a/drivers/net/fm/p5040.c b/drivers/net/fm/p5040.c index ef9f4bcce4d..f6ae947ef99 100644 --- a/drivers/net/fm/p5040.c +++ b/drivers/net/fm/p5040.c @@ -2,7 +2,7 @@ /* * Copyright 2011 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <phy.h> #include <fm_eth.h> #include <asm/io.h> diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c index 70ab4610cdf..18d71e7b60e 100644 --- a/drivers/net/fm/t1024.c +++ b/drivers/net/fm/t1024.c @@ -4,7 +4,7 @@ * Shengzhou Liu <Shengzhou.Liu@freescale.com> */ -#include <common.h> +#include <config.h> #include <phy.h> #include <fm_eth.h> #include <asm/immap_85xx.h> diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c index 5c260bed7fd..dafa6d638e3 100644 --- a/drivers/net/fm/t1040.c +++ b/drivers/net/fm/t1040.c @@ -2,7 +2,7 @@ /* * Copyright 2013 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <phy.h> #include <fm_eth.h> #include <asm/io.h> diff --git a/drivers/net/fm/t2080.c b/drivers/net/fm/t2080.c index 6174934d2b8..390ca0aee70 100644 --- a/drivers/net/fm/t2080.c +++ b/drivers/net/fm/t2080.c @@ -5,7 +5,7 @@ * Shengzhou Liu <Shengzhou.Liu@freescale.com> */ -#include <common.h> +#include <config.h> #include <phy.h> #include <fm_eth.h> #include <asm/immap_85xx.h> diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c index f0a02bfe457..df76073eecd 100644 --- a/drivers/net/fm/t4240.c +++ b/drivers/net/fm/t4240.c @@ -3,7 +3,7 @@ * Copyright 2012 Freescale Semiconductor, Inc. * Roy Zang <tie-fei.zang@freescale.com> */ -#include <common.h> +#include <config.h> #include <phy.h> #include <fm_eth.h> #include <asm/io.h> diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c index 9cc9f3fde3a..f7b51ce0bba 100644 --- a/drivers/net/fm/tgec.c +++ b/drivers/net/fm/tgec.c @@ -7,7 +7,6 @@ /* MAXFRM - maximum frame length */ #define MAXFRM_MASK 0x0000ffff -#include <common.h> #include <phy.h> #include <asm/types.h> #include <asm/io.h> diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c index 22225c2f82f..f6c8f80c835 100644 --- a/drivers/net/fm/tgec_phy.c +++ b/drivers/net/fm/tgec_phy.c @@ -4,7 +4,6 @@ * Andy Fleming <afleming@gmail.com> * Some part is taken from tsec.c */ -#include <common.h> #include <miiphy.h> #include <phy.h> #include <asm/io.h> diff --git a/drivers/net/fsl-mc/dpio/qbman_portal.c b/drivers/net/fsl-mc/dpio/qbman_portal.c index 44ce00041ee..f4e82b0507c 100644 --- a/drivers/net/fsl-mc/dpio/qbman_portal.c +++ b/drivers/net/fsl-mc/dpio/qbman_portal.c @@ -218,7 +218,6 @@ void qbman_eq_desc_set_response(struct qbman_eq_desc *d, qb_attr_code_encode(&code_eq_rsp_stash, cl, !!stash); } - void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid, uint32_t qd_bin, uint32_t qd_prio) { @@ -365,7 +364,6 @@ static struct qb_attr_code code_dqrr_stat = QB_CODE(0, 8, 8); #define QBMAN_DQRR_RESPONSE_BPSCN 0x29 #define QBMAN_DQRR_RESPONSE_CSCN_WQ 0x2a - /* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry * only once, so repeated calls can return a sequence of DQRR entries, without * requiring they be consumed immediately or in any particular order. */ diff --git a/drivers/net/fsl-mc/dpio/qbman_portal.h b/drivers/net/fsl-mc/dpio/qbman_portal.h index 8cbc771a127..67ed90cd389 100644 --- a/drivers/net/fsl-mc/dpio/qbman_portal.h +++ b/drivers/net/fsl-mc/dpio/qbman_portal.h @@ -16,7 +16,6 @@ #define QBMAN_VER_4_0_DQRR_SIZE 4 #define QBMAN_VER_4_1_DQRR_SIZE 8 - /* --------------------- */ /* portal data structure */ /* --------------------- */ @@ -130,7 +129,6 @@ static inline uint32_t qb_attr_code_decode(const struct qb_attr_code *code, return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]); } - /* encode a field to a cacheline */ static inline void qb_attr_code_encode(const struct qb_attr_code *code, uint32_t *cacheline, uint32_t val) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index f5c5057bec1..c2869ce4010 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -3,7 +3,7 @@ * Copyright 2014 Freescale Semiconductor, Inc. * Copyright 2017-2018, 2020-2021 NXP */ -#include <common.h> +#include <config.h> #include <command.h> #include <cpu_func.h> #include <env.h> diff --git a/drivers/net/fsl-mc/mc_sys.c b/drivers/net/fsl-mc/mc_sys.c index 4d32516b005..482fb0463d5 100644 --- a/drivers/net/fsl-mc/mc_sys.c +++ b/drivers/net/fsl-mc/mc_sys.c @@ -8,7 +8,6 @@ #include <fsl-mc/fsl_mc_sys.h> #include <fsl-mc/fsl_mc_cmd.h> -#include <common.h> #include <errno.h> #include <asm/io.h> #include <linux/delay.h> diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 1fd5089cc4b..a6b0bafc8c6 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -4,7 +4,6 @@ * Copyright 2017-2021 NXP */ -#include <common.h> #include <dm.h> #include <errno.h> #include <fdt_support.h> diff --git a/drivers/net/fsl_enetc_mdio.c b/drivers/net/fsl_enetc_mdio.c index 50ad76dfeb5..2d5fcbb6dbd 100644 --- a/drivers/net/fsl_enetc_mdio.c +++ b/drivers/net/fsl_enetc_mdio.c @@ -4,7 +4,6 @@ * Copyright 2019 NXP */ -#include <common.h> #include <dm.h> #include <errno.h> #include <pci.h> diff --git a/drivers/net/fsl_ls_mdio.c b/drivers/net/fsl_ls_mdio.c index fce73937502..e3c37d9045f 100644 --- a/drivers/net/fsl_ls_mdio.c +++ b/drivers/net/fsl_ls_mdio.c @@ -3,7 +3,6 @@ * Copyright 2020 NXP */ -#include <common.h> #include <dm.h> #include <errno.h> #include <miiphy.h> diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c index 5fd11db05f5..a0f1c59e058 100644 --- a/drivers/net/fsl_mdio.c +++ b/drivers/net/fsl_mdio.c @@ -5,7 +5,6 @@ * Mingkai Hu <Mingkai.hu@freescale.com> */ -#include <common.h> #include <miiphy.h> #include <phy.h> #include <fsl_mdio.h> diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 9b536fd5ab8..8781e50a48d 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -11,7 +11,6 @@ * Copyright (C) 2018, IBM Corporation. */ -#include <common.h> #include <clk.h> #include <reset.h> #include <cpu_func.h> diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index fae3adc3de3..fa0b3dbb6d1 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -7,7 +7,6 @@ */ #include <config.h> -#include <common.h> #include <cpu_func.h> #include <env.h> #include <malloc.h> @@ -102,7 +101,6 @@ static int _ftmac100_init(struct ftmac100_data *priv, unsigned char enetaddr[6]) /* set the ethernet address */ ftmac100_set_mac(priv, enetaddr); - /* disable all interrupts */ writel (0, &ftmac100->imr); diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 51f835adabc..8cfeeffe95b 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -5,7 +5,6 @@ * Rockchip GMAC ethernet IP driver for U-Boot */ -#include <common.h> #include <dm.h> #include <clk.h> #include <log.h> @@ -52,7 +51,6 @@ struct rk_gmac_ops { void (*set_to_rgmii)(struct gmac_rockchip_plat *pdata); }; - static int gmac_rockchip_of_to_plat(struct udevice *dev) { struct gmac_rockchip_plat *pdata = dev_get_plat(dev); diff --git a/drivers/net/higmacv300.c b/drivers/net/higmacv300.c index 1862235d0cd..6b88f6fbf59 100644 --- a/drivers/net/higmacv300.c +++ b/drivers/net/higmacv300.c @@ -8,7 +8,6 @@ #include <malloc.h> #include <asm/cache.h> #include <asm/io.h> -#include <common.h> #include <console.h> #include <linux/bitops.h> #include <linux/bug.h> diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c index 518548e3bbc..cc2e826257a 100644 --- a/drivers/net/ks8851_mll.c +++ b/drivers/net/ks8851_mll.c @@ -6,7 +6,6 @@ #include <log.h> #include <asm/io.h> -#include <common.h> #include <command.h> #include <malloc.h> #include <net.h> diff --git a/drivers/net/ks8851_mll.h b/drivers/net/ks8851_mll.h index 7f90ae4e59b..7c5da7db5e2 100644 --- a/drivers/net/ks8851_mll.h +++ b/drivers/net/ks8851_mll.h @@ -114,7 +114,6 @@ #define TXSR_TXFID_SHIFT (0) #define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f) - #define KS_RXCR1 0x74 #define RXCR1_FRXQ (1 << 15) #define RXCR1_RXUDPFCC (1 << 14) diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 87fbada06ba..b72198ca530 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -4,7 +4,6 @@ * Copyright 2017, 2023 NXP */ -#include <common.h> #include <cpu_func.h> #include <dm/device_compat.h> #include <fsl-mc/fsl_dpmac.h> diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h index af082e34cae..ac8d1e408ec 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.h +++ b/drivers/net/ldpaa_eth/ldpaa_eth.h @@ -17,7 +17,6 @@ #include <fsl-mc/fsl_qbman_portal.h> #include <fsl-mc/fsl_mc_private.h> - enum ldpaa_eth_type { LDPAA_ETH_1G_E, LDPAA_ETH_10G_E, diff --git a/drivers/net/ldpaa_eth/ldpaa_wriop.c b/drivers/net/ldpaa_eth/ldpaa_wriop.c index adecb813576..758759240e0 100644 --- a/drivers/net/ldpaa_eth/ldpaa_wriop.c +++ b/drivers/net/ldpaa_eth/ldpaa_wriop.c @@ -3,7 +3,6 @@ * Copyright (C) 2015 Freescale Semiconductor */ -#include <common.h> #include <asm/io.h> #include <asm/types.h> #include <malloc.h> @@ -53,7 +52,6 @@ void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if) } } - /*TODO what it do */ static int wriop_dpmac_to_index(int dpmac_id) { @@ -103,7 +101,6 @@ int wriop_is_enabled_dpmac(int dpmac_id) return dpmac_info[i].enabled; } - int wriop_set_mdio(int dpmac_id, struct mii_dev *bus) { int i = wriop_dpmac_to_index(dpmac_id); diff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c index 32bcb51725a..2727fb01179 100644 --- a/drivers/net/ldpaa_eth/ls1088a.c +++ b/drivers/net/ldpaa_eth/ls1088a.c @@ -2,7 +2,7 @@ /* * Copyright 2017 NXP */ -#include <common.h> +#include <config.h> #include <phy.h> #include <fsl-mc/ldpaa_wriop.h> #include <asm/io.h> diff --git a/drivers/net/ldpaa_eth/ls2080a.c b/drivers/net/ldpaa_eth/ls2080a.c index 845a36bce87..05017552b3f 100644 --- a/drivers/net/ldpaa_eth/ls2080a.c +++ b/drivers/net/ldpaa_eth/ls2080a.c @@ -2,7 +2,7 @@ /* * Copyright 2015 Freescale Semiconductor, Inc. */ -#include <common.h> +#include <config.h> #include <phy.h> #include <fsl-mc/ldpaa_wriop.h> #include <asm/io.h> diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c index c2641a92d7e..25ae684063b 100644 --- a/drivers/net/ldpaa_eth/lx2160a.c +++ b/drivers/net/ldpaa_eth/lx2160a.c @@ -2,7 +2,7 @@ /* * Copyright 2018, 2020 NXP */ -#include <common.h> +#include <config.h> #include <phy.h> #include <fsl-mc/ldpaa_wriop.h> #include <asm/io.h> diff --git a/drivers/net/macb.c b/drivers/net/macb.c index bca014c3cbb..cbf5f605518 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2005-2006 Atmel Corporation */ -#include <common.h> #include <clk.h> #include <cpu_func.h> #include <dm.h> diff --git a/drivers/net/macb.h b/drivers/net/macb.h index 72b84ae96ed..0eb90574618 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -273,7 +273,6 @@ #define GEM_SGMIIEN_OFFSET 27 #define GEM_SGMIIEN_SIZE 1 - /* Constants for data bus width. */ #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */ #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */ @@ -303,7 +302,6 @@ #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */ #define GEM_ADDR64_SIZE 1 - /* Bitfields in NSR */ #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */ #define MACB_NSR_LINK_SIZE 1 @@ -456,7 +454,6 @@ #define GEM_TX_PKT_BUFF_OFFSET 21 #define GEM_TX_PKT_BUFF_SIZE 1 - /* Bitfields in DCFG5. */ #define GEM_TSU_OFFSET 8 #define GEM_TSU_SIZE 1 diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index ec1fae9688b..7e53492733e 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -10,7 +10,8 @@ * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com> */ -#include <common.h> +#include <config.h> +#include <cpu_func.h> #include <env.h> #include <hang.h> #include <malloc.h> @@ -399,7 +400,7 @@ static int mcffec_send(struct udevice *dev, void *packet, int length) #endif #ifdef CONFIG_SYS_UNIFY_CACHE - icache_invalid(); + invalidate_icache_all(); #endif j = 0; @@ -433,7 +434,7 @@ static int mcffec_recv(struct udevice *dev, int flags, uchar **packetp) for (;;) { #ifdef CONFIG_SYS_UNIFY_CACHE - icache_invalid(); + invalidate_icache_all(); #endif /* If nothing received - leave for() loop */ if (info->rxbd[info->rx_idx].cbd_sc & BD_ENET_RX_EMPTY) diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index eae20654513..9bf887035d7 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -4,7 +4,6 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include <common.h> #include <config.h> #include <net.h> #include <netdev.h> diff --git a/drivers/net/mdio-ipq4019.c b/drivers/net/mdio-ipq4019.c index 50134b4d9b6..c824c3da3dd 100644 --- a/drivers/net/mdio-ipq4019.c +++ b/drivers/net/mdio-ipq4019.c @@ -11,7 +11,6 @@ */ #include <asm/io.h> -#include <common.h> #include <dm.h> #include <errno.h> #include <linux/bitops.h> diff --git a/drivers/net/mpc8xx_fec.c b/drivers/net/mpc8xx_fec.c index 78337731e1f..182f84c38af 100644 --- a/drivers/net/mpc8xx_fec.c +++ b/drivers/net/mpc8xx_fec.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <command.h> #include <hang.h> #include <malloc.h> @@ -637,7 +636,6 @@ static int fec_start(struct udevice *dev) return 0; } - static void fec_stop(struct udevice *dev) { struct ether_fcc_info_s *efis = dev_get_priv(dev); diff --git a/drivers/net/mscc_eswitch/jr2_switch.c b/drivers/net/mscc_eswitch/jr2_switch.c index 7157428a685..925888e0765 100644 --- a/drivers/net/mscc_eswitch/jr2_switch.c +++ b/drivers/net/mscc_eswitch/jr2_switch.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include <common.h> #include <config.h> #include <dm.h> #include <malloc.h> diff --git a/drivers/net/mscc_eswitch/luton_switch.c b/drivers/net/mscc_eswitch/luton_switch.c index 5e4f00c4f4d..1c584373b8b 100644 --- a/drivers/net/mscc_eswitch/luton_switch.c +++ b/drivers/net/mscc_eswitch/luton_switch.c @@ -3,7 +3,6 @@ * Copyright (c) 2019 Microsemi Corporation */ -#include <common.h> #include <config.h> #include <dm.h> #include <malloc.h> @@ -628,7 +627,6 @@ static int luton_probe(struct udevice *dev) GCB_MISC_STAT_PHY_READY, true, 500, false)) return -EACCES; - /* Initialize miim buses */ memset(&miim, 0x0, sizeof(miim) * LUTON_MIIM_BUS_COUNT); diff --git a/drivers/net/mscc_eswitch/mscc_miim.h b/drivers/net/mscc_eswitch/mscc_miim.h index feb1f40ae55..b53fd304b1e 100644 --- a/drivers/net/mscc_eswitch/mscc_miim.h +++ b/drivers/net/mscc_eswitch/mscc_miim.h @@ -20,5 +20,4 @@ struct mii_dev *mscc_mdiobus_init(struct mscc_miim_dev *miim, int *miim_count, phys_addr_t miim_base, unsigned long miim_size); - #endif /* _MSCC_MIIM_H_ */ diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c b/drivers/net/mscc_eswitch/ocelot_switch.c index 7ea1f551a11..30bb4b5bad8 100644 --- a/drivers/net/mscc_eswitch/ocelot_switch.c +++ b/drivers/net/mscc_eswitch/ocelot_switch.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include <common.h> #include <config.h> #include <dm.h> #include <log.h> diff --git a/drivers/net/mscc_eswitch/serval_switch.c b/drivers/net/mscc_eswitch/serval_switch.c index be06e483373..8eab41df99a 100644 --- a/drivers/net/mscc_eswitch/serval_switch.c +++ b/drivers/net/mscc_eswitch/serval_switch.c @@ -3,7 +3,6 @@ * Copyright (c) 2019 Microsemi Corporation */ -#include <common.h> #include <config.h> #include <dm.h> #include <log.h> diff --git a/drivers/net/mscc_eswitch/servalt_switch.c b/drivers/net/mscc_eswitch/servalt_switch.c index 2d2329c204a..61547d7933e 100644 --- a/drivers/net/mscc_eswitch/servalt_switch.c +++ b/drivers/net/mscc_eswitch/servalt_switch.c @@ -3,7 +3,6 @@ * Copyright (c) 2019 Microsemi Corporation */ -#include <common.h> #include <config.h> #include <dm.h> #include <malloc.h> diff --git a/drivers/net/mt7628-eth.c b/drivers/net/mt7628-eth.c index b95de474fb0..fc8a6bb331b 100644 --- a/drivers/net/mt7628-eth.c +++ b/drivers/net/mt7628-eth.c @@ -13,7 +13,6 @@ * copyrights here, so I can't add them here. */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <log.h> diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 75e7bcf83b7..5098afef8a8 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -6,7 +6,6 @@ * Author: Mark Lee <mark-mc.lee@mediatek.com> */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <log.h> @@ -1965,7 +1964,9 @@ static int mtk_eth_of_to_plat(struct udevice *dev) return -ENODEV; } - priv->pn_swap = ofnode_read_bool(args.node, "pn_swap"); + /* Upstream linux use mediatek,pnswap instead of pn_swap */ + priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") || + ofnode_read_bool(args.node, "mediatek,pnswap"); } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) { /* get corresponding usxgmii phandle */ ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", diff --git a/drivers/net/mv88e6xxx.c b/drivers/net/mv88e6xxx.c index 8fbbc1cacca..557b6b2c8f6 100644 --- a/drivers/net/mv88e6xxx.c +++ b/drivers/net/mv88e6xxx.c @@ -23,7 +23,6 @@ * on the mv88e6176 via an SGMII interface. */ -#include <common.h> #include <dm/device.h> #include <dm/device_compat.h> #include <dm/device-internal.h> diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 3587ca2124e..17b62bbc205 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -11,7 +11,6 @@ * Copyright (C) 2002 rabeeh@galileo.co.il */ -#include <common.h> #include <dm.h> #include <log.h> #include <net.h> diff --git a/drivers/net/mvmdio.c b/drivers/net/mvmdio.c index 5ebcfe14b7f..3315e06f591 100644 --- a/drivers/net/mvmdio.c +++ b/drivers/net/mvmdio.c @@ -4,7 +4,6 @@ * Author: Ken Ma<make@marvell.com> */ -#include <common.h> #include <dm.h> #include <dm/device-internal.h> #include <dm/lists.h> diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 24933473fa0..1640868c24a 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -12,7 +12,6 @@ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <log.h> @@ -971,7 +970,6 @@ static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp, return &pp->rxqs[rxq]; } - /* Drop packets received by the RXQ and free buffers */ static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) @@ -1108,7 +1106,6 @@ static void mvneta_cleanup_rxqs(struct mvneta_port *pp) mvneta_rxq_deinit(pp, &pp->rxqs[queue]); } - /* Init all Rx queues */ static int mvneta_setup_rxqs(struct mvneta_port *pp) { diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 1cd54307650..ae545fe229c 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -13,7 +13,6 @@ * warranty of any kind, whether express or implied. */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <asm/cache.h> @@ -4703,7 +4702,6 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) port->rxqs[queue] = rxq; } - /* Create Rx descriptor rings */ for (queue = 0; queue < rxq_number; queue++) { struct mvpp2_rx_queue *rxq = port->rxqs[queue]; diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index 151bc55e076..1943de8ba73 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c @@ -4,12 +4,12 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <command.h> #include <env.h> #include <log.h> #include <stdio_dev.h> #include <net.h> +#include <vsprintf.h> #ifndef CFG_NETCONSOLE_BUFFER_SIZE #define CFG_NETCONSOLE_BUFFER_SIZE 512 diff --git a/drivers/net/npcm750_eth.c b/drivers/net/npcm750_eth.c index 2028f4ae286..f0ec6c556cc 100644 --- a/drivers/net/npcm750_eth.c +++ b/drivers/net/npcm750_eth.c @@ -3,7 +3,6 @@ * Copyright (c) 2021 Nuvoton Technology Corp. */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <errno.h> diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index ecf8c28fe41..adeca3d040d 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -5,7 +5,6 @@ * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <errno.h> diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index a1f3c2bd290..180a96af16b 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -6,7 +6,6 @@ * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <log.h> diff --git a/drivers/net/pfe_eth/pfe_cmd.c b/drivers/net/pfe_eth/pfe_cmd.c index 2fe0db0fe71..99c2a8d4e92 100644 --- a/drivers/net/pfe_eth/pfe_cmd.c +++ b/drivers/net/pfe_eth/pfe_cmd.c @@ -9,7 +9,6 @@ * @brief PFE utility commands */ -#include <common.h> #include <command.h> #include <log.h> #include <linux/delay.h> diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c index ab532c5a420..e24a6f93d91 100644 --- a/drivers/net/pfe_eth/pfe_eth.c +++ b/drivers/net/pfe_eth/pfe_eth.c @@ -4,7 +4,7 @@ * Copyright 2017 NXP */ -#include <common.h> +#include <config.h> #include <dm.h> #include <log.h> #include <malloc.h> diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c index ff48726dbf5..651b8aee6f0 100644 --- a/drivers/net/pfe_eth/pfe_mdio.c +++ b/drivers/net/pfe_eth/pfe_mdio.c @@ -3,7 +3,7 @@ * Copyright 2015-2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ -#include <common.h> +#include <config.h> #include <dm.h> #include <log.h> #include <malloc.h> @@ -164,7 +164,6 @@ static void pfe_configure_serdes(struct pfe_eth_dev *priv) if (gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX) sgmii_2500 = 1; - /* PCS configuration done with corresponding GEMAC */ bus.priv = gem_info[priv->gemac_port].gemac_base; diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 3d96938eaba..73064b2af68 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -23,6 +23,12 @@ config PHY_ADDR_ENABLE help Select this if you want to control which phy address is used +config PHY_ANEG_TIMEOUT + int "PHY auto-negotiation timeout" + default 4000 + help + Default PHY auto-negotiation timeout. + if PHY_ADDR_ENABLE config PHY_ADDR int "PHY address" diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c index 0970449d0f9..ce448810ff6 100644 --- a/drivers/net/phy/adin.c +++ b/drivers/net/phy/adin.c @@ -6,7 +6,6 @@ * Copyright 2022 Variscite Ltd. * Copyright 2022 Josua Mayer <josua@solid-run.com> */ -#include <common.h> #include <phy.h> #include <linux/bitops.h> #include <linux/bitfield.h> diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index a958e88d44f..d2db8d9f792 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -6,7 +6,6 @@ * Copyright 2018, 2021 NXP */ #include <config.h> -#include <common.h> #include <dm.h> #include <log.h> #include <net.h> @@ -567,9 +566,9 @@ int aquantia_startup(struct phy_device *phydev) if ((i++ % 500) == 0) printf("."); } while (!aquantia_link_is_up(phydev) && - i < (4 * PHY_ANEG_TIMEOUT)); + i < (4 * CONFIG_PHY_ANEG_TIMEOUT)); - if (i > PHY_ANEG_TIMEOUT) + if (i > CONFIG_PHY_ANEG_TIMEOUT) printf(" TIMEOUT !\n"); } diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index abb7bdf537c..61525f68c35 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -6,7 +6,6 @@ * author Andy Fleming * Copyright (c) 2019 Michael Walle <michael@walle.cc> */ -#include <common.h> #include <phy.h> #include <dm/device_compat.h> #include <linux/bitfield.h> diff --git a/drivers/net/phy/b53.c b/drivers/net/phy/b53.c index 26e8e2fe64f..e95363067fe 100644 --- a/drivers/net/phy/b53.c +++ b/drivers/net/phy/b53.c @@ -22,7 +22,6 @@ * cover other switches would be trivial. */ -#include <common.h> #include <command.h> #include <linux/bitops.h> #include <linux/delay.h> diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index ecccb7c3b54..0a49015eb89 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -5,7 +5,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ -#include <common.h> #include <phy.h> #include <linux/delay.h> diff --git a/drivers/net/phy/ca_phy.c b/drivers/net/phy/ca_phy.c index edef21867b0..5b2c67d2fda 100644 --- a/drivers/net/phy/ca_phy.c +++ b/drivers/net/phy/ca_phy.c @@ -8,7 +8,6 @@ */ #include <config.h> -#include <common.h> #include <log.h> #include <malloc.h> #include <linux/ctype.h> diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index 1cf8b28f582..d043e859bad 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -8,7 +8,6 @@ */ #include <config.h> -#include <common.h> #include <log.h> #include <malloc.h> #include <linux/ctype.h> diff --git a/drivers/net/phy/davicom.c b/drivers/net/phy/davicom.c index 31ffa1ac7a9..52c7189b904 100644 --- a/drivers/net/phy/davicom.c +++ b/drivers/net/phy/davicom.c @@ -5,7 +5,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ -#include <common.h> #include <phy.h> #define MIIM_DM9161_SCR 0x10 @@ -22,7 +21,6 @@ #define MIIM_DM9161_10BTCSR 0x12 #define MIIM_DM9161_10BTCSR_INIT 0x7800 - /* Davicom DM9161E */ static int dm9161_config(struct phy_device *phydev) { diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index b6726031ebb..772cde1c520 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -3,7 +3,6 @@ * TI PHY drivers * */ -#include <common.h> #include <log.h> #include <phy.h> #include <dm/devres.h> diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index f9d4782580e..b6fb5adae1f 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <phy.h> #include <linux/compat.h> #include <malloc.h> diff --git a/drivers/net/phy/ethernet_id.c b/drivers/net/phy/ethernet_id.c index 4dfdee60dcc..2f8454ca27d 100644 --- a/drivers/net/phy/ethernet_id.c +++ b/drivers/net/phy/ethernet_id.c @@ -5,7 +5,6 @@ * Copyright (C) 2022 Xilinx, Inc. */ -#include <common.h> #include <dm/device_compat.h> #include <dm/device-internal.h> #include <dm/lists.h> diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c index 2f0823b8365..11d36164976 100644 --- a/drivers/net/phy/fixed.c +++ b/drivers/net/phy/fixed.c @@ -6,7 +6,6 @@ */ #include <config.h> -#include <common.h> #include <malloc.h> #include <phy.h> #include <dm.h> diff --git a/drivers/net/phy/generic_10g.c b/drivers/net/phy/generic_10g.c index 34ac51ea070..38dc9a88563 100644 --- a/drivers/net/phy/generic_10g.c +++ b/drivers/net/phy/generic_10g.c @@ -7,7 +7,6 @@ * * Based loosely off of Linux's PHY Lib */ -#include <common.h> #include <miiphy.h> #include <phy.h> diff --git a/drivers/net/phy/intel_xway.c b/drivers/net/phy/intel_xway.c index 9d1b97d349f..fe50eec011a 100644 --- a/drivers/net/phy/intel_xway.c +++ b/drivers/net/phy/intel_xway.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0+ -#include <common.h> #include <phy.h> #include <linux/bitfield.h> diff --git a/drivers/net/phy/lxt.c b/drivers/net/phy/lxt.c index 20940033a38..60020508896 100644 --- a/drivers/net/phy/lxt.c +++ b/drivers/net/phy/lxt.c @@ -5,7 +5,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ -#include <common.h> #include <phy.h> /* LXT971 Status 2 registers */ @@ -16,7 +15,6 @@ #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ - /* LXT971 */ static int lxt971_parse_status(struct phy_device *phydev) { diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 0a90f710dfe..b0a0b7fcb38 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -5,7 +5,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ -#include <common.h> #include <errno.h> #include <marvell_phy.h> #include <phy.h> diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 9e64672f5ca..8c95bcbb9ad 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -22,7 +22,6 @@ * If both the fiber and copper ports are connected, the first to gain * link takes priority and the other port is completely locked out. */ -#include <common.h> #include <console.h> #include <dm/device_compat.h> #include <dm/devres.h> diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c index b49c9b5f495..d43b476b3c8 100644 --- a/drivers/net/phy/meson-gxl.c +++ b/drivers/net/phy/meson-gxl.c @@ -7,7 +7,6 @@ * Author: Neil Armstrong <narmstrong@baylibre.com> */ #include <config.h> -#include <common.h> #include <linux/bitops.h> #include <dm.h> #include <phy.h> diff --git a/drivers/net/phy/micrel_ksz8xxx.c b/drivers/net/phy/micrel_ksz8xxx.c index b0f3abcb037..a9a64466ac2 100644 --- a/drivers/net/phy/micrel_ksz8xxx.c +++ b/drivers/net/phy/micrel_ksz8xxx.c @@ -6,7 +6,6 @@ * author Andy Fleming * (C) 2012 NetModule AG, David Andrey, added KSZ9031 */ -#include <common.h> #include <dm.h> #include <errno.h> #include <fdtdec.h> diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index ffc3c987eaa..c48ae6e88f3 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -8,7 +8,6 @@ * (C) Copyright 2017 Adaptrum, Inc. * Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc. */ -#include <common.h> #include <dm.h> #include <env.h> #include <errno.h> @@ -229,7 +228,6 @@ int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum) return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR); } - static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr, int regnum) { diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index cf71f7d4e7e..b143137893f 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -12,7 +12,6 @@ * channel. */ -#include <common.h> #include <ioports.h> #include <ppc_asm.tmpl> #include <miiphy.h> @@ -280,7 +279,6 @@ int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg) return rdreg; } - /***************************************************************************** * * Write a MII PHY register. diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index a2c763c8791..a96430cec43 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -6,7 +6,6 @@ */ #include <config.h> -#include <common.h> #include <malloc.h> #include <phy.h> #include <linux/bitfield.h> diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 85778106edd..ecc10f788af 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -29,7 +29,6 @@ * changes may be required. */ -#include <common.h> #include <log.h> #include <linux/bitops.h> #include <linux/delay.h> diff --git a/drivers/net/phy/mv88e6352.c b/drivers/net/phy/mv88e6352.c index 56060762d85..db4c91e34b4 100644 --- a/drivers/net/phy/mv88e6352.c +++ b/drivers/net/phy/mv88e6352.c @@ -4,7 +4,6 @@ * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com */ -#include <common.h> #include <command.h> #include <log.h> #include <miiphy.h> @@ -263,7 +262,6 @@ int do_mvsw_reg_write(const char *name, int argc, char *const argv[]) return ret; } - int do_mvsw_reg(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { int ret; diff --git a/drivers/net/phy/natsemi.c b/drivers/net/phy/natsemi.c index 6b9e99ea115..1a65e55402b 100644 --- a/drivers/net/phy/natsemi.c +++ b/drivers/net/phy/natsemi.c @@ -5,7 +5,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ -#include <common.h> #include <phy.h> /* NatSemi DP83630 */ @@ -43,7 +42,6 @@ U_BOOT_PHY_DRIVER(dp83630) = { .shutdown = &genphy_shutdown, }; - /* DP83865 Link and Auto-Neg Status Register */ #define MIIM_DP83865_LANR 0x11 #define MIIM_DP83865_SPD_MASK 0x0018 @@ -51,7 +49,6 @@ U_BOOT_PHY_DRIVER(dp83630) = { #define MIIM_DP83865_SPD_100 0x0008 #define MIIM_DP83865_DPX_FULL 0x0002 - /* NatSemi DP83865 */ static int dp838xx_config(struct phy_device *phydev) { @@ -102,7 +99,6 @@ static int dp83865_startup(struct phy_device *phydev) return dp83865_parse_status(phydev); } - U_BOOT_PHY_DRIVER(dp83865) = { .name = "NatSemi DP83865", .uid = 0x20005c70, diff --git a/drivers/net/phy/ncsi.c b/drivers/net/phy/ncsi.c index 2bca116a9d8..a1de438ffff 100644 --- a/drivers/net/phy/ncsi.c +++ b/drivers/net/phy/ncsi.c @@ -5,7 +5,6 @@ * Copyright (C) 2019, IBM Corporation. */ -#include <common.h> #include <log.h> #include <malloc.h> #include <phy.h> diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c index f24fc5b2de6..a1e4c3d053b 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -5,7 +5,6 @@ * Copyright 2021 NXP * Author: Radu Pirea <radu-nicolae.pirea@oss.nxp.com> */ -#include <common.h> #include <dm.h> #include <dm/devres.h> #include <linux/delay.h> diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c index 471b0e322b5..a61471f4277 100644 --- a/drivers/net/phy/nxp-tja11xx.c +++ b/drivers/net/phy/nxp-tja11xx.c @@ -6,7 +6,6 @@ * Copyright (C) 2018 Marek Vasut <marex@denx.de> */ -#include <common.h> #include <linux/bitops.h> #include <linux/delay.h> #include <linux/iopoll.h> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 270176cfe62..716a1d46111 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -7,7 +7,6 @@ * * Based loosely off of Linux's PHY Lib */ -#include <common.h> #include <console.h> #include <dm.h> #include <log.h> @@ -251,7 +250,7 @@ int genphy_update_link(struct phy_device *phydev) /* * Timeout reached ? */ - if (i > (PHY_ANEG_TIMEOUT / 50)) { + if (i > (CONFIG_PHY_ANEG_TIMEOUT / 50)) { printf(" TIMEOUT !\n"); phydev->link = 0; return -ETIMEDOUT; diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 7e1036b2271..30f35cced9d 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -6,7 +6,6 @@ * author Andy Fleming * Copyright 2016 Karsten Merker <merker@debian.org> */ -#include <common.h> #include <linux/bitops.h> #include <phy.h> #include <linux/delay.h> diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c index 056b607e0b8..0d823f5f2b1 100644 --- a/drivers/net/phy/smsc.c +++ b/drivers/net/phy/smsc.c @@ -9,7 +9,6 @@ * Some code copied from linux kernel * Copyright (c) 2006 Herbert Valerio Riedel <hvr@gnu.org> */ -#include <common.h> #include <miiphy.h> /* This code does not check the partner abilities. */ diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c index 15f2c12ed83..b39311976d6 100644 --- a/drivers/net/phy/teranetics.c +++ b/drivers/net/phy/teranetics.c @@ -5,7 +5,6 @@ * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ -#include <common.h> #include <phy.h> #include <linux/delay.h> diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index c5cf0d7dfbd..4867d1931b4 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -6,7 +6,6 @@ * Original Author: Andy Fleming * Add vsc8662 phy support - Priyanka Jain */ -#include <common.h> #include <miiphy.h> /* Cicada Auxiliary Control/Status Register */ diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c index e2969bc4842..e44b7b75bd5 100644 --- a/drivers/net/phy/xilinx_gmii2rgmii.c +++ b/drivers/net/phy/xilinx_gmii2rgmii.c @@ -5,7 +5,6 @@ * Copyright (C) 2018 Xilinx, Inc. */ -#include <common.h> #include <dm.h> #include <log.h> #include <phy.h> diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c index c07c780193f..a59e17d11e5 100644 --- a/drivers/net/phy/xilinx_phy.c +++ b/drivers/net/phy/xilinx_phy.c @@ -6,7 +6,6 @@ */ #include <config.h> -#include <common.h> #include <log.h> #include <phy.h> #include <dm.h> diff --git a/drivers/net/pic32_eth.c b/drivers/net/pic32_eth.c index 1333a3aa7e4..eea3c48aeff 100644 --- a/drivers/net/pic32_eth.c +++ b/drivers/net/pic32_eth.c @@ -3,7 +3,6 @@ * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> * */ -#include <common.h> #include <cpu_func.h> #include <errno.h> #include <dm.h> diff --git a/drivers/net/pic32_mdio.c b/drivers/net/pic32_mdio.c index d4049cfea52..8610f9a1aa5 100644 --- a/drivers/net/pic32_mdio.c +++ b/drivers/net/pic32_mdio.c @@ -5,7 +5,6 @@ * Copyright 2015 Microchip Inc. * Purna Chandra Mandal <purna.mandal@microchip.com> */ -#include <common.h> #include <phy.h> #include <miiphy.h> #include <errno.h> diff --git a/drivers/net/qe/dm_qe_uec.c b/drivers/net/qe/dm_qe_uec.c index 6d1509d90cf..ac3aedd8b49 100644 --- a/drivers/net/qe/dm_qe_uec.c +++ b/drivers/net/qe/dm_qe_uec.c @@ -7,7 +7,6 @@ * Copyright (C) 2020 Heiko Schocher <hs@denx.de> */ -#include <common.h> #include <dm.h> #include <errno.h> #include <memalign.h> diff --git a/drivers/net/qe/dm_qe_uec_phy.c b/drivers/net/qe/dm_qe_uec_phy.c index a0bcc8d3e55..8c0168be859 100644 --- a/drivers/net/qe/dm_qe_uec_phy.c +++ b/drivers/net/qe/dm_qe_uec_phy.c @@ -8,7 +8,6 @@ * Copyright (C) 2020 Heiko Schocher <hs@denx.de> */ -#include <common.h> #include <dm.h> #include <errno.h> #include <miiphy.h> diff --git a/drivers/net/qe/uccf.c b/drivers/net/qe/uccf.c index 00848a1a37d..badf4e5db3e 100644 --- a/drivers/net/qe/uccf.c +++ b/drivers/net/qe/uccf.c @@ -7,6 +7,7 @@ */ #include <malloc.h> +#include <stdio.h> #include <linux/errno.h> #include <asm/io.h> #include <linux/immap_qe.h> diff --git a/drivers/net/qe/uccf.h b/drivers/net/qe/uccf.h index 99f8458edf6..e60bbe241cd 100644 --- a/drivers/net/qe/uccf.h +++ b/drivers/net/qe/uccf.h @@ -9,8 +9,8 @@ #ifndef __UCCF_H__ #define __UCCF_H__ -#include "common.h" -#include "linux/immap_qe.h" +#include <linux/types.h> +#include <linux/immap_qe.h> #include <fsl_qe.h> /* Fast or Giga ethernet */ diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 4764bca7082..f1401d2f6ed 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -8,7 +8,6 @@ * Based on the SuperH Ethernet driver. */ -#include <common.h> #include <clk.h> #include <cpu_func.h> #include <dm.h> diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index 5a69ca1a0f9..8e1b6e2f6f6 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -9,7 +9,6 @@ #include <asm/io.h> #include <clk.h> -#include <common.h> #include <dm.h> #include <dm/device-internal.h> #include <dm/device_compat.h> diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index d8f24ec81a2..2e0afad089f 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -68,7 +68,6 @@ * */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <log.h> diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 93e83661cec..edcae88a3fc 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -39,7 +39,6 @@ * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> * Modified to use le32_to_cpu and cpu_to_le32 properly */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <errno.h> @@ -737,7 +736,6 @@ static void rtl8169_hw_start(struct udevice *dev) RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | (InterFrameGap << TxInterFrameGapShift)); - tpc->cur_rx = 0; RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev, @@ -1032,7 +1030,6 @@ static int rtl_init(unsigned long dev_ioaddr, const char *name, #endif } - tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC); if (!tpc->RxDescArray) return -ENOMEM; diff --git a/drivers/net/sandbox-raw-bus.c b/drivers/net/sandbox-raw-bus.c index fb1ba5a8c83..15670d6d24a 100644 --- a/drivers/net/sandbox-raw-bus.c +++ b/drivers/net/sandbox-raw-bus.c @@ -4,7 +4,6 @@ * Copyright (c) 2018 Joe Hershberger <joe.hershberger@ni.com> */ -#include <common.h> #include <asm/eth-raw-os.h> #include <dm.h> #include <errno.h> diff --git a/drivers/net/sandbox-raw.c b/drivers/net/sandbox-raw.c index 99eb7a3bbff..1d716716778 100644 --- a/drivers/net/sandbox-raw.c +++ b/drivers/net/sandbox-raw.c @@ -8,7 +8,6 @@ #include <log.h> #include <asm/eth-raw-os.h> -#include <common.h> #include <dm.h> #include <env.h> #include <malloc.h> diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c index 13022addb6a..fe3627db6e3 100644 --- a/drivers/net/sandbox.c +++ b/drivers/net/sandbox.c @@ -6,7 +6,6 @@ * Joe Hershberger <joe.hershberger@ni.com> */ -#include <common.h> #include <dm.h> #include <log.h> #include <malloc.h> diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 7b1f59dc498..f1ce994cfd5 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -9,7 +9,6 @@ */ #include <config.h> -#include <common.h> #include <cpu_func.h> #include <env.h> #include <log.h> diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 1c07610e1ac..ecf4a697e27 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -474,7 +474,6 @@ enum EESR_BIT { EESR_PRE = 0x00000002, EESR_CERF = 0x00000001, }; - #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) # define TX_CHECK (EESR_TC1 | EESR_FTC) # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ diff --git a/drivers/net/sja1105.c b/drivers/net/sja1105.c index 48f044c6472..0ba84a4496f 100644 --- a/drivers/net/sja1105.c +++ b/drivers/net/sja1105.c @@ -8,7 +8,6 @@ * Ported from Linux (drivers/net/dsa/sja1105/). */ -#include <common.h> #include <dm/device_compat.h> #include <linux/bitops.h> #include <linux/bitrev.h> diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 616b7ce174f..f39ba40944f 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -5,7 +5,6 @@ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> */ -#include <common.h> #include <command.h> #include <malloc.h> #include <net.h> diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 8bff4fe9a9e..0da182d9f4c 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -16,7 +16,6 @@ #include <asm/global_data.h> #include <asm/gpio.h> #include <asm/io.h> -#include <common.h> #include <clk.h> #include <dm.h> #include <fdt_support.h> @@ -172,7 +171,6 @@ struct emac_eth_dev { struct udevice *phy_reg; }; - struct sun8i_eth_pdata { struct eth_pdata eth_pdata; u32 reset_delays[3]; @@ -180,7 +178,6 @@ struct sun8i_eth_pdata { int rx_delay_ps; }; - static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) { struct udevice *dev = bus->priv; @@ -893,6 +890,11 @@ static const struct emac_variant emac_variant_r40 = { .syscon_offset = 0x164, }; +static const struct emac_variant emac_variant_v3s = { + .syscon_offset = 0x30, + .soc_has_internal_phy = true, +}; + static const struct emac_variant emac_variant_a64 = { .syscon_offset = 0x30, .support_rmii = true, @@ -910,6 +912,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = { .data = (ulong)&emac_variant_h3 }, { .compatible = "allwinner,sun8i-r40-gmac", .data = (ulong)&emac_variant_r40 }, + { .compatible = "allwinner,sun8i-v3s-emac", + .data = (ulong)&emac_variant_v3s }, { .compatible = "allwinner,sun50i-a64-emac", .data = (ulong)&emac_variant_a64 }, { .compatible = "allwinner,sun50i-h6-emac", diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c index f546ad1fe8d..3dee849c97e 100644 --- a/drivers/net/sunxi_emac.c +++ b/drivers/net/sunxi_emac.c @@ -5,7 +5,6 @@ * (C) Copyright 2012, Stefan Roese <sr@denx.de> */ -#include <common.h> #include <clk.h> #include <dm.h> #include <log.h> diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index b151e25d6a4..c70b42f6bcc 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -6,7 +6,6 @@ * */ -#include <common.h> #include <malloc.h> #include <asm/cache.h> #include <asm/gpio.h> @@ -328,6 +327,9 @@ static int am65_cpsw_start(struct udevice *dev) struct ti_udma_drv_chan_cfg_data *dma_rx_cfg_data; int ret, i; + if (common->started) + return 0; + ret = power_domain_on(&common->pwrdmn); if (ret) { dev_err(dev, "power_domain_on() failed %d\n", ret); @@ -359,7 +361,7 @@ static int am65_cpsw_start(struct udevice *dev) UDMA_RX_BUF_SIZE); if (ret) { dev_err(dev, "RX dma add buf failed %d\n", ret); - goto err_free_tx; + goto err_free_rx; } } @@ -488,6 +490,9 @@ static int am65_cpsw_send(struct udevice *dev, void *packet, int length) struct ti_udma_drv_packet_data packet_data; int ret; + if (!common->started) + return -ENETDOWN; + packet_data.pkt_type = AM65_CPSW_CPPI_PKT_TYPE; packet_data.dest_tag = priv->port_id; ret = dma_send(&common->dma_tx, packet, length, &packet_data); @@ -504,6 +509,9 @@ static int am65_cpsw_recv(struct udevice *dev, int flags, uchar **packetp) struct am65_cpsw_priv *priv = dev_get_priv(dev); struct am65_cpsw_common *common = priv->cpsw_common; + if (!common->started) + return -ENETDOWN; + /* try to receive a new packet */ return dma_receive(&common->dma_rx, (void **)packetp, NULL); } diff --git a/drivers/net/ti/cpsw-common.c b/drivers/net/ti/cpsw-common.c index d5428274d19..3e66d7c7bdf 100644 --- a/drivers/net/ti/cpsw-common.c +++ b/drivers/net/ti/cpsw-common.c @@ -5,7 +5,6 @@ * Copyright (C) 2016, Texas Instruments, Incorporated */ -#include <common.h> #include <dm.h> #include <fdt_support.h> #include <asm/global_data.h> diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c index 9a5e9642df1..d7746f454ba 100644 --- a/drivers/net/ti/cpsw.c +++ b/drivers/net/ti/cpsw.c @@ -5,7 +5,6 @@ * Copyright (C) 2010-2018 Texas Instruments Incorporated - https://www.ti.com/ */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <log.h> diff --git a/drivers/net/ti/cpsw_mdio.c b/drivers/net/ti/cpsw_mdio.c index f1b1eba75d0..9e0083ca789 100644 --- a/drivers/net/ti/cpsw_mdio.c +++ b/drivers/net/ti/cpsw_mdio.c @@ -6,7 +6,6 @@ */ #include <clk.h> -#include <common.h> #include <dm/device_compat.h> #include <log.h> #include <malloc.h> diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c index 034877a7690..d8085193e80 100644 --- a/drivers/net/ti/davinci_emac.c +++ b/drivers/net/ti/davinci_emac.c @@ -21,7 +21,7 @@ * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors */ -#include <common.h> +#include <config.h> #include <command.h> #include <cpu_func.h> #include <log.h> @@ -144,7 +144,6 @@ static int davinci_emac_write_hwaddr(struct udevice *dev) writel(mac_hi, &adap_emac->MACSRCADDRHI); writel(mac_lo, &adap_emac->MACSRCADDRLO); - return 0; } @@ -205,7 +204,6 @@ static int davinci_eth_phy_detect(void) return count; } - /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) { @@ -378,7 +376,6 @@ static int gen_auto_negotiate(int phy_addr) } /* End of generic PHY functions */ - #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad, int reg) diff --git a/drivers/net/ti/davinci_emac.h b/drivers/net/ti/davinci_emac.h index 695855b4d54..c213e24b8b2 100644 --- a/drivers/net/ti/davinci_emac.h +++ b/drivers/net/ti/davinci_emac.h @@ -20,7 +20,6 @@ */ #define EMAC_MAX_RX_BUFFERS 10 - /*********************************************** ******** Internally used macros *************** ***********************************************/ @@ -45,7 +44,6 @@ /* Number of statistics registers */ #define EMAC_NUM_STATS 36 - /* EMAC Descriptor */ typedef volatile struct _emac_desc { @@ -78,7 +76,6 @@ typedef volatile struct _emac_desc #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) #define EMAC_RXMBPENABLE_RXBROADEN (0x2000) - #define MDIO_CONTROL_IDLE (0x80000000) #define MDIO_CONTROL_ENABLE (0x40000000) #define MDIO_CONTROL_FAULT_ENABLE (0x40000) diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index 43dbf3f1067..d4abc9a0411 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -5,7 +5,6 @@ * (C) Copyright 2012-2014 * Texas Instruments Incorporated, <www.ti.com> */ -#include <common.h> #include <command.h> #include <console.h> #include <asm/global_data.h> @@ -84,7 +83,6 @@ enum link_type { #endif - struct ks2_eth_priv { struct udevice *dev; struct phy_device *phydev; @@ -209,7 +207,6 @@ int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface) __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port)); __raw_writel(control, SGMII_CTL_REG(port)); - mask = SGMII_REG_STATUS_LINK; if (control & SGMII_REG_CONTROL_AUTONEG) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 8833e3098d5..6481ee24a60 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -8,7 +8,6 @@ */ #include <config.h> -#include <common.h> #include <dm.h> #include <malloc.h> #include <net.h> diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c index 09883f06be2..bd1869dfc83 100644 --- a/drivers/net/vsc7385.c +++ b/drivers/net/vsc7385.c @@ -13,7 +13,6 @@ */ #include <config.h> -#include <common.h> #include <console.h> #include <log.h> #include <asm/io.h> diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index ef151ee51b4..4d87e2d1f36 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -7,7 +7,6 @@ */ #include <config.h> -#include <common.h> #include <cpu_func.h> #include <display_options.h> #include <dm.h> @@ -362,7 +361,7 @@ static int pcs_pma_startup(struct axidma_priv *priv) * and the external PHY is not obtained. */ debug("axiemac: waiting for link status of the PCS/PMA PHY"); - while (retry_cnt * 10 < PHY_ANEG_TIMEOUT) { + while (retry_cnt * 10 < CONFIG_PHY_ANEG_TIMEOUT) { rc = phyread(priv, priv->pcsaddr, MII_BMSR, &mii_reg); if ((mii_reg & BMSR_LSTATUS) && mii_reg != 0xffff && !rc) { debug(".Done\n"); diff --git a/drivers/net/xilinx_axi_mrmac.c b/drivers/net/xilinx_axi_mrmac.c index 410fb25ddef..555651937f8 100644 --- a/drivers/net/xilinx_axi_mrmac.c +++ b/drivers/net/xilinx_axi_mrmac.c @@ -9,7 +9,6 @@ */ #include <config.h> -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <log.h> diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 16ba915fbaa..c25ac2e6600 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -6,7 +6,6 @@ * Michal SIMEK <monstr@monstr.eu> */ -#include <common.h> #include <log.h> #include <net.h> #include <config.h> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 7c57d32614f..fe7d1084450 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -9,7 +9,6 @@ */ #include <clk.h> -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <generic-phy.h> @@ -391,7 +390,6 @@ static int zynq_phy_init(struct udevice *dev) return phy_config(priv->phydev); } - static int zynq_gem_init(struct udevice *dev) { u32 i, nwconfig, nwcfg; |