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-rw-r--r--drivers/net/phy/micrel_ksz90x1.c169
-rw-r--r--drivers/net/ravb.c14
-rw-r--r--drivers/net/ti/am65-cpsw-nuss.c2
3 files changed, 162 insertions, 23 deletions
diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c
index c48ae6e88f3..ee8eae1efd9 100644
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -389,10 +389,126 @@ U_BOOT_PHY_DRIVER(ksz9031) = {
#define KSZ9131RN_DLL_ENABLE_DELAY 0
#define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
+#define KSZ9131RN_COMMON_CTRL 0
+#define KSZ9131RN_COMMON_CTRL_INDIVIDUAL_LED_MODE BIT(4)
+
+#define KSZ9131RN_LED_ERRATA_REG 0x1e
+#define KSZ9131RN_LED_ERRATA_BIT BIT(9)
+
+#define KSZ9131RN_CONTROL_PAD_SKEW 4
+#define KSZ9131RN_RX_DATA_PAD_SKEW 5
+#define KSZ9131RN_TX_DATA_PAD_SKEW 6
+#define KSZ9131RN_CLK_PAD_SKEW 8
+
+#define KSZ9131RN_SKEW_5BIT_MAX 2400
+#define KSZ9131RN_SKEW_4BIT_MAX 800
+#define KSZ9131RN_OFFSET 700
+#define KSZ9131RN_STEP 100
+
+static int ksz9131_of_load_skew_values(struct phy_device *phydev,
+ ofnode of_node,
+ u16 reg, size_t field_sz,
+ const char *field[], u8 numfields)
+{
+ int val[4] = {-(1 + KSZ9131RN_OFFSET), -(2 + KSZ9131RN_OFFSET),
+ -(3 + KSZ9131RN_OFFSET), -(4 + KSZ9131RN_OFFSET)};
+ int skewval, skewmax = 0;
+ int matches = 0;
+ u16 maxval;
+ u16 newval;
+ u16 mask;
+ int i;
+
+ /* psec properties in dts should mean x pico seconds */
+ if (field_sz == 5)
+ skewmax = KSZ9131RN_SKEW_5BIT_MAX;
+ else
+ skewmax = KSZ9131RN_SKEW_4BIT_MAX;
+
+ for (i = 0; i < numfields; i++)
+ if (!ofnode_read_s32(of_node, field[i], &skewval)) {
+ if (skewval < -KSZ9131RN_OFFSET)
+ skewval = -KSZ9131RN_OFFSET;
+ else if (skewval > skewmax)
+ skewval = skewmax;
+
+ val[i] = skewval + KSZ9131RN_OFFSET;
+ matches++;
+ }
+
+ if (!matches)
+ return 0;
+
+ if (matches < numfields)
+ newval = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, reg);
+ else
+ newval = 0;
+
+ maxval = (field_sz == 4) ? 0xf : 0x1f;
+ for (i = 0; i < numfields; i++)
+ if (val[i] != -(i + 1 + KSZ9131RN_OFFSET)) {
+ mask = 0xffff;
+ mask ^= maxval << (field_sz * i);
+ newval = (newval & mask) |
+ (((val[i] / KSZ9131RN_STEP) & maxval)
+ << (field_sz * i));
+ }
+
+ return phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, reg, newval);
+}
+
+static int ksz9131_of_load_all_skew_values(struct phy_device *phydev)
+{
+ const char *control_skews[2] = { "txen-skew-psec", "rxdv-skew-psec" };
+ const char *clk_skews[2] = { "rxc-skew-psec", "txc-skew-psec" };
+ const char *rx_data_skews[4] = {
+ "rxd0-skew-psec", "rxd1-skew-psec",
+ "rxd2-skew-psec", "rxd3-skew-psec"
+ };
+ const char *tx_data_skews[4] = {
+ "txd0-skew-psec", "txd1-skew-psec",
+ "txd2-skew-psec", "txd3-skew-psec"
+ };
+ struct ofnode_phandle_args phandle_args;
+ int ret;
+
+ /*
+ * Silently ignore failure here as the device tree is not required to
+ * contain a phy node.
+ */
+ if (dev_read_phandle_with_args(phydev->dev, "phy-handle", NULL, 0, 0,
+ &phandle_args))
+ return 0;
+
+ if (!ofnode_valid(phandle_args.node))
+ return 0;
+
+ ret = ksz9131_of_load_skew_values(phydev, phandle_args.node,
+ KSZ9131RN_CLK_PAD_SKEW, 5,
+ clk_skews, 2);
+ if (ret < 0)
+ return ret;
+
+ ret = ksz9131_of_load_skew_values(phydev, phandle_args.node,
+ KSZ9131RN_CONTROL_PAD_SKEW, 4,
+ control_skews, 2);
+ if (ret < 0)
+ return ret;
+
+ ret = ksz9131_of_load_skew_values(phydev, phandle_args.node,
+ KSZ9131RN_RX_DATA_PAD_SKEW, 4,
+ rx_data_skews, 4);
+ if (ret < 0)
+ return ret;
+
+ return ksz9131_of_load_skew_values(phydev, phandle_args.node,
+ KSZ9131RN_TX_DATA_PAD_SKEW, 4,
+ tx_data_skews, 4);
+}
+
static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
{
- struct phy_driver *drv = phydev->drv;
- u16 rxcdll_val, txcdll_val, val;
+ u16 rxcdll_val, txcdll_val;
int ret;
switch (phydev->interface) {
@@ -416,24 +532,37 @@ static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
return 0;
}
- val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
- KSZ9131RN_RXC_DLL_CTRL);
- val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
- val |= rxcdll_val;
- ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
- KSZ9131RN_RXC_DLL_CTRL, val);
- if (ret)
+ ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+ KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
+ rxcdll_val);
+ if (ret < 0)
return ret;
- val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
- KSZ9131RN_TXC_DLL_CTRL);
+ return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+ KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
+ txcdll_val);
+}
+
+/* Silicon Errata DS80000693B
+ *
+ * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
+ * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
+ * according to the datasheet (off if there is no link).
+ */
+static int ksz9131_led_errata(struct phy_device *phydev)
+{
+ int reg;
- val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
- val |= txcdll_val;
- ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
- KSZ9131RN_TXC_DLL_CTRL, val);
+ reg = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+ KSZ9131RN_COMMON_CTRL);
+ if (reg < 0)
+ return reg;
- return ret;
+ if (!(reg & KSZ9131RN_COMMON_CTRL_INDIVIDUAL_LED_MODE))
+ return 0;
+
+ return phy_set_bits(phydev, MDIO_DEVAD_NONE, KSZ9131RN_LED_ERRATA_REG,
+ KSZ9131RN_LED_ERRATA_BIT);
}
static int ksz9131_config(struct phy_device *phydev)
@@ -446,6 +575,14 @@ static int ksz9131_config(struct phy_device *phydev)
return ret;
}
+ ret = ksz9131_of_load_all_skew_values(phydev);
+ if (ret < 0)
+ return ret;
+
+ ret = ksz9131_led_errata(phydev);
+ if (ret < 0)
+ return ret;
+
/* add an option to disable the gigabit feature of this PHY */
if (env_get("disable_giga")) {
unsigned features;
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index c39bef17b79..539fd37ee59 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -592,7 +592,7 @@ static int ravb_probe(struct udevice *dev)
ret = clk_get_bulk(dev, &eth->clks);
if (ret < 0)
- goto err_mdio_alloc;
+ goto err_clk_get;
mdiodev = mdio_alloc();
if (!mdiodev) {
@@ -614,23 +614,25 @@ static int ravb_probe(struct udevice *dev)
/* Bring up PHY */
ret = clk_enable_bulk(&eth->clks);
if (ret)
- goto err_mdio_register;
+ goto err_clk_enable;
ret = ravb_reset(dev);
if (ret)
- goto err_mdio_reset;
+ goto err_clk_enable;
ret = ravb_phy_config(dev);
if (ret)
- goto err_mdio_reset;
+ goto err_clk_enable;
return 0;
-err_mdio_reset:
- clk_release_bulk(&eth->clks);
+err_clk_enable:
+ mdio_unregister(mdiodev);
err_mdio_register:
mdio_free(mdiodev);
err_mdio_alloc:
+ clk_release_bulk(&eth->clks);
+err_clk_get:
unmap_physmem(eth->iobase, MAP_NOCACHE);
return ret;
}
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index c70b42f6bcc..3c62fc0b428 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -661,7 +661,7 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev)
dev_read_u32(dev, "max-speed", (u32 *)&pdata->max_speed);
if (pdata->max_speed)
- dev_err(dev, "Port %u speed froced to %uMbit\n",
+ dev_err(dev, "Port %u speed forced to %uMbit\n",
priv->port_id, pdata->max_speed);
return 0;
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-05 04:22:21 +0000