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-rw-r--r--drivers/net/designware.c42
-rw-r--r--drivers/net/mtk_eth/an8855.c89
-rw-r--r--drivers/net/phy/Kconfig4
-rw-r--r--drivers/net/phy/miiphybb.c93
-rw-r--r--drivers/net/phy/ti_phy_init.c48
-rw-r--r--drivers/net/ravb.c14
6 files changed, 140 insertions, 150 deletions
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 94d8f1b4c04..2ab03015ffa 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -33,6 +33,9 @@
#include <linux/printk.h>
#include <power/regulator.h>
#include "designware.h"
+#if IS_ENABLED(CONFIG_ARCH_NPCM8XX)
+#include <asm/arch/gmac.h>
+#endif
static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
@@ -352,10 +355,35 @@ static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
#ifdef CONFIG_ARCH_NPCM8XX
+ if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+ unsigned int start;
+
+ /* Indirect access to VR_MII_MMD registers */
+ writew((VR_MII_MMD >> 9), PCS_BA + PCS_IND_AC);
+ /* Set PCS_Mode to SGMII */
+ clrsetbits_le16(PCS_BA + VR_MII_MMD_AN_CTRL, BIT(1), BIT(2));
+ /* Set Auto Speed Mode Change */
+ setbits_le16(PCS_BA + VR_MII_MMD_CTRL1, BIT(9));
+ /* Indirect access to SR_MII_MMD registers */
+ writew((SR_MII_MMD >> 9), PCS_BA + PCS_IND_AC);
+ /* Restart Auto-Negotiation */
+ setbits_le16(PCS_BA + SR_MII_MMD_CTRL, BIT(9) | BIT(12));
+
+ printf("SGMII PHY Wait for link up \n");
+ /* SGMII PHY Wait for link up */
+ start = get_timer(0);
+ while (!(readw(PCS_BA + SR_MII_MMD_STS) & BIT(2))) {
+ if (get_timer(start) >= LINK_UP_TIMEOUT) {
+ printf("PHY link up timeout\n");
+ return -ETIMEDOUT;
+ }
+ mdelay(1);
+ };
+ }
/* Pass all Multicast Frames */
setbits_le32(&mac_p->framefilt, BIT(4));
-
#endif
+
return 0;
}
@@ -741,6 +769,18 @@ int designware_eth_probe(struct udevice *dev)
puts("Error enabling phy supply\n");
return ret;
}
+#if IS_ENABLED(CONFIG_ARCH_NPCM8XX)
+ int phy_uv;
+
+ phy_uv = dev_read_u32_default(dev, "phy-supply-microvolt", 0);
+ if (phy_uv) {
+ ret = regulator_set_value(phy_supply, phy_uv);
+ if (ret) {
+ puts("Error setting phy voltage\n");
+ return ret;
+ }
+ }
+#endif
}
#endif
diff --git a/drivers/net/mtk_eth/an8855.c b/drivers/net/mtk_eth/an8855.c
index 4bd7506a58b..25a98e0f935 100644
--- a/drivers/net/mtk_eth/an8855.c
+++ b/drivers/net/mtk_eth/an8855.c
@@ -22,7 +22,7 @@
#define AN8855_FORCE_MODE_LNK BIT(31)
#define AN8855_FORCE_MODE 0xb31593f0
-#define AN8855_PORT_CTRL_BASE (0x10208000)
+#define AN8855_PORT_CTRL_BASE 0x10208000
#define AN8855_PORT_CTRL_REG(p, r) (AN8855_PORT_CTRL_BASE + (p) * 0x200 + (r))
#define AN8855_PORTMATRIX_REG(p) AN8855_PORT_CTRL_REG(p, 0x44)
@@ -46,7 +46,7 @@
#define AN8855_CKGCR 0x10213e1c
-#define AN8855_SCU_BASE 0x10000000
+#define AN8855_SCU_BASE 0x10000000
#define AN8855_RG_RGMII_TXCK_C (AN8855_SCU_BASE + 0x1d0)
#define AN8855_RG_GPIO_LED_MODE (AN8855_SCU_BASE + 0x0054)
#define AN8855_RG_GPIO_LED_SEL(i) (AN8855_SCU_BASE + (0x0058 + ((i) * 4)))
@@ -66,23 +66,23 @@
#define AN8855_RG_HSGMII_PCS_CTROL_1 (AN8855_HSGMII_CSR_PCS_BASE + 0xa00)
#define AN8855_RG_AN_SGMII_MODE_FORCE (AN8855_HSGMII_CSR_PCS_BASE + 0xa24)
-#define AN8855_MULTI_SGMII_CSR_BASE 0x10224000
-#define AN8855_SGMII_STS_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x018)
+#define AN8855_MULTI_SGMII_CSR_BASE 0x10224000
+#define AN8855_SGMII_STS_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x018)
#define AN8855_MSG_RX_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x100)
-#define AN8855_MSG_RX_LIK_STS_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x514)
-#define AN8855_MSG_RX_LIK_STS_2 (AN8855_MULTI_SGMII_CSR_BASE + 0x51c)
+#define AN8855_MSG_RX_LIK_STS_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x514)
+#define AN8855_MSG_RX_LIK_STS_2 (AN8855_MULTI_SGMII_CSR_BASE + 0x51c)
#define AN8855_PHY_RX_FORCE_CTRL_0 (AN8855_MULTI_SGMII_CSR_BASE + 0x520)
-#define AN8855_XFI_CSR_PCS_BASE 0x10225000
+#define AN8855_XFI_CSR_PCS_BASE 0x10225000
#define AN8855_RG_USXGMII_AN_CONTROL_0 (AN8855_XFI_CSR_PCS_BASE + 0xbf8)
#define AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000
-#define AN8855_RG_RATE_ADAPT_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x000)
+#define AN8855_RG_RATE_ADAPT_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x000)
#define AN8855_RATE_ADP_P0_CTRL_0 (AN8855_MULTI_PHY_RA_CSR_BASE + 0x100)
-#define AN8855_MII_RA_AN_ENABLE (AN8855_MULTI_PHY_RA_CSR_BASE + 0x300)
+#define AN8855_MII_RA_AN_ENABLE (AN8855_MULTI_PHY_RA_CSR_BASE + 0x300)
#define AN8855_QP_DIG_CSR_BASE 0x1022a000
-#define AN8855_QP_CK_RST_CTRL_4 (AN8855_QP_DIG_CSR_BASE + 0x310)
+#define AN8855_QP_CK_RST_CTRL_4 (AN8855_QP_DIG_CSR_BASE + 0x310)
#define AN8855_QP_DIG_MODE_CTRL_0 (AN8855_QP_DIG_CSR_BASE + 0x324)
#define AN8855_QP_DIG_MODE_CTRL_1 (AN8855_QP_DIG_CSR_BASE + 0x330)
@@ -90,7 +90,7 @@
#define AN8855_PON_RXFEDIG_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x100)
#define AN8855_PON_RXFEDIG_CTRL_9 (AN8855_QP_PMA_TOP_BASE + 0x124)
-#define AN8855_SS_LCPLL_PWCTL_SETTING_2 (AN8855_QP_PMA_TOP_BASE + 0x208)
+#define AN8855_SS_LCPLL_PWCTL_SETTING_2 (AN8855_QP_PMA_TOP_BASE + 0x208)
#define AN8855_SS_LCPLL_TDC_FLT_2 (AN8855_QP_PMA_TOP_BASE + 0x230)
#define AN8855_SS_LCPLL_TDC_FLT_5 (AN8855_QP_PMA_TOP_BASE + 0x23c)
#define AN8855_SS_LCPLL_TDC_PCW_1 (AN8855_QP_PMA_TOP_BASE + 0x248)
@@ -101,7 +101,7 @@
#define AN8855_PLL_CTRL_3 (AN8855_QP_PMA_TOP_BASE + 0x40c)
#define AN8855_PLL_CTRL_4 (AN8855_QP_PMA_TOP_BASE + 0x410)
#define AN8855_PLL_CK_CTRL_0 (AN8855_QP_PMA_TOP_BASE + 0x414)
-#define AN8855_RX_DLY_0 (AN8855_QP_PMA_TOP_BASE + 0x614)
+#define AN8855_RX_DLY_0 (AN8855_QP_PMA_TOP_BASE + 0x614)
#define AN8855_RX_CTRL_2 (AN8855_QP_PMA_TOP_BASE + 0x630)
#define AN8855_RX_CTRL_5 (AN8855_QP_PMA_TOP_BASE + 0x63c)
#define AN8855_RX_CTRL_6 (AN8855_QP_PMA_TOP_BASE + 0x640)
@@ -118,7 +118,7 @@
#define AN8855_RG_QP_CDR_PR_CKREF_DIV1 (AN8855_QP_ANA_CSR_BASE + 0x18)
#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE (AN8855_QP_ANA_CSR_BASE + 0x1c)
#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF (AN8855_QP_ANA_CSR_BASE + 0x20)
-#define AN8855_RG_QP_TX_MODE_16B_EN (AN8855_QP_ANA_CSR_BASE + 0x28)
+#define AN8855_RG_QP_TX_MODE_16B_EN (AN8855_QP_ANA_CSR_BASE + 0x28)
#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL (AN8855_QP_ANA_CSR_BASE + 0x3c)
#define AN8855_RG_QP_PLL_SDM_ORD (AN8855_QP_ANA_CSR_BASE + 0x40)
@@ -135,49 +135,49 @@
#define PHY_SINGLE_LED_ON_DUR(i) (0x3e9 + ((i) * 2))
#define PHY_SINGLE_LED_BLK_DUR(i) (0x3ea + ((i) * 2))
-#define PHY_PMA_CTRL (0x340)
+#define PHY_PMA_CTRL 0x340
#define PHY_DEV1F 0x1f
#define PHY_LED_ON_CTRL(i) (0x24 + ((i) * 2))
-#define LED_ON_EN (1 << 15)
-#define LED_ON_POL (1 << 14)
-#define LED_ON_EVT_MASK (0x7f)
+#define LED_ON_EN BIT(15)
+#define LED_ON_POL BIT(14)
+#define LED_ON_EVT_MASK 0x7f
/* LED ON Event */
-#define LED_ON_EVT_FORCE (1 << 6)
-#define LED_ON_EVT_LINK_HD (1 << 5)
-#define LED_ON_EVT_LINK_FD (1 << 4)
-#define LED_ON_EVT_LINK_DOWN (1 << 3)
-#define LED_ON_EVT_LINK_10M (1 << 2)
-#define LED_ON_EVT_LINK_100M (1 << 1)
-#define LED_ON_EVT_LINK_1000M (1 << 0)
+#define LED_ON_EVT_FORCE BIT(6)
+#define LED_ON_EVT_LINK_HD BIT(5)
+#define LED_ON_EVT_LINK_FD BIT(4)
+#define LED_ON_EVT_LINK_DOWN BIT(3)
+#define LED_ON_EVT_LINK_10M BIT(2)
+#define LED_ON_EVT_LINK_100M BIT(1)
+#define LED_ON_EVT_LINK_1000M BIT(0)
#define PHY_LED_BLK_CTRL(i) (0x25 + ((i) * 2))
-#define LED_BLK_EVT_MASK (0x3ff)
+#define LED_BLK_EVT_MASK 0x3ff
/* LED Blinking Event */
-#define LED_BLK_EVT_FORCE (1 << 9)
-#define LED_BLK_EVT_10M_RX_ACT (1 << 5)
-#define LED_BLK_EVT_10M_TX_ACT (1 << 4)
-#define LED_BLK_EVT_100M_RX_ACT (1 << 3)
-#define LED_BLK_EVT_100M_TX_ACT (1 << 2)
-#define LED_BLK_EVT_1000M_RX_ACT (1 << 1)
-#define LED_BLK_EVT_1000M_TX_ACT (1 << 0)
+#define LED_BLK_EVT_FORCE BIT(9)
+#define LED_BLK_EVT_10M_RX_ACT BIT(5)
+#define LED_BLK_EVT_10M_TX_ACT BIT(4)
+#define LED_BLK_EVT_100M_RX_ACT BIT(3)
+#define LED_BLK_EVT_100M_TX_ACT BIT(2)
+#define LED_BLK_EVT_1000M_RX_ACT BIT(1)
+#define LED_BLK_EVT_1000M_TX_ACT BIT(0)
#define PHY_LED_BCR (0x21)
-#define LED_BCR_EXT_CTRL (1 << 15)
-#define LED_BCR_CLK_EN (1 << 3)
-#define LED_BCR_TIME_TEST (1 << 2)
-#define LED_BCR_MODE_MASK (3)
-#define LED_BCR_MODE_DISABLE (0)
+#define LED_BCR_EXT_CTRL BIT(15)
+#define LED_BCR_CLK_EN BIT(3)
+#define LED_BCR_TIME_TEST BIT(2)
+#define LED_BCR_MODE_MASK 3
+#define LED_BCR_MODE_DISABLE 0
-#define PHY_LED_ON_DUR (0x22)
-#define LED_ON_DUR_MASK (0xffff)
+#define PHY_LED_ON_DUR 0x22
+#define LED_ON_DUR_MASK 0xffff
-#define PHY_LED_BLK_DUR (0x23)
-#define LED_BLK_DUR_MASK (0xffff)
+#define PHY_LED_BLK_DUR 0x23
+#define LED_BLK_DUR_MASK 0xffff
-#define PHY_LED_BLINK_DUR_CTRL (0x720)
+#define PHY_LED_BLINK_DUR_CTRL 0x720
/* Definition of LED */
#define LED_ON_EVENT (LED_ON_EVT_LINK_1000M | \
@@ -993,7 +993,7 @@ static int an8855_setup(struct mtk_eth_switch_priv *swpriv)
/* Switch soft reset */
an8855_reg_write(priv, AN8855_SYS_CTRL_REG, AN8855_SW_SYS_RST);
- udelay(100000);
+ mdelay(100);
an8855_reg_read(priv, AN8855_PKG_SEL, &val);
if ((val & 0x7) == PAG_SEL_AN8855H) {
@@ -1003,8 +1003,7 @@ static int an8855_setup(struct mtk_eth_switch_priv *swpriv)
/* Invert for LED activity change */
an8855_reg_read(priv, AN8855_RG_GPIO_L_INV, &val);
for (id = 0; id < ARRAY_SIZE(led_cfg); id++) {
- if ((led_cfg[id].pol == LED_HIGH) &&
- (led_cfg[id].en == 1))
+ if (led_cfg[id].pol == LED_HIGH && led_cfg[id].en == 1)
val |= 0x1 << id;
}
an8855_reg_write(priv, AN8855_RG_GPIO_L_INV, (val | 0x1));
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 13e73810ad6..3132718e4f8 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -2,10 +2,6 @@
config BITBANGMII
bool "Bit-banged ethernet MII management channel support"
-config BITBANGMII_MULTI
- bool "Enable the multi bus support"
- depends on BITBANGMII
-
config MV88E6352_SWITCH
bool "Marvell 88E6352 switch support"
diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c
index b143137893f..9f5f9b12c9f 100644
--- a/drivers/net/phy/miiphybb.c
+++ b/drivers/net/phy/miiphybb.c
@@ -17,90 +17,6 @@
#include <miiphy.h>
#include <asm/global_data.h>
-#ifndef CONFIG_BITBANGMII_MULTI
-
-/*
- * If CONFIG_BITBANGMII_MULTI is not defined we use a
- * compatibility layer with the previous miiphybb implementation
- * based on macros usage.
- *
- */
-static int bb_mii_init_wrap(struct bb_miiphy_bus *bus)
-{
-#ifdef MII_INIT
- MII_INIT;
-#endif
- return 0;
-}
-
-static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus)
-{
-#ifdef MDIO_DECLARE
- MDIO_DECLARE;
-#endif
- MDIO_ACTIVE;
- return 0;
-}
-
-static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus)
-{
-#ifdef MDIO_DECLARE
- MDIO_DECLARE;
-#endif
- MDIO_TRISTATE;
- return 0;
-}
-
-static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v)
-{
-#ifdef MDIO_DECLARE
- MDIO_DECLARE;
-#endif
- MDIO(v);
- return 0;
-}
-
-static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v)
-{
-#ifdef MDIO_DECLARE
- MDIO_DECLARE;
-#endif
- *v = MDIO_READ;
- return 0;
-}
-
-static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v)
-{
-#ifdef MDC_DECLARE
- MDC_DECLARE;
-#endif
- MDC(v);
- return 0;
-}
-
-static int bb_delay_wrap(struct bb_miiphy_bus *bus)
-{
- MIIDELAY;
- return 0;
-}
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
- {
- .name = BB_MII_DEVNAME,
- .init = bb_mii_init_wrap,
- .mdio_active = bb_mdio_active_wrap,
- .mdio_tristate = bb_mdio_tristate_wrap,
- .set_mdio = bb_set_mdio_wrap,
- .get_mdio = bb_get_mdio_wrap,
- .set_mdc = bb_set_mdc_wrap,
- .delay = bb_delay_wrap,
- }
-};
-
-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
- sizeof(bb_miiphy_buses[0]);
-#endif
-
int bb_miiphy_init(void)
{
int i;
@@ -114,7 +30,6 @@ int bb_miiphy_init(void)
static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname)
{
-#ifdef CONFIG_BITBANGMII_MULTI
int i;
/* Search the correct bus */
@@ -124,10 +39,6 @@ static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname)
}
}
return NULL;
-#else
- /* We have just one bitbanging bus */
- return &bb_miiphy_buses[0];
-#endif
}
/*****************************************************************************
@@ -272,9 +183,7 @@ int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg)
bus->set_mdc(bus, 1);
bus->delay(bus);
-#ifdef DEBUG
- printf("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, rdreg);
-#endif
+ debug("%s[%s](0x%x) @ 0x%x = 0x%04x\n", __func__, miidev->name, reg, addr, rdreg);
return rdreg;
}
diff --git a/drivers/net/phy/ti_phy_init.c b/drivers/net/phy/ti_phy_init.c
index a0878193ac0..850c0cbec96 100644
--- a/drivers/net/phy/ti_phy_init.c
+++ b/drivers/net/phy/ti_phy_init.c
@@ -10,12 +10,58 @@
#include <phy.h>
#include "ti_phy_init.h"
+#define DP83822_DEVADDR 0x1f
+
+#define MII_DP83822_RCSR 0x17
+
+/* RCSR bits */
+#define DP83822_RX_CLK_SHIFT BIT(12)
+#define DP83822_TX_CLK_SHIFT BIT(11)
+
+/* DP83822 specific RGMII RX/TX delay configuration. */
+static int dp83822_config(struct phy_device *phydev)
+{
+ ofnode node = phy_get_ofnode(phydev);
+ u32 rgmii_delay = 0;
+ u32 rx_delay = 0;
+ u32 tx_delay = 0;
+ int ret;
+
+ ret = ofnode_read_u32(node, "rx-internal-delay-ps", &rx_delay);
+ if (ret) {
+ rx_delay = phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID;
+ }
+
+ ret = ofnode_read_u32(node, "tx-internal-delay-ps", &tx_delay);
+ if (ret) {
+ tx_delay = phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID;
+ }
+
+ /* Bit set means Receive path internal clock shift is ENABLED */
+ if (rx_delay)
+ rgmii_delay |= DP83822_RX_CLK_SHIFT;
+
+ /* Bit set means Transmit path internal clock shift is DISABLED */
+ if (!tx_delay)
+ rgmii_delay |= DP83822_TX_CLK_SHIFT;
+
+ ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
+ DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT,
+ rgmii_delay);
+ if (ret)
+ return ret;
+
+ return genphy_config_aneg(phydev);
+}
+
U_BOOT_PHY_DRIVER(dp83822) = {
.name = "TI DP83822",
.uid = 0x2000a240,
.mask = 0xfffffff0,
.features = PHY_BASIC_FEATURES,
- .config = &genphy_config_aneg,
+ .config = &dp83822_config,
.startup = &genphy_startup,
.shutdown = &genphy_shutdown,
};
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index 231764e60b5..7286ad19598 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -560,12 +560,12 @@ static int ravb_remove(struct udevice *dev)
return 0;
}
-int ravb_bb_init(struct bb_miiphy_bus *bus)
+static int ravb_bb_init(struct bb_miiphy_bus *bus)
{
return 0;
}
-int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
+static int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
{
struct ravb_priv *eth = bus->priv;
@@ -574,7 +574,7 @@ int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
return 0;
}
-int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
+static int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
struct ravb_priv *eth = bus->priv;
@@ -583,7 +583,7 @@ int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
return 0;
}
-int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
+static int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
struct ravb_priv *eth = bus->priv;
@@ -595,7 +595,7 @@ int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
return 0;
}
-int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
+static int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
struct ravb_priv *eth = bus->priv;
@@ -604,7 +604,7 @@ int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
return 0;
}
-int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
+static int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
struct ravb_priv *eth = bus->priv;
@@ -616,7 +616,7 @@ int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
return 0;
}
-int ravb_bb_delay(struct bb_miiphy_bus *bus)
+static int ravb_bb_delay(struct bb_miiphy_bus *bus)
{
udelay(10);
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-24 10:14:03 +0000