summaryrefslogtreecommitdiff
path: root/drivers/net
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/Kconfig7
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/designware.c18
-rw-r--r--drivers/net/fsl-mc/mc.c5
-rw-r--r--drivers/net/macb.c4
-rw-r--r--drivers/net/mvgbe.c6
-rw-r--r--drivers/net/mvneta.c15
-rw-r--r--drivers/net/mvpp2.c84
-rw-r--r--drivers/net/ocelot_switch.c765
-rw-r--r--drivers/net/phy/aquantia.c39
-rw-r--r--drivers/net/phy/micrel_ksz90x1.c4
-rw-r--r--drivers/net/phy/phy.c49
-rw-r--r--drivers/net/phy/realtek.c29
-rw-r--r--drivers/net/rtl8139.c6
-rw-r--r--drivers/net/tsec.c37
-rw-r--r--drivers/net/zynq_gem.c11
16 files changed, 990 insertions, 90 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index ff55e03d3fd..39ce4e8a1fc 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -432,6 +432,13 @@ config SNI_AVE
This driver implements support for the Socionext AVE Ethernet
controller, as found on the Socionext UniPhier family.
+config MSCC_OCELOT_SWITCH
+ bool "Ocelot switch driver"
+ depends on DM_ETH && ARCH_MSCC
+ select PHYLIB
+ help
+ This driver supports the Ocelot network switch device.
+
config ETHER_ON_FEC1
bool "FEC1"
depends on MPC8XX_FEC
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index ee7f3e71a8d..e38c1646447 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -75,3 +75,4 @@ obj-$(CONFIG_FSL_PFE) += pfe_eth/
obj-$(CONFIG_SNI_AVE) += sni_ave.o
obj-y += ti/
obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 4fa26abc1b8..2c5d9560c58 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -380,24 +380,28 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
return -EPERM;
}
- length = max(length, ETH_ZLEN);
-
memcpy((void *)data_start, packet, length);
+ if (length < ETH_ZLEN) {
+ memset(&((char *)data_start)[length], 0, ETH_ZLEN - length);
+ length = ETH_ZLEN;
+ }
/* Flush data to be sent */
flush_dcache_range(data_start, data_end);
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
- desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) &
- DESC_TXCTRL_SIZE1MASK;
+ desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
+ ((length << DESC_TXCTRL_SIZE1SHFT) &
+ DESC_TXCTRL_SIZE1MASK);
desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
#else
- desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) &
- DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
- DESC_TXCTRL_TXFIRST;
+ desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
+ ((length << DESC_TXCTRL_SIZE1SHFT) &
+ DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
+ DESC_TXCTRL_TXFIRST;
desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
#endif
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index b245fbc681e..a51b8a46254 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -834,6 +834,11 @@ int get_dpl_apply_status(void)
return mc_dpl_applied;
}
+int is_lazy_dpl_addr_valid(void)
+{
+ return !!mc_lazy_dpl_addr;
+}
+
/*
* Return the MC address of private DRAM block.
* As per MC design document, MC initial base address
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 94c89c762b6..c9ee22279ae 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -1151,7 +1151,9 @@ static int macb_eth_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
+ if (!pdata->iobase)
+ return -EINVAL;
return macb_late_eth_ofdata_to_platdata(dev);
}
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 74fed7abd83..037e59ec6e3 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -1005,10 +1005,8 @@ static int mvgbe_ofdata_to_platdata(struct udevice *dev)
phy_mode = fdt_getprop(gd->fdt_blob, pnode, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
- if (pdata->phy_interface == -1) {
- debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
- return -EINVAL;
- }
+ else
+ pdata->phy_interface = PHY_INTERFACE_MODE_GMII;
dmvgbe->phy_interface = pdata->phy_interface;
diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index 8cb04b52d71..333be8ff28b 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -27,6 +27,7 @@
#include <asm/arch/soc.h>
#include <linux/compat.h>
#include <linux/mbus.h>
+#include <asm-generic/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -274,6 +275,9 @@ struct mvneta_port {
int init;
int phyaddr;
struct phy_device *phydev;
+#ifdef CONFIG_DM_GPIO
+ struct gpio_desc phy_reset_gpio;
+#endif
struct mii_dev *bus;
};
@@ -1749,6 +1753,17 @@ static int mvneta_probe(struct udevice *dev)
if (ret)
return ret;
+#ifdef CONFIG_DM_GPIO
+ gpio_request_by_name(dev, "phy-reset-gpios", 0,
+ &pp->phy_reset_gpio, GPIOD_IS_OUT);
+
+ if (dm_gpio_is_valid(&pp->phy_reset_gpio)) {
+ dm_gpio_set_value(&pp->phy_reset_gpio, 1);
+ mdelay(10);
+ dm_gpio_set_value(&pp->phy_reset_gpio, 0);
+ }
+#endif
+
return board_network_enable(bus);
}
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 9b3ab25c195..bcc6fe92a9f 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -897,7 +897,6 @@ struct mvpp2 {
void __iomem *base;
void __iomem *lms_base;
void __iomem *iface_base;
- void __iomem *mdio_base;
void __iomem *mpcs_base;
void __iomem *xpcs_base;
@@ -928,8 +927,6 @@ struct mvpp2 {
/* Maximum number of RXQs per port */
unsigned int max_port_rxqs;
- struct mii_dev *bus;
-
int probe_done;
u8 num_ports;
};
@@ -955,6 +952,7 @@ struct mvpp2_port {
/* Per-port registers' base address */
void __iomem *base;
+ void __iomem *mdio_base;
struct mvpp2_rx_queue **rxqs;
struct mvpp2_tx_queue **txqs;
@@ -977,6 +975,7 @@ struct mvpp2_port {
phy_interface_t phy_interface;
int phy_node;
int phyaddr;
+ struct mii_dev *bus;
#ifdef CONFIG_DM_GPIO
struct gpio_desc phy_reset_gpio;
struct gpio_desc phy_tx_disable_gpio;
@@ -4500,7 +4499,7 @@ static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
struct phy_device *phy_dev;
if (!port->init || port->link == 0) {
- phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev,
+ phy_dev = phy_connect(port->bus, port->phyaddr, dev,
port->phy_interface);
port->phy_dev = phy_dev;
if (!phy_dev) {
@@ -4705,39 +4704,34 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
{
int port_node = dev_of_offset(dev);
const char *phy_mode_str;
- int phy_node, mdio_off, cp_node;
+ int phy_node;
u32 id;
u32 phyaddr = 0;
int phy_mode = -1;
- phys_addr_t mdio_addr;
+
+ /* Default mdio_base from the same eth base */
+ if (port->priv->hw_version == MVPP21)
+ port->mdio_base = port->priv->lms_base + MVPP21_SMI;
+ else
+ port->mdio_base = port->priv->iface_base + MVPP22_SMI;
phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
if (phy_node > 0) {
+ ofnode phy_ofnode;
+ fdt_addr_t phy_base;
+
phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
if (phyaddr < 0) {
dev_err(&pdev->dev, "could not find phy address\n");
return -1;
}
- mdio_off = fdt_parent_offset(gd->fdt_blob, phy_node);
-
- /* TODO: This WA for mdio issue. U-boot 2017 don't have
- * mdio driver and on MACHIATOBin board ports from CP1
- * connected to mdio on CP0.
- * WA is to get mdio address from phy handler parent
- * base address. WA should be removed after
- * mdio driver implementation.
- */
- mdio_addr = fdtdec_get_uint(gd->fdt_blob,
- mdio_off, "reg", 0);
-
- cp_node = fdt_parent_offset(gd->fdt_blob, mdio_off);
- mdio_addr |= fdt_get_base_address((void *)gd->fdt_blob,
- cp_node);
- port->priv->mdio_base = (void *)mdio_addr;
+ phy_ofnode = ofnode_get_parent(offset_to_ofnode(phy_node));
+ phy_base = ofnode_get_addr(phy_ofnode);
+ port->mdio_base = (void *)phy_base;
- if (port->priv->mdio_base < 0) {
+ if (port->mdio_base < 0) {
dev_err(&pdev->dev, "could not find mdio base address\n");
return -1;
}
@@ -5059,7 +5053,7 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
/* SMI / MDIO functions */
-static int smi_wait_ready(struct mvpp2 *priv)
+static int smi_wait_ready(struct mvpp2_port *priv)
{
u32 timeout = MVPP2_SMI_TIMEOUT;
u32 smi_reg;
@@ -5084,7 +5078,7 @@ static int smi_wait_ready(struct mvpp2 *priv)
*/
static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
- struct mvpp2 *priv = bus->priv;
+ struct mvpp2_port *priv = bus->priv;
u32 smi_reg;
u32 timeout;
@@ -5139,7 +5133,7 @@ static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
u16 value)
{
- struct mvpp2 *priv = bus->priv;
+ struct mvpp2_port *priv = bus->priv;
u32 smi_reg;
/* check parameters */
@@ -5338,7 +5332,6 @@ static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
static int mvpp2_base_probe(struct udevice *dev)
{
struct mvpp2 *priv = dev_get_priv(dev);
- struct mii_dev *bus;
void *bd_space;
u32 size = 0;
int i;
@@ -5397,15 +5390,11 @@ static int mvpp2_base_probe(struct udevice *dev)
priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
if (IS_ERR(priv->lms_base))
return PTR_ERR(priv->lms_base);
-
- priv->mdio_base = priv->lms_base + MVPP21_SMI;
} else {
priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
if (IS_ERR(priv->iface_base))
return PTR_ERR(priv->iface_base);
- priv->mdio_base = priv->iface_base + MVPP22_SMI;
-
/* Store common base addresses for all ports */
priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
@@ -5417,26 +5406,14 @@ static int mvpp2_base_probe(struct udevice *dev)
else
priv->max_port_rxqs = 32;
- /* Finally create and register the MDIO bus driver */
- bus = mdio_alloc();
- if (!bus) {
- printf("Failed to allocate MDIO bus\n");
- return -ENOMEM;
- }
-
- bus->read = mpp2_mdio_read;
- bus->write = mpp2_mdio_write;
- snprintf(bus->name, sizeof(bus->name), dev->name);
- bus->priv = (void *)priv;
- priv->bus = bus;
-
- return mdio_register(bus);
+ return 0;
}
static int mvpp2_probe(struct udevice *dev)
{
struct mvpp2_port *port = dev_get_priv(dev);
struct mvpp2 *priv = dev_get_priv(dev->parent);
+ struct mii_dev *bus;
int err;
/* Only call the probe function for the parent once */
@@ -5445,6 +5422,23 @@ static int mvpp2_probe(struct udevice *dev)
port->priv = dev_get_priv(dev->parent);
+ /* Create and register the MDIO bus driver */
+ bus = mdio_alloc();
+ if (!bus) {
+ printf("Failed to allocate MDIO bus\n");
+ return -ENOMEM;
+ }
+
+ bus->read = mpp2_mdio_read;
+ bus->write = mpp2_mdio_write;
+ snprintf(bus->name, sizeof(bus->name), dev->name);
+ bus->priv = (void *)port;
+ port->bus = bus;
+
+ err = mdio_register(bus);
+ if (err)
+ return err;
+
err = phy_info_parse(dev, port);
if (err)
return err;
diff --git a/drivers/net/ocelot_switch.c b/drivers/net/ocelot_switch.c
new file mode 100644
index 00000000000..9fed26cd94b
--- /dev/null
+++ b/drivers/net/ocelot_switch.c
@@ -0,0 +1,765 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/of_access.h>
+#include <dm/of_addr.h>
+#include <fdt_support.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <miiphy.h>
+#include <net.h>
+#include <wait_bit.h>
+
+#define MIIM_STATUS 0x0
+#define MIIM_STAT_BUSY BIT(3)
+#define MIIM_CMD 0x8
+#define MIIM_CMD_SCAN BIT(0)
+#define MIIM_CMD_OPR_WRITE BIT(1)
+#define MIIM_CMD_OPR_READ BIT(2)
+#define MIIM_CMD_SINGLE_SCAN BIT(3)
+#define MIIM_CMD_WRDATA(x) ((x) << 4)
+#define MIIM_CMD_REGAD(x) ((x) << 20)
+#define MIIM_CMD_PHYAD(x) ((x) << 25)
+#define MIIM_CMD_VLD BIT(31)
+#define MIIM_DATA 0xC
+#define MIIM_DATA_ERROR (0x2 << 16)
+
+#define PHY_CFG 0x0
+#define PHY_CFG_ENA 0xF
+#define PHY_CFG_COMMON_RST BIT(4)
+#define PHY_CFG_RST (0xF << 5)
+#define PHY_STAT 0x4
+#define PHY_STAT_SUPERVISOR_COMPLETE BIT(0)
+
+#define ANA_PORT_VLAN_CFG(x) (0x7000 + 0x100 * (x))
+#define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
+#define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
+#define ANA_PORT_PORT_CFG(x) (0x7070 + 0x100 * (x))
+#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
+#define ANA_TABLES_MACHDATA 0x8b34
+#define ANA_TABLES_MACLDATA 0x8b38
+#define ANA_TABLES_MACACCESS 0x8b3c
+#define ANA_TABLES_MACACCESS_VALID BIT(11)
+#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) ((x) << 9)
+#define ANA_TABLES_MACACCESS_DEST_IDX(x) ((x) << 3)
+#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) (x)
+#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)
+#define MACACCESS_CMD_IDLE 0
+#define MACACCESS_CMD_LEARN 1
+#define MACACCESS_CMD_GET_NEXT 4
+#define ANA_PGID(x) (0x8c00 + 4 * (x))
+
+#define SYS_FRM_AGING 0x574
+#define SYS_FRM_AGING_ENA BIT(20)
+
+#define SYS_SYSTEM_RST_CFG 0x508
+#define SYS_SYSTEM_RST_MEM_INIT BIT(0)
+#define SYS_SYSTEM_RST_MEM_ENA BIT(1)
+#define SYS_SYSTEM_RST_CORE_ENA BIT(2)
+#define SYS_PORT_MODE(x) (0x514 + 0x4 * (x))
+#define SYS_PORT_MODE_INCL_INJ_HDR(x) ((x) << 3)
+#define SYS_PORT_MODE_INCL_INJ_HDR_M GENMASK(4, 3)
+#define SYS_PORT_MODE_INCL_XTR_HDR(x) ((x) << 1)
+#define SYS_PORT_MODE_INCL_XTR_HDR_M GENMASK(2, 1)
+#define SYS_PAUSE_CFG(x) (0x608 + 0x4 * (x))
+#define SYS_PAUSE_CFG_PAUSE_ENA BIT(0)
+
+#define QSYS_SWITCH_PORT_MODE(x) (0x11234 + 0x4 * (x))
+#define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(14)
+#define QSYS_QMAP 0x112d8
+#define QSYS_EGR_NO_SHARING 0x1129c
+
+/* Port registers */
+#define DEV_CLOCK_CFG 0x0
+#define DEV_CLOCK_CFG_LINK_SPEED_1000 1
+#define DEV_MAC_ENA_CFG 0x1c
+#define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
+#define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
+
+#define DEV_MAC_IFG_CFG 0x30
+#define DEV_MAC_IFG_CFG_TX_IFG(x) ((x) << 8)
+#define DEV_MAC_IFG_CFG_RX_IFG2(x) ((x) << 4)
+#define DEV_MAC_IFG_CFG_RX_IFG1(x) (x)
+
+#define PCS1G_CFG 0x48
+#define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
+#define PCS1G_MODE_CFG 0x4c
+#define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4)
+#define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
+#define PCS1G_SD_CFG 0x50
+#define PCS1G_ANEG_CFG 0x54
+#define PCS1G_ANEG_CFG_ADV_ABILITY(x) ((x) << 16)
+
+#define QS_XTR_GRP_CFG(x) (4 * (x))
+#define QS_XTR_GRP_CFG_MODE(x) ((x) << 2)
+#define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
+#define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
+#define QS_XTR_RD(x) (0x8 + 4 * (x))
+#define QS_XTR_FLUSH 0x18
+#define QS_XTR_FLUSH_FLUSH GENMASK(1, 0)
+#define QS_XTR_DATA_PRESENT 0x1c
+#define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4)
+#define QS_INJ_GRP_CFG_MODE(x) ((x) << 2)
+#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
+#define QS_INJ_WR(x) (0x2c + 4 * (x))
+#define QS_INJ_CTRL(x) (0x34 + 4 * (x))
+#define QS_INJ_CTRL_GAP_SIZE(x) ((x) << 21)
+#define QS_INJ_CTRL_EOF BIT(19)
+#define QS_INJ_CTRL_SOF BIT(18)
+#define QS_INJ_CTRL_VLD_BYTES(x) ((x) << 16)
+
+#define XTR_EOF_0 ntohl(0x80000000u)
+#define XTR_EOF_1 ntohl(0x80000001u)
+#define XTR_EOF_2 ntohl(0x80000002u)
+#define XTR_EOF_3 ntohl(0x80000003u)
+#define XTR_PRUNED ntohl(0x80000004u)
+#define XTR_ABORT ntohl(0x80000005u)
+#define XTR_ESCAPE ntohl(0x80000006u)
+#define XTR_NOT_READY ntohl(0x80000007u)
+
+#define IFH_INJ_BYPASS BIT(31)
+#define IFH_TAG_TYPE_C 0
+#define XTR_VALID_BYTES(x) (4 - ((x) & 3))
+#define MAC_VID 1
+#define CPU_PORT 11
+#define INTERNAL_PORT_MSK 0xF
+#define IFH_LEN 4
+#define OCELOT_BUF_CELL_SZ 60
+#define ETH_ALEN 6
+#define PGID_BROADCAST 13
+#define PGID_UNICAST 14
+#define PGID_SRC 80
+
+enum ocelot_target {
+ ANA,
+ QS,
+ QSYS,
+ REW,
+ SYS,
+ HSIO,
+ PORT0,
+ PORT1,
+ PORT2,
+ PORT3,
+ TARGET_MAX,
+};
+
+#define MAX_PORT (PORT3 - PORT0)
+
+/* MAC table entry types.
+ * ENTRYTYPE_NORMAL is subject to aging.
+ * ENTRYTYPE_LOCKED is not subject to aging.
+ * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
+ * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
+ */
+enum macaccess_entry_type {
+ ENTRYTYPE_NORMAL = 0,
+ ENTRYTYPE_LOCKED,
+ ENTRYTYPE_MACv4,
+ ENTRYTYPE_MACv6,
+};
+
+enum ocelot_mdio_target {
+ MIIM,
+ PHY,
+ TARGET_MDIO_MAX,
+};
+
+enum ocelot_phy_id {
+ INTERNAL,
+ EXTERNAL,
+ NUM_PHY,
+};
+
+struct ocelot_private {
+ void __iomem *regs[TARGET_MAX];
+
+ struct mii_dev *bus[NUM_PHY];
+ struct phy_device *phydev;
+ int phy_mode;
+ int max_speed;
+
+ int rx_pos;
+ int rx_siz;
+ int rx_off;
+ int tx_num;
+
+ u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN];
+ void *tx_adj_buf;
+};
+
+struct mscc_miim_dev {
+ void __iomem *regs;
+ void __iomem *phy_regs;
+};
+
+struct mscc_miim_dev miim[NUM_PHY];
+
+static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
+{
+ return wait_for_bit_le32(miim->regs + MIIM_STATUS, MIIM_STAT_BUSY,
+ false, 250, false);
+}
+
+static int mscc_miim_reset(struct mii_dev *bus)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+
+ if (miim->phy_regs) {
+ writel(0, miim->phy_regs + PHY_CFG);
+ writel(PHY_CFG_RST | PHY_CFG_COMMON_RST
+ | PHY_CFG_ENA, miim->phy_regs + PHY_CFG);
+ mdelay(500);
+ }
+
+ return 0;
+}
+
+static int mscc_miim_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ u32 val;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
+ MIIM_CMD_REGAD(reg) | MIIM_CMD_OPR_READ,
+ miim->regs + MIIM_CMD);
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret)
+ goto out;
+
+ val = readl(miim->regs + MIIM_DATA);
+ if (val & MIIM_DATA_ERROR) {
+ ret = -EIO;
+ goto out;
+ }
+
+ ret = val & 0xFFFF;
+ out:
+ return ret;
+}
+
+static int mscc_miim_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+ struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv;
+ int ret;
+
+ ret = mscc_miim_wait_ready(miim);
+ if (ret < 0)
+ goto out;
+
+ writel(MIIM_CMD_VLD | MIIM_CMD_PHYAD(addr) |
+ MIIM_CMD_REGAD(reg) | MIIM_CMD_WRDATA(val) |
+ MIIM_CMD_OPR_WRITE, miim->regs + MIIM_CMD);
+ out:
+ return ret;
+}
+
+/* For now only setup the internal mdio bus */
+static struct mii_dev *ocelot_mdiobus_init(struct udevice *dev)
+{
+ unsigned long phy_size[TARGET_MAX];
+ phys_addr_t phy_base[TARGET_MAX];
+ struct ofnode_phandle_args phandle;
+ ofnode eth_node, node, mdio_node;
+ struct resource res;
+ struct mii_dev *bus;
+ fdt32_t faddr;
+ int i;
+
+ bus = mdio_alloc();
+
+ if (!bus)
+ return NULL;
+
+ /* gathered only the first mdio bus */
+ eth_node = dev_read_first_subnode(dev);
+ node = ofnode_first_subnode(eth_node);
+ ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,
+ &phandle);
+ mdio_node = ofnode_get_parent(phandle.node);
+
+ for (i = 0; i < TARGET_MDIO_MAX; i++) {
+ if (ofnode_read_resource(mdio_node, i, &res)) {
+ pr_err("%s: get OF resource failed\n", __func__);
+ return NULL;
+ }
+ faddr = cpu_to_fdt32(res.start);
+ phy_base[i] = ofnode_translate_address(mdio_node, &faddr);
+ phy_size[i] = res.end - res.start;
+ }
+
+ strcpy(bus->name, "miim-internal");
+ miim[INTERNAL].phy_regs = ioremap(phy_base[PHY], phy_size[PHY]);
+ miim[INTERNAL].regs = ioremap(phy_base[MIIM], phy_size[MIIM]);
+ bus->priv = &miim[INTERNAL];
+ bus->reset = mscc_miim_reset;
+ bus->read = mscc_miim_read;
+ bus->write = mscc_miim_write;
+
+ if (mdio_register(bus))
+ return NULL;
+ else
+ return bus;
+}
+
+__weak void mscc_switch_reset(void)
+{
+}
+
+static void ocelot_stop(struct udevice *dev)
+{
+ struct ocelot_private *priv = dev_get_priv(dev);
+ int i;
+
+ mscc_switch_reset();
+ for (i = 0; i < NUM_PHY; i++)
+ if (priv->bus[i])
+ mscc_miim_reset(priv->bus[i]);
+}
+
+static void ocelot_cpu_capture_setup(struct ocelot_private *priv)
+{
+ int i;
+
+ /* map the 8 CPU extraction queues to CPU port 11 */
+ writel(0, priv->regs[QSYS] + QSYS_QMAP);
+
+ for (i = 0; i <= 1; i++) {
+ /*
+ * Do byte-swap and expect status after last data word
+ * Extraction: Mode: manual extraction) | Byte_swap
+ */
+ writel(QS_XTR_GRP_CFG_MODE(1) | QS_XTR_GRP_CFG_BYTE_SWAP,
+ priv->regs[QS] + QS_XTR_GRP_CFG(i));
+ /*
+ * Injection: Mode: manual extraction | Byte_swap
+ */
+ writel(QS_INJ_GRP_CFG_MODE(1) | QS_INJ_GRP_CFG_BYTE_SWAP,
+ priv->regs[QS] + QS_INJ_GRP_CFG(i));
+ }
+
+ for (i = 0; i <= 1; i++)
+ /* Enable IFH insertion/parsing on CPU ports */
+ writel(SYS_PORT_MODE_INCL_INJ_HDR(1) |
+ SYS_PORT_MODE_INCL_XTR_HDR(1),
+ priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i));
+ /*
+ * Setup the CPU port as VLAN aware to support switching frames
+ * based on tags
+ */
+ writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
+ MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));
+
+ /* Disable learning (only RECV_ENA must be set) */
+ writel(ANA_PORT_PORT_CFG_RECV_ENA,
+ priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));
+
+ /* Enable switching to/from cpu port */
+ setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT),
+ QSYS_SWITCH_PORT_MODE_PORT_ENA);
+
+ /* No pause on CPU port - not needed (off by default) */
+ clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT),
+ SYS_PAUSE_CFG_PAUSE_ENA);
+
+ setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT));
+}
+
+static void ocelot_port_init(struct ocelot_private *priv, int port)
+{
+ void __iomem *regs = priv->regs[port];
+
+ /* Enable PCS */
+ writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG);
+
+ /* Disable Signal Detect */
+ writel(0, regs + PCS1G_SD_CFG);
+
+ /* Enable MAC RX and TX */
+ writel(DEV_MAC_ENA_CFG_RX_ENA | DEV_MAC_ENA_CFG_TX_ENA,
+ regs + DEV_MAC_ENA_CFG);
+
+ /* Clear sgmii_mode_ena */
+ writel(0, regs + PCS1G_MODE_CFG);
+
+ /*
+ * Clear sw_resolve_ena(bit 0) and set adv_ability to
+ * something meaningful just in case
+ */
+ writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG);
+
+ /* Set MAC IFG Gaps */
+ writel(DEV_MAC_IFG_CFG_TX_IFG(5) | DEV_MAC_IFG_CFG_RX_IFG1(5) |
+ DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG);
+
+ /* Set link speed and release all resets */
+ writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG);
+
+ /* Make VLAN aware for CPU traffic */
+ writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
+ MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port - PORT0));
+
+ /* Enable the port in the core */
+ setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port - PORT0),
+ QSYS_SWITCH_PORT_MODE_PORT_ENA);
+}
+
+static int ocelot_switch_init(struct ocelot_private *priv)
+{
+ /* Reset switch & memories */
+ writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT,
+ priv->regs[SYS] + SYS_SYSTEM_RST_CFG);
+
+ /* Wait to complete */
+ if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
+ SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
+ pr_err("Timeout in memory reset\n");
+ return -EIO;
+ }
+
+ /* Enable switch core */
+ setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
+ SYS_SYSTEM_RST_CORE_ENA);
+
+ return 0;
+}
+
+static void ocelot_switch_flush(struct ocelot_private *priv)
+{
+ /* All Queues flush */
+ setbits_le32(priv->regs[QS] + QS_XTR_FLUSH, QS_XTR_FLUSH_FLUSH);
+ /* Allow to drain */
+ mdelay(1);
+ /* All Queues normal */
+ clrbits_le32(priv->regs[QS] + QS_XTR_FLUSH, QS_XTR_FLUSH_FLUSH);
+}
+
+static int ocelot_initialize(struct ocelot_private *priv)
+{
+ int ret, i;
+
+ /* Initialize switch memories, enable core */
+ ret = ocelot_switch_init(priv);
+ if (ret)
+ return ret;
+ /*
+ * Disable port-to-port by switching
+ * Put fron ports in "port isolation modes" - i.e. they cant send
+ * to other ports - via the PGID sorce masks.
+ */
+ for (i = 0; i <= MAX_PORT; i++)
+ writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i));
+
+ /* Flush queues */
+ ocelot_switch_flush(priv);
+
+ /* Setup frame ageing - "2 sec" - The unit is 6.5us on Ocelot */
+ writel(SYS_FRM_AGING_ENA | (20000000 / 65),
+ priv->regs[SYS] + SYS_FRM_AGING);
+
+ for (i = PORT0; i <= PORT3; i++)
+ ocelot_port_init(priv, i);
+
+ ocelot_cpu_capture_setup(priv);
+
+ debug("Ports enabled\n");
+
+ return 0;
+}
+
+static inline int ocelot_vlant_wait_for_completion(struct ocelot_private *priv)
+{
+ unsigned int val, timeout = 10;
+
+ /* Wait for the issued mac table command to be completed, or timeout.
+ * When the command read from ANA_TABLES_MACACCESS is
+ * MACACCESS_CMD_IDLE, the issued command completed successfully.
+ */
+ do {
+ val = readl(priv->regs[ANA] + ANA_TABLES_MACACCESS);
+ val &= ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M;
+ } while (val != MACACCESS_CMD_IDLE && timeout--);
+
+ if (!timeout)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int ocelot_mac_table_add(struct ocelot_private *priv,
+ const unsigned char mac[ETH_ALEN], int pgid)
+{
+ u32 macl = 0, mach = 0;
+ int ret;
+
+ /* Set the MAC address to handle and the vlan associated in a format
+ * understood by the hardware.
+ */
+ mach |= MAC_VID << 16;
+ mach |= ((u32)mac[0]) << 8;
+ mach |= ((u32)mac[1]) << 0;
+ macl |= ((u32)mac[2]) << 24;
+ macl |= ((u32)mac[3]) << 16;
+ macl |= ((u32)mac[4]) << 8;
+ macl |= ((u32)mac[5]) << 0;
+
+ writel(macl, priv->regs[ANA] + ANA_TABLES_MACLDATA);
+ writel(mach, priv->regs[ANA] + ANA_TABLES_MACHDATA);
+
+ writel(ANA_TABLES_MACACCESS_VALID |
+ ANA_TABLES_MACACCESS_DEST_IDX(pgid) |
+ ANA_TABLES_MACACCESS_ENTRYTYPE(ENTRYTYPE_LOCKED) |
+ ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
+ priv->regs[ANA] + ANA_TABLES_MACACCESS);
+
+ ret = ocelot_vlant_wait_for_completion(priv);
+
+ return ret;
+}
+
+static int ocelot_write_hwaddr(struct udevice *dev)
+{
+ struct ocelot_private *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ ocelot_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
+
+ writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
+
+ return 0;
+}
+
+static int ocelot_start(struct udevice *dev)
+{
+ struct ocelot_private *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff };
+ int ret;
+
+ ret = ocelot_initialize(priv);
+ if (ret)
+ return ret;
+
+ /* Set MAC address tables entries for CPU redirection */
+ ocelot_mac_table_add(priv, mac, PGID_BROADCAST);
+
+ writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
+ priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
+
+ /* It should be setup latter in ocelot_write_hwaddr */
+ ocelot_mac_table_add(priv, pdata->enetaddr, PGID_UNICAST);
+
+ writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
+
+ return 0;
+}
+
+static int ocelot_send(struct udevice *dev, void *packet, int length)
+{
+ struct ocelot_private *priv = dev_get_priv(dev);
+ u32 ifh[IFH_LEN];
+ int port = BIT(0); /* use port 0 */
+ u8 grp = 0; /* Send everything on CPU group 0 */
+ int i, count = (length + 3) / 4, last = length % 4;
+ u32 *buf = packet;
+
+ writel(QS_INJ_CTRL_GAP_SIZE(1) | QS_INJ_CTRL_SOF,
+ priv->regs[QS] + QS_INJ_CTRL(grp));
+
+ /*
+ * Generate the IFH for frame injection
+ *
+ * The IFH is a 128bit-value
+ * bit 127: bypass the analyzer processing
+ * bit 56-67: destination mask
+ * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
+ * bit 20-27: cpu extraction queue mask
+ * bit 16: tag type 0: C-tag, 1: S-tag
+ * bit 0-11: VID
+ */
+ ifh[0] = IFH_INJ_BYPASS;
+ ifh[1] = (0xf00 & port) >> 8;
+ ifh[2] = (0xff & port) << 24;
+ ifh[3] = (IFH_TAG_TYPE_C << 16);
+
+ for (i = 0; i < IFH_LEN; i++)
+ writel(ifh[i], priv->regs[QS] + QS_INJ_WR(grp));
+
+ for (i = 0; i < count; i++)
+ writel(buf[i], priv->regs[QS] + QS_INJ_WR(grp));
+
+ /* Add padding */
+ while (i < (OCELOT_BUF_CELL_SZ / 4)) {
+ writel(0, priv->regs[QS] + QS_INJ_WR(grp));
+ i++;
+ }
+
+ /* Indicate EOF and valid bytes in last word */
+ writel(QS_INJ_CTRL_GAP_SIZE(1) |
+ QS_INJ_CTRL_VLD_BYTES(length < OCELOT_BUF_CELL_SZ ? 0 : last) |
+ QS_INJ_CTRL_EOF, priv->regs[QS] + QS_INJ_CTRL(grp));
+
+ /* Add dummy CRC */
+ writel(0, priv->regs[QS] + QS_INJ_WR(grp));
+
+ return 0;
+}
+
+static int ocelot_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct ocelot_private *priv = dev_get_priv(dev);
+ u8 grp = 0; /* Send everything on CPU group 0 */
+ u32 *rxbuf = (u32 *)net_rx_packets[0];
+ int i, byte_cnt = 0;
+ bool eof_flag = false, pruned_flag = false, abort_flag = false;
+
+ if (!(readl(priv->regs[QS] + QS_XTR_DATA_PRESENT) & BIT(grp)))
+ return -EAGAIN;
+
+ /* skip IFH */
+ for (i = 0; i < IFH_LEN; i++)
+ readl(priv->regs[QS] + QS_XTR_RD(grp));
+
+ while (!eof_flag) {
+ u32 val = readl(priv->regs[QS] + QS_XTR_RD(grp));
+
+ switch (val) {
+ case XTR_NOT_READY:
+ debug("%d NOT_READY...?\n", byte_cnt);
+ break;
+ case XTR_ABORT:
+ /* really nedeed?? not done in linux */
+ *rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
+ abort_flag = true;
+ eof_flag = true;
+ debug("XTR_ABORT\n");
+ break;
+ case XTR_EOF_0:
+ case XTR_EOF_1:
+ case XTR_EOF_2:
+ case XTR_EOF_3:
+ byte_cnt += XTR_VALID_BYTES(val);
+ *rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
+ eof_flag = true;
+ debug("EOF\n");
+ break;
+ case XTR_PRUNED:
+ /* But get the last 4 bytes as well */
+ eof_flag = true;
+ pruned_flag = true;
+ debug("PRUNED\n");
+ /* fallthrough */
+ case XTR_ESCAPE:
+ *rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
+ byte_cnt += 4;
+ rxbuf++;
+ debug("ESCAPED\n");
+ break;
+ default:
+ *rxbuf = val;
+ byte_cnt += 4;
+ rxbuf++;
+ }
+ }
+
+ if (abort_flag || pruned_flag || !eof_flag) {
+ debug("Discarded frame: abort:%d pruned:%d eof:%d\n",
+ abort_flag, pruned_flag, eof_flag);
+ return -EAGAIN;
+ }
+
+ *packetp = net_rx_packets[0];
+
+ return byte_cnt;
+}
+
+static int ocelot_probe(struct udevice *dev)
+{
+ struct ocelot_private *priv = dev_get_priv(dev);
+ int ret, i;
+
+ struct {
+ enum ocelot_target id;
+ char *name;
+ } reg[] = {
+ { SYS, "sys" },
+ { REW, "rew" },
+ { QSYS, "qsys" },
+ { ANA, "ana" },
+ { QS, "qs" },
+ { HSIO, "hsio" },
+ { PORT0, "port0" },
+ { PORT1, "port1" },
+ { PORT2, "port2" },
+ { PORT3, "port3" },
+ };
+
+ for (i = 0; i < ARRAY_SIZE(reg); i++) {
+ priv->regs[reg[i].id] = dev_remap_addr_name(dev, reg[i].name);
+ if (!priv->regs[reg[i].id]) {
+ pr_err
+ ("Error %d: can't get regs base addresses for %s\n",
+ ret, reg[i].name);
+ return -ENOMEM;
+ }
+ }
+
+ priv->bus[INTERNAL] = ocelot_mdiobus_init(dev);
+
+ for (i = 0; i < 4; i++) {
+ phy_connect(priv->bus[INTERNAL], i, dev,
+ PHY_INTERFACE_MODE_NONE);
+ }
+
+ return 0;
+}
+
+static int ocelot_remove(struct udevice *dev)
+{
+ struct ocelot_private *priv = dev_get_priv(dev);
+ int i;
+
+ for (i = 0; i < NUM_PHY; i++) {
+ mdio_unregister(priv->bus[i]);
+ mdio_free(priv->bus[i]);
+ }
+
+ return 0;
+}
+
+static const struct eth_ops ocelot_ops = {
+ .start = ocelot_start,
+ .stop = ocelot_stop,
+ .send = ocelot_send,
+ .recv = ocelot_recv,
+ .write_hwaddr = ocelot_write_hwaddr,
+};
+
+static const struct udevice_id mscc_ocelot_ids[] = {
+ {.compatible = "mscc,vsc7514-switch"},
+ { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(ocelot) = {
+ .name = "ocelot-switch",
+ .id = UCLASS_ETH,
+ .of_match = mscc_ocelot_ids,
+ .probe = ocelot_probe,
+ .remove = ocelot_remove,
+ .ops = &ocelot_ops,
+ .priv_auto_alloc_size = sizeof(struct ocelot_private),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index a0abb232992..12df09877de 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -3,6 +3,7 @@
* Aquantia PHY drivers
*
* Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
*/
#include <config.h>
#include <common.h>
@@ -19,6 +20,18 @@
#define AQUNTIA_SPEED_LSB_MASK 0x2000
#define AQUNTIA_SPEED_MSB_MASK 0x40
+#define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812
+#define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
+#define AQUANTIA_FIRMWARE_ID 0x20
+#define AQUANTIA_RESERVED_STATUS 0xc885
+#define AQUANTIA_FIRMWARE_MAJOR_MASK 0xff00
+#define AQUANTIA_FIRMWARE_MINOR_MASK 0xff
+#define AQUANTIA_FIRMWARE_BUILD_MASK 0xf0
+
+#define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
+#define AQUANTIA_SI_IN_USE_MASK 0x0078
+#define AQUANTIA_SI_USXGMII 0x0018
+
/* registers in MDIO_MMD_VEND1 region */
#define GLOBAL_FIRMWARE_ID 0x20
#define GLOBAL_FAULT 0xc850
@@ -244,6 +257,7 @@ static int aquantia_upload_firmware(struct phy_device *phydev)
int aquantia_config(struct phy_device *phydev)
{
u32 val, id, rstatus, fault;
+ u32 reg_val1 = 0;
id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
@@ -284,6 +298,21 @@ int aquantia_config(struct phy_device *phydev)
phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
AQUNTIA_SPEED_LSB_MASK |
AQUNTIA_SPEED_MSB_MASK);
+
+ val = phy_read(phydev, MDIO_MMD_PHYXS,
+ AQUANTIA_SYSTEM_INTERFACE_SR);
+ /* If SI is USXGMII then start USXGMII autoneg */
+ if ((val & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) {
+ phy_write(phydev, MDIO_MMD_PHYXS,
+ AQUANTIA_VENDOR_PROVISIONING_REG,
+ AQUANTIA_USX_AUTONEG_CONTROL_ENA);
+ printf("%s: system interface USXGMII\n",
+ phydev->dev->name);
+ } else {
+ printf("%s: system interface XFI\n",
+ phydev->dev->name);
+ }
+
} else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) {
/* 2.5GBASE-T mode */
phydev->advertising = SUPPORTED_1000baseT_Full;
@@ -299,6 +328,16 @@ int aquantia_config(struct phy_device *phydev)
val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
}
+
+ val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
+ reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
+
+ printf("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
+ phydev->drv->name,
+ (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
+ reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
+ (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
+
return 0;
}
diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c
index 3951535bf1f..63e7b0242b9 100644
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -123,8 +123,8 @@ static int ksz90x1_of_config_group(struct phy_device *phydev,
} else {
changed = 1; /* Value was changed in OF */
/* Calculate the register value and fix corner cases */
- if (val[i] > ps_to_regval * 0xf) {
- max = (1 << ofcfg->grp[i].size) - 1;
+ max = (1 << ofcfg->grp[i].size) - 1;
+ if (val[i] > ps_to_regval * max) {
regval |= max << offset;
} else {
regval |= (val[i] / ps_to_regval) << offset;
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index cda4caa8034..0c8b29dae44 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -620,7 +620,7 @@ static struct phy_driver *get_phy_driver(struct phy_device *phydev,
}
static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
- u32 phy_id,
+ u32 phy_id, bool is_c45,
phy_interface_t interface)
{
struct phy_device *dev;
@@ -650,6 +650,7 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
dev->addr = addr;
dev->phy_id = phy_id;
+ dev->is_c45 = is_c45;
dev->bus = bus;
dev->drv = get_phy_driver(dev, interface);
@@ -702,13 +703,17 @@ static struct phy_device *create_phy_by_mask(struct mii_dev *bus,
phy_interface_t interface)
{
u32 phy_id = 0xffffffff;
+ bool is_c45;
while (phy_mask) {
int addr = ffs(phy_mask) - 1;
int r = get_phy_id(bus, addr, devad, &phy_id);
/* If the PHY ID is mostly f's, we didn't find anything */
- if (r == 0 && (phy_id & 0x1fffffff) != 0x1fffffff)
- return phy_device_create(bus, addr, phy_id, interface);
+ if (r == 0 && (phy_id & 0x1fffffff) != 0x1fffffff) {
+ is_c45 = (devad == MDIO_DEVAD_NONE) ? false : true;
+ return phy_device_create(bus, addr, phy_id, is_c45,
+ interface);
+ }
phy_mask &= ~(1 << addr);
}
return NULL;
@@ -876,18 +881,18 @@ void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev)
debug("%s connected to %s\n", dev->name, phydev->drv->name);
}
+#ifdef CONFIG_PHY_FIXED
#ifdef CONFIG_DM_ETH
-struct phy_device *phy_connect(struct mii_dev *bus, int addr,
- struct udevice *dev,
- phy_interface_t interface)
+static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
+ struct udevice *dev,
+ phy_interface_t interface)
#else
-struct phy_device *phy_connect(struct mii_dev *bus, int addr,
- struct eth_device *dev,
- phy_interface_t interface)
+static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
+ struct eth_device *dev,
+ phy_interface_t interface)
#endif
{
struct phy_device *phydev = NULL;
-#ifdef CONFIG_PHY_FIXED
int sn;
const char *name;
@@ -895,13 +900,33 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr,
while (sn > 0) {
name = fdt_get_name(gd->fdt_blob, sn, NULL);
if (name && strcmp(name, "fixed-link") == 0) {
- phydev = phy_device_create(bus,
- sn, PHY_FIXED_ID, interface);
+ phydev = phy_device_create(bus, sn, PHY_FIXED_ID, false,
+ interface);
break;
}
sn = fdt_next_subnode(gd->fdt_blob, sn);
}
+
+ return phydev;
+}
+#endif
+
+#ifdef CONFIG_DM_ETH
+struct phy_device *phy_connect(struct mii_dev *bus, int addr,
+ struct udevice *dev,
+ phy_interface_t interface)
+#else
+struct phy_device *phy_connect(struct mii_dev *bus, int addr,
+ struct eth_device *dev,
+ phy_interface_t interface)
#endif
+{
+ struct phy_device *phydev = NULL;
+
+#ifdef CONFIG_PHY_FIXED
+ phydev = phy_connect_fixed(bus, dev, interface);
+#endif
+
if (!phydev)
phydev = phy_find_by_mask(bus, 1 << addr, interface);
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index b3e6578df9a..dd45e11b3ad 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -57,6 +57,33 @@
#define MIIM_RTL8211F_TX_DELAY 0x100
#define MIIM_RTL8211F_LCR 0x10
+static int rtl8211f_phy_extread(struct phy_device *phydev, int addr,
+ int devaddr, int regnum)
+{
+ int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
+ MIIM_RTL8211F_PAGE_SELECT);
+ int val;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
+
+ return val;
+}
+
+static int rtl8211f_phy_extwrite(struct phy_device *phydev, int addr,
+ int devaddr, int regnum, u16 val)
+{
+ int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
+ MIIM_RTL8211F_PAGE_SELECT);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
+ phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
+
+ return 0;
+}
+
static int rtl8211b_probe(struct phy_device *phydev)
{
#ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER
@@ -336,6 +363,8 @@ static struct phy_driver RTL8211F_driver = {
.config = &rtl8211f_config,
.startup = &rtl8211f_startup,
.shutdown = &genphy_shutdown,
+ .readext = &rtl8211f_phy_extread,
+ .writeext = &rtl8211f_phy_extwrite,
};
int phy_realtek_init(void)
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
index 590f8ce1542..13309970e2c 100644
--- a/drivers/net/rtl8139.c
+++ b/drivers/net/rtl8139.c
@@ -183,12 +183,10 @@ static void rtl_reset(struct eth_device *dev);
static int rtl_transmit(struct eth_device *dev, void *packet, int length);
static int rtl_poll(struct eth_device *dev);
static void rtl_disable(struct eth_device *dev);
-#ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */
-static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, u8 set)
+static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, int join)
{
return (0);
}
-#endif
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
@@ -229,9 +227,7 @@ int rtl8139_initialize(bd_t *bis)
dev->halt = rtl_disable;
dev->send = rtl_transmit;
dev->recv = rtl_poll;
-#ifdef CONFIG_MCAST_TFTP
dev->mcast = rtl_bcast_addr;
-#endif
eth_register (dev);
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 03a46da2f8a..06a9b4fb03c 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -78,7 +78,30 @@ static void tsec_configure_serdes(struct tsec_private *priv)
0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
}
-#ifdef CONFIG_MCAST_TFTP
+/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
+ * and this is the ethernet-crc method needed for TSEC -- and perhaps
+ * some other adapter -- hash tables
+ */
+#define CRCPOLY_LE 0xedb88320
+static u32 ether_crc(size_t len, unsigned char const *p)
+{
+ int i;
+ u32 crc;
+
+ crc = ~0;
+ while (len--) {
+ crc ^= *p++;
+ for (i = 0; i < 8; i++)
+ crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
+ }
+ /* an reverse the bits, cuz of way they arrive -- last-first */
+ crc = (crc >> 16) | (crc << 16);
+ crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
+ crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
+ crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
+ crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
+ return crc;
+}
/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
@@ -99,9 +122,10 @@ static void tsec_configure_serdes(struct tsec_private *priv)
* the entry.
*/
#ifndef CONFIG_DM_ETH
-static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
+static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
+ int join)
#else
-static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int set)
+static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
#endif
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
@@ -115,14 +139,13 @@ static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int set)
value = BIT(31 - whichbit);
- if (set)
+ if (join)
setbits_be32(&regs->hash.gaddr0 + whichreg, value);
else
clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
return 0;
}
-#endif /* Multicast TFTP ? */
/*
* Initialized required registers to appropriate values, zeroing
@@ -720,9 +743,7 @@ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
dev->halt = tsec_halt;
dev->send = tsec_send;
dev->recv = tsec_recv;
-#ifdef CONFIG_MCAST_TFTP
dev->mcast = tsec_mcast_addr;
-#endif
/* Tell U-Boot to get the addr from the env */
for (i = 0; i < 6; i++)
@@ -862,9 +883,7 @@ static const struct eth_ops tsec_ops = {
.recv = tsec_recv,
.free_pkt = tsec_free_pkt,
.stop = tsec_halt,
-#ifdef CONFIG_MCAST_TFTP
.mcast = tsec_mcast_addr,
-#endif
};
static const struct udevice_id tsec_ids[] = {
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 9bd79b198a2..3bd0093b7ab 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -570,11 +570,6 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
addr &= ~(ARCH_DMA_MINALIGN - 1);
size = roundup(len, ARCH_DMA_MINALIGN);
flush_dcache_range(addr, addr + size);
-
- addr = (ulong)priv->rxbuffers;
- addr &= ~(ARCH_DMA_MINALIGN - 1);
- size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
- flush_dcache_range(addr, addr + size);
barrier();
/* Start transmit */
@@ -621,6 +616,9 @@ static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
*packetp = (uchar *)(uintptr_t)addr;
+ invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
+ barrier();
+
return frame_len;
}
@@ -706,6 +704,9 @@ static int zynq_gem_probe(struct udevice *dev)
return -ENOMEM;
memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
+ u32 addr = (ulong)priv->rxbuffers;
+ flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
+ barrier();
/* Align bd_space to MMU_SECTION_SHIFT */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
generated by cgit v1.2.3 (git 2.0.4) at 2025-09-22 18:18:49 +0000