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-rw-r--r--drivers/pci/Kconfig8
-rw-r--r--drivers/pci/pci-uclass.c9
-rw-r--r--drivers/pci/pci_auto.c39
-rw-r--r--drivers/pci/pcie_iproc.c7
4 files changed, 34 insertions, 29 deletions
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index e4123ba820f..cc139af6cb5 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -21,7 +21,6 @@ config DM_PCI_COMPAT
config PCI_AARDVARK
bool "Enable Aardvark PCIe driver"
- default n
depends on DM_GPIO
depends on ARMADA_3700
help
@@ -37,7 +36,6 @@ config PCI_PNP
config PCI_REGION_MULTI_ENTRY
bool "Enable Multiple entries of region type MEMORY in ranges for PCI"
- default n
help
Enable PCI memory regions to be of multiple entry. Multiple entry
here refers to allow more than one count of address ranges for MEMORY
@@ -47,7 +45,6 @@ config PCI_REGION_MULTI_ENTRY
config PCI_MAP_SYSTEM_MEMORY
bool "Map local system memory from a virtual base address"
depends on MIPS
- default n
help
Say Y if base address of system memory is being used as a virtual address
instead of a physical address (e.g. on MIPS). The PCI core will then remap
@@ -58,7 +55,6 @@ config PCI_MAP_SYSTEM_MEMORY
config PCI_SRIOV
bool "Enable Single Root I/O Virtualization support for PCI"
- default n
help
Say Y here if you want to enable PCI Single Root I/O Virtualization
capability support. This helps to enumerate Virtual Function devices
@@ -67,7 +63,6 @@ config PCI_SRIOV
config PCI_ARID
bool "Enable Alternate Routing-ID support for PCI"
- default n
help
Say Y here if you want to enable Alternate Routing-ID capability
support on PCI devices. This helps to skip some devices in BDF
@@ -75,14 +70,12 @@ config PCI_ARID
config PCIE_ECAM_GENERIC
bool "Generic ECAM-based PCI host controller support"
- default n
help
Say Y here if you want to enable support for generic ECAM-based
PCIe host controllers, such as the one emulated by QEMU.
config PCIE_ECAM_SYNQUACER
bool "SynQuacer ECAM-based PCI host controller support"
- default n
select PCI_INIT_R
select PCI_REGION_MULTI_ENTRY
help
@@ -186,7 +179,6 @@ config PCI_XILINX
config PCIE_LAYERSCAPE
bool
- default n
config PCIE_LAYERSCAPE_RC
bool "Layerscape PCIe Root Complex mode support"
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index ce2eb5da2ca..4d0e938fe50 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -856,10 +856,7 @@ int pci_bind_bus_devices(struct udevice *bus)
/* Check only the first access, we don't expect problems */
ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
PCI_SIZE_16);
- if (ret)
- goto error;
-
- if (vendor == 0xffff || vendor == 0x0000)
+ if (ret || vendor == 0xffff || vendor == 0x0000)
continue;
pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
@@ -940,10 +937,6 @@ int pci_bind_bus_devices(struct udevice *bus)
}
return 0;
-error:
- printf("Cannot read bus configuration: %d\n", ret);
-
- return ret;
}
static void decode_regions(struct pci_controller *hose, ofnode parent_node,
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index b128a05dd38..7b6e629cae7 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -165,6 +165,7 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
u16 cmdstat, prefechable_64;
+ u8 io_32;
struct udevice *ctlr = pci_get_controller(dev);
struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
@@ -175,6 +176,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+ dm_pci_read_config8(dev, PCI_IO_LIMIT, &io_32);
+ io_32 &= PCI_IO_RANGE_TYPE_MASK;
/* Configure bus number registers */
dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
@@ -191,7 +194,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
* I/O space
*/
dm_pci_write_config16(dev, PCI_MEMORY_BASE,
- (pci_mem->bus_lower & 0xfff00000) >> 16);
+ ((pci_mem->bus_lower & 0xfff00000) >> 16) &
+ PCI_MEMORY_RANGE_MASK);
cmdstat |= PCI_COMMAND_MEMORY;
}
@@ -205,7 +209,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
* I/O space
*/
dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
- (pci_prefetch->bus_lower & 0xfff00000) >> 16);
+ (((pci_prefetch->bus_lower & 0xfff00000) >> 16) &
+ PCI_PREF_RANGE_MASK) | prefechable_64);
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
#ifdef CONFIG_SYS_PCI_64BIT
dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
@@ -217,8 +222,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
cmdstat |= PCI_COMMAND_MEMORY;
} else {
/* We don't support prefetchable memory for now, so disable */
- dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
- dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000 |
+ prefechable_64);
+ dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 |
+ prefechable_64);
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
@@ -230,8 +237,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
pciauto_region_align(pci_io, 0x1000);
dm_pci_write_config8(dev, PCI_IO_BASE,
- (pci_io->bus_lower & 0x0000f000) >> 8);
- dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
+ (((pci_io->bus_lower & 0x0000f000) >> 8) &
+ PCI_IO_RANGE_MASK) | io_32);
+ if (io_32 == PCI_IO_RANGE_TYPE_32)
+ dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
(pci_io->bus_lower & 0xffff0000) >> 16);
cmdstat |= PCI_COMMAND_IO;
@@ -261,7 +270,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
pciauto_region_align(pci_mem, 0x100000);
dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
- (pci_mem->bus_lower - 1) >> 16);
+ ((pci_mem->bus_lower - 1) >> 16) &
+ PCI_MEMORY_RANGE_MASK);
}
if (pci_prefetch) {
@@ -275,7 +285,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
pciauto_region_align(pci_prefetch, 0x100000);
dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
- (pci_prefetch->bus_lower - 1) >> 16);
+ (((pci_prefetch->bus_lower - 1) >> 16) &
+ PCI_PREF_RANGE_MASK) | prefechable_64);
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
#ifdef CONFIG_SYS_PCI_64BIT
dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
@@ -286,12 +297,20 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
}
if (pci_io) {
+ u8 io_32;
+
+ dm_pci_read_config8(dev, PCI_IO_LIMIT,
+ &io_32);
+ io_32 &= PCI_IO_RANGE_TYPE_MASK;
+
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
dm_pci_write_config8(dev, PCI_IO_LIMIT,
- ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
- dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
+ ((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) &
+ PCI_IO_RANGE_MASK) | io_32);
+ if (io_32 == PCI_IO_RANGE_TYPE_32)
+ dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
}
}
diff --git a/drivers/pci/pcie_iproc.c b/drivers/pci/pcie_iproc.c
index 12ce9d525ca..be03dcbd97c 100644
--- a/drivers/pci/pcie_iproc.c
+++ b/drivers/pci/pcie_iproc.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2020 Broadcom
+ * Copyright (C) 2020-2021 Broadcom
*
*/
@@ -12,6 +12,7 @@
#include <malloc.h>
#include <asm/io.h>
#include <dm/device_compat.h>
+#include <linux/delay.h>
#include <linux/log2.h>
#define EP_PERST_SOURCE_SELECT_SHIFT 2
@@ -884,7 +885,7 @@ static int iproc_pcie_map_ranges(struct udevice *dev)
for (i = 0; i < hose->region_count; i++) {
if (hose->regions[i].flags == PCI_REGION_MEM ||
hose->regions[i].flags == PCI_REGION_PREFETCH) {
- debug("%d: bus_addr %p, axi_addr %p, size 0x%lx\n",
+ debug("%d: bus_addr %p, axi_addr %p, size 0x%llx\n",
i, &hose->regions[i].bus_start,
&hose->regions[i].phys_start,
hose->regions[i].size);
@@ -1049,7 +1050,7 @@ static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie)
while (!pci_get_dma_regions(pcie->dev, &regions, i)) {
dev_dbg(pcie->dev,
- "dma %d: bus_addr %#lx, axi_addr %#llx, size %#lx\n",
+ "dma %d: bus_addr %#llx, axi_addr %#llx, size %#llx\n",
i, regions.bus_start, regions.phys_start, regions.size);
/* Each range entry corresponds to an inbound mapping region */
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-18 19:15:18 +0000