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-rw-r--r--drivers/pci/Kconfig24
-rw-r--r--drivers/pci/Makefile2
-rw-r--r--drivers/pci/pcie_layerscape.c3
-rw-r--r--drivers/pci/pcie_layerscape.h3
-rw-r--r--drivers/pci/pcie_layerscape_fixup.c24
-rw-r--r--drivers/pci/pcie_layerscape_gen4_fixup.c24
6 files changed, 55 insertions, 25 deletions
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 13603b9d57d..437cd9a055d 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -143,6 +143,30 @@ config PCIE_LAYERSCAPE_GEN4
several PCIe controllers. The PCIe controller can work in RC or
EP mode according to RCW[HOST_AGT_PEX] setting.
+config FSL_PCIE_COMPAT
+ string "PCIe compatible of Kernel DT"
+ depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
+ default "fsl,ls1012a-pcie" if ARCH_LS1012A
+ default "fsl,ls1028a-pcie" if ARCH_LS1028A
+ default "fsl,ls1043a-pcie" if ARCH_LS1043A
+ default "fsl,ls1046a-pcie" if ARCH_LS1046A
+ default "fsl,ls2080a-pcie" if ARCH_LS2080A
+ default "fsl,ls1088a-pcie" if ARCH_LS1088A
+ default "fsl,lx2160a-pcie" if ARCH_LX2160A
+ default "fsl,ls1021a-pcie" if ARCH_LS1021A
+ help
+ This compatible is used to find pci controller node in Kernel DT
+ to complete fixup.
+
+config FSL_PCIE_EP_COMPAT
+ string "PCIe EP compatible of Kernel DT"
+ depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
+ default "fsl,lx2160a-pcie-ep" if ARCH_LX2160A
+ default "fsl,ls-pcie-ep"
+ help
+ This compatible is used to find pci controller ep node in Kernel DT
+ to complete fixup.
+
config PCIE_INTEL_FPGA
bool "Intel FPGA PCIe support"
depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index da8b826d69c..8a33eb02665 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -36,7 +36,7 @@ obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
- pcie_layerscape_gen4_fixup.o
+ pcie_layerscape_gen4_fixup.o pcie_layerscape.o
obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 5ad7c287735..47394bdba71 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*/
@@ -339,6 +339,7 @@ static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
ls_pcie_disable_bars(pcie);
+ pcie->stream_id_cur = 0;
}
static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index ddfbba65384..95454bc1886 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*/
@@ -144,6 +144,7 @@ struct ls_pcie {
bool big_endian;
bool enabled;
int next_lut_index;
+ int stream_id_cur;
int mode;
};
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index 089e031724a..27ef20d4c3d 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017 NXP
+ * Copyright 2017-2019 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Layerscape PCIe driver
*/
@@ -69,8 +69,8 @@ static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
* msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
* [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
*/
-static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
- u32 devid, u32 streamid)
+static void fdt_pcie_set_msi_map_entry_ls(void *blob, struct ls_pcie *pcie,
+ u32 devid, u32 streamid)
{
u32 *prop;
u32 phandle;
@@ -122,8 +122,8 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
* iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
* [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
*/
-static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
- u32 devid, u32 streamid)
+static void fdt_pcie_set_iommu_map_entry_ls(void *blob, struct ls_pcie *pcie,
+ u32 devid, u32 streamid)
{
u32 *prop;
u32 iommu_map[4];
@@ -175,7 +175,7 @@ static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
}
}
-static void fdt_fixup_pcie(void *blob)
+static void fdt_fixup_pcie_ls(void *blob)
{
struct udevice *dev, *bus;
struct ls_pcie *pcie;
@@ -209,11 +209,11 @@ static void fdt_fixup_pcie(void *blob)
ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
streamid);
/* update msi-map in device tree */
- fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
- streamid);
+ fdt_pcie_set_msi_map_entry_ls(blob, pcie, bdf >> 8,
+ streamid);
/* update iommu-map in device tree */
- fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
- streamid);
+ fdt_pcie_set_iommu_map_entry_ls(blob, pcie, bdf >> 8,
+ streamid);
}
}
#endif
@@ -253,7 +253,7 @@ static void ft_pcie_ep_fix(void *blob, struct ls_pcie *pcie)
{
int off;
- off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie-ep",
+ off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
pcie->dbi_res.start);
if (off < 0)
return;
@@ -279,7 +279,7 @@ void ft_pci_setup(void *blob, bd_t *bd)
ft_pcie_ls_setup(blob, pcie);
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
- fdt_fixup_pcie(blob);
+ fdt_fixup_pcie_ls(blob);
#endif
}
diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c b/drivers/pci/pcie_layerscape_gen4_fixup.c
index 1c9e5750bdb..da9817159fd 100644
--- a/drivers/pci/pcie_layerscape_gen4_fixup.c
+++ b/drivers/pci/pcie_layerscape_gen4_fixup.c
@@ -37,7 +37,7 @@ static int ls_pcie_g4_next_streamid(struct ls_pcie_g4 *pcie)
{
int stream_id = pcie->stream_id_cur;
- if (stream_id > FSL_PEX_STREAM_ID_NUM)
+ if (stream_id > FSL_PEX_STREAM_ID_END)
return -EINVAL;
pcie->stream_id_cur++;
@@ -64,8 +64,9 @@ static void ls_pcie_g4_lut_set_mapping(struct ls_pcie_g4 *pcie, int index,
* msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
* [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
*/
-static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie_g4 *pcie,
- u32 devid, u32 streamid)
+static void fdt_pcie_set_msi_map_entry_ls_gen4(void *blob,
+ struct ls_pcie_g4 *pcie,
+ u32 devid, u32 streamid)
{
u32 *prop;
u32 phandle;
@@ -106,8 +107,9 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie_g4 *pcie,
* iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
* [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
*/
-static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie_g4 *pcie,
- u32 devid, u32 streamid)
+static void fdt_pcie_set_iommu_map_entry_ls_gen4(void *blob,
+ struct ls_pcie_g4 *pcie,
+ u32 devid, u32 streamid)
{
u32 *prop;
u32 iommu_map[4];
@@ -145,7 +147,7 @@ static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie_g4 *pcie,
fdt_appendprop(blob, nodeoff, "iommu-map", iommu_map, 16);
}
-static void fdt_fixup_pcie(void *blob)
+static void fdt_fixup_pcie_ls_gen4(void *blob)
{
struct udevice *dev, *bus;
struct ls_pcie_g4 *pcie;
@@ -176,9 +178,11 @@ static void fdt_fixup_pcie(void *blob)
/* map PCI b.d.f to streamID in LUT */
ls_pcie_g4_lut_set_mapping(pcie, index, bdf >> 8, streamid);
/* update msi-map in device tree */
- fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, streamid);
+ fdt_pcie_set_msi_map_entry_ls_gen4(blob, pcie, bdf >> 8,
+ streamid);
/* update iommu-map in device tree */
- fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8, streamid);
+ fdt_pcie_set_iommu_map_entry_ls_gen4(blob, pcie, bdf >> 8,
+ streamid);
}
}
#endif
@@ -187,7 +191,7 @@ static void ft_pcie_ep_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
{
int off;
- off = fdt_node_offset_by_compat_reg(blob, "fsl,lx2160a-pcie-ep",
+ off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
pcie->ccsr_res.start);
if (off < 0) {
@@ -238,7 +242,7 @@ void ft_pci_setup(void *blob, bd_t *bd)
ft_pcie_layerscape_gen4_setup(blob, pcie);
#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
- fdt_fixup_pcie(blob);
+ fdt_fixup_pcie_ls_gen4(blob);
#endif
}
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-24 22:20:37 +0000