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-rw-r--r--drivers/phy/Kconfig9
-rw-r--r--drivers/phy/Makefile1
-rw-r--r--drivers/phy/omap-usb2-phy.c196
-rw-r--r--drivers/phy/ti-pipe3-phy.c32
4 files changed, 230 insertions, 8 deletions
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 14d82b93ed1..3921e39d7bc 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -155,4 +155,13 @@ config MSM8916_USB_PHY
This PHY is found on qualcomm dragonboard410c development board.
+config OMAP_USB2_PHY
+ bool "Support OMAP's USB2 PHY"
+ depends on PHY
+ depends on SYSCON
+ help
+ Support for the OMAP's USB2 PHY.
+
+ This PHY is found on OMAP devices supporting USB2.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 8030d599e75..53dd5bd0f77 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o
obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o
obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
+obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o
diff --git a/drivers/phy/omap-usb2-phy.c b/drivers/phy/omap-usb2-phy.c
new file mode 100644
index 00000000000..fd20e8c1688
--- /dev/null
+++ b/drivers/phy/omap-usb2-phy.c
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OMAP USB2 PHY LAYER
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#define OMAP_USB2_CALIBRATE_FALSE_DISCONNECT BIT(0)
+
+#define OMAP_DEV_PHY_PD BIT(0)
+#define OMAP_USB2_PHY_PD BIT(28)
+
+#define USB2PHY_DISCON_BYP_LATCH BIT(31)
+#define USB2PHY_ANA_CONFIG1 (0x4c)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct omap_usb2_phy {
+ struct regmap *pwr_regmap;
+ ulong flags;
+ void *phy_base;
+ u32 pwr_reg_offset;
+};
+
+struct usb_phy_data {
+ const char *label;
+ u8 flags;
+ u32 mask;
+ u32 power_on;
+ u32 power_off;
+};
+
+static const struct usb_phy_data omap5_usb2_data = {
+ .label = "omap5_usb2",
+ .flags = 0,
+ .mask = OMAP_DEV_PHY_PD,
+ .power_off = OMAP_DEV_PHY_PD,
+};
+
+static const struct usb_phy_data dra7x_usb2_data = {
+ .label = "dra7x_usb2",
+ .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+ .mask = OMAP_DEV_PHY_PD,
+ .power_off = OMAP_DEV_PHY_PD,
+};
+
+static const struct usb_phy_data dra7x_usb2_phy2_data = {
+ .label = "dra7x_usb2_phy2",
+ .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+ .mask = OMAP_USB2_PHY_PD,
+ .power_off = OMAP_USB2_PHY_PD,
+};
+
+static const struct udevice_id omap_usb2_id_table[] = {
+ {
+ .compatible = "ti,omap5-usb2",
+ .data = (ulong)&omap5_usb2_data,
+ },
+ {
+ .compatible = "ti,dra7x-usb2",
+ .data = (ulong)&dra7x_usb2_data,
+ },
+ {
+ .compatible = "ti,dra7x-usb2-phy2",
+ .data = (ulong)&dra7x_usb2_phy2_data,
+ },
+ {},
+};
+
+static int omap_usb_phy_power(struct phy *usb_phy, bool on)
+{
+ struct udevice *dev = usb_phy->dev;
+ const struct usb_phy_data *data;
+ const struct omap_usb2_phy *phy = dev_get_priv(dev);
+ u32 val;
+ int rc;
+
+ data = (const struct usb_phy_data *)dev_get_driver_data(dev);
+ if (!data)
+ return -EINVAL;
+
+ rc = regmap_read(phy->pwr_regmap, phy->pwr_reg_offset, &val);
+ if (rc)
+ return rc;
+ val &= ~data->mask;
+ if (on)
+ val |= data->power_on;
+ else
+ val |= data->power_off;
+ rc = regmap_write(phy->pwr_regmap, phy->pwr_reg_offset, val);
+ if (rc)
+ return rc;
+
+ return 0;
+}
+
+static int omap_usb2_phy_init(struct phy *usb_phy)
+{
+ struct udevice *dev = usb_phy->dev;
+ struct omap_usb2_phy *priv = dev_get_priv(dev);
+ u32 val;
+
+ if (priv->flags & OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) {
+ /*
+ *
+ * Reduce the sensitivity of internal PHY by enabling the
+ * DISCON_BYP_LATCH of the USB2PHY_ANA_CONFIG1 register. This
+ * resolves issues with certain devices which can otherwise
+ * be prone to false disconnects.
+ *
+ */
+ val = readl(priv->phy_base + USB2PHY_ANA_CONFIG1);
+ val |= USB2PHY_DISCON_BYP_LATCH;
+ writel(val, priv->phy_base + USB2PHY_ANA_CONFIG1);
+ }
+
+ return 0;
+}
+
+static int omap_usb2_phy_power_on(struct phy *usb_phy)
+{
+ return omap_usb_phy_power(usb_phy, true);
+}
+
+static int omap_usb2_phy_power_off(struct phy *usb_phy)
+{
+ return omap_usb_phy_power(usb_phy, false);
+}
+
+static int omap_usb2_phy_exit(struct phy *usb_phy)
+{
+ return omap_usb_phy_power(usb_phy, false);
+}
+
+struct phy_ops omap_usb2_phy_ops = {
+ .init = omap_usb2_phy_init,
+ .power_on = omap_usb2_phy_power_on,
+ .power_off = omap_usb2_phy_power_off,
+ .exit = omap_usb2_phy_exit,
+};
+
+int omap_usb2_phy_probe(struct udevice *dev)
+{
+ int rc;
+ struct regmap *regmap;
+ struct omap_usb2_phy *priv = dev_get_priv(dev);
+ const struct usb_phy_data *data;
+ u32 tmp[2];
+
+ data = (const struct usb_phy_data *)dev_get_driver_data(dev);
+ if (!data)
+ return -EINVAL;
+
+ if (data->flags & OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) {
+ u32 base = dev_read_addr(dev);
+
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ priv->phy_base = (void *)base;
+ priv->flags |= OMAP_USB2_CALIBRATE_FALSE_DISCONNECT;
+ }
+
+ regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-phy-power");
+ if (IS_ERR(regmap)) {
+ printf("can't get regmap (err %ld)\n", PTR_ERR(regmap));
+ return PTR_ERR(regmap);
+ }
+ priv->pwr_regmap = regmap;
+
+ rc = dev_read_u32_array(dev, "syscon-phy-power", tmp, 2);
+ if (rc) {
+ printf("couldn't get power reg. offset (err %d)\n", rc);
+ return rc;
+ }
+ priv->pwr_reg_offset = tmp[1];
+
+ return 0;
+}
+
+U_BOOT_DRIVER(omap_usb2_phy) = {
+ .name = "omap_usb2_phy",
+ .id = UCLASS_PHY,
+ .of_match = omap_usb2_id_table,
+ .probe = omap_usb2_phy_probe,
+ .ops = &omap_usb2_phy_ops,
+ .priv_auto_alloc_size = sizeof(struct omap_usb2_phy),
+};
diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c
index b22bbaf9851..e7e78e3c56d 100644
--- a/drivers/phy/ti-pipe3-phy.c
+++ b/drivers/phy/ti-pipe3-phy.c
@@ -141,7 +141,7 @@ static int omap_pipe3_dpll_program(struct omap_pipe3 *pipe3)
omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
- val &= ~PLL_SELFREQDCO_MASK;
+ val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE);
val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
@@ -265,10 +265,13 @@ static int pipe3_exit(struct phy *phy)
return -EBUSY;
}
- val = readl(pipe3->pll_reset_reg);
- writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
- mdelay(1);
- writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
+ if (pipe3->pll_reset_reg) {
+ val = readl(pipe3->pll_reset_reg);
+ writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
+ mdelay(1);
+ writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
+ }
+
return 0;
}
@@ -331,9 +334,11 @@ static int pipe3_phy_probe(struct udevice *dev)
if (!pipe3->power_reg)
return -EINVAL;
- pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
- if (!pipe3->pll_reset_reg)
- return -EINVAL;
+ if (device_is_compatible(dev, "ti,phy-pipe3-sata")) {
+ pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
+ if (!pipe3->pll_reset_reg)
+ return -EINVAL;
+ }
pipe3->dpll_map = (struct pipe3_dpll_map *)dev_get_driver_data(dev);
@@ -350,8 +355,19 @@ static struct pipe3_dpll_map dpll_map_sata[] = {
{ }, /* Terminator */
};
+static struct pipe3_dpll_map dpll_map_usb[] = {
+ {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
+ {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
+ {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
+ {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
+ {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
+ {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
+ { }, /* Terminator */
+};
+
static const struct udevice_id pipe3_phy_ids[] = {
{ .compatible = "ti,phy-pipe3-sata", .data = (ulong)&dpll_map_sata },
+ { .compatible = "ti,omap-usb3", .data = (ulong)&dpll_map_usb},
{ }
};
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-25 13:23:02 +0000