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-rw-r--r--drivers/phy/phy-stm32-usbphyc.c18
-rw-r--r--drivers/phy/rockchip/Kconfig9
-rw-r--r--drivers/phy/rockchip/Makefile1
-rw-r--r--drivers/phy/rockchip/phy-rockchip-snps-pcie3.c157
4 files changed, 177 insertions, 8 deletions
diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c
index f23aef4fb01..02d859a0398 100644
--- a/drivers/phy/phy-stm32-usbphyc.c
+++ b/drivers/phy/phy-stm32-usbphyc.c
@@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_PHY
+
#include <common.h>
#include <clk.h>
#include <div64.h>
@@ -98,8 +100,8 @@ static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
u32 usbphyc_pll;
if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
- pr_debug("%s: input clk freq (%dHz) out of range\n",
- __func__, clk_rate);
+ log_debug("input clk freq (%dHz) out of range\n",
+ clk_rate);
return -EINVAL;
}
@@ -116,8 +118,8 @@ static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
- pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
- clk_rate, pll_params.ndiv, pll_params.frac);
+ log_debug("input clk freq=%dHz, ndiv=%d, frac=%d\n",
+ clk_rate, pll_params.ndiv, pll_params.frac);
return 0;
}
@@ -154,7 +156,7 @@ static int stm32_usbphyc_phy_init(struct phy *phy)
true : false;
int ret;
- pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
/* Check if one phy port has already configured the pll */
if (pllen && stm32_usbphyc_is_init(usbphyc))
goto initialized;
@@ -200,7 +202,7 @@ static int stm32_usbphyc_phy_exit(struct phy *phy)
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
- pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
usbphyc_phy->init = false;
/* Check if other phy port requires pllen */
@@ -239,7 +241,7 @@ static int stm32_usbphyc_phy_power_on(struct phy *phy)
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
- pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
if (usbphyc_phy->vdd) {
ret = regulator_set_enable(usbphyc_phy->vdd, true);
if (ret)
@@ -262,7 +264,7 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy)
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
- pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
usbphyc_phy->powered = false;
if (stm32_usbphyc_is_powered(usbphyc))
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 2318e71f356..e477a6cd9e9 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -18,6 +18,15 @@ config PHY_ROCKCHIP_PCIE
help
Enable this to support the Rockchip PCIe PHY.
+config PHY_ROCKCHIP_SNPS_PCIE3
+ bool "Rockchip Snps PCIe3 PHY Driver"
+ depends on PHY && ARCH_ROCKCHIP
+ help
+ Support for Rockchip PCIe3 PHY with Synopsys IP block.
+ It could support PCIe Gen3 single root complex, and could
+ also be able splited into multiple combinations of lanes.
+
+
config PHY_ROCKCHIP_TYPEC
bool "Rockchip TYPEC PHY Driver"
depends on ARCH_ROCKCHIP
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index 44049154f9d..f6ad3bf59ae 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -5,4 +5,5 @@
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
+obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
new file mode 100644
index 00000000000..5ae41fbeeec
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip PCIE3.0 phy driver
+ *
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <reset-uclass.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+
+#define GRF_PCIE30PHY_CON1 0x4
+#define GRF_PCIE30PHY_CON6 0x18
+#define GRF_PCIE30PHY_CON9 0x24
+
+/**
+ * struct rockchip_p3phy_priv - RK DW PCIe PHY state
+ *
+ * @mmio: The base address of PHY internal registers
+ * @phy_grf: The regmap for controlling pipe signal
+ * @p30phy: The reset signal for PHY
+ * @ref_clk_m: The reference clock of M for PHY
+ * @ref_clk_n: The reference clock of N for PHY
+ * @pclk: The clock for accessing PHY blocks
+ */
+struct rockchip_p3phy_priv {
+ void __iomem *mmio;
+ struct regmap *phy_grf;
+ struct reset_ctl p30phy;
+ struct clk ref_clk_m;
+ struct clk ref_clk_n;
+ struct clk pclk;
+};
+
+static int rochchip_p3phy_init(struct phy *phy)
+{
+ struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
+ int ret;
+
+ ret = clk_enable(&priv->ref_clk_m);
+ if (ret < 0 && ret != -ENOSYS)
+ return ret;
+
+ ret = clk_enable(&priv->ref_clk_n);
+ if (ret < 0 && ret != -ENOSYS)
+ goto err_ref;
+
+ ret = clk_enable(&priv->pclk);
+ if (ret < 0 && ret != -ENOSYS)
+ goto err_pclk;
+
+ reset_assert(&priv->p30phy);
+ udelay(1);
+
+ /* Deassert PCIe PMA output clamp mode */
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
+ (0x1 << 15) | (0x1 << 31));
+
+ reset_deassert(&priv->p30phy);
+ udelay(1);
+
+ return 0;
+err_pclk:
+ clk_disable(&priv->ref_clk_n);
+err_ref:
+ clk_disable(&priv->ref_clk_m);
+
+ return ret;
+}
+
+static int rochchip_p3phy_exit(struct phy *phy)
+{
+ struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
+
+ clk_disable(&priv->ref_clk_m);
+ clk_disable(&priv->ref_clk_n);
+ clk_disable(&priv->pclk);
+ reset_assert(&priv->p30phy);
+
+ return 0;
+}
+
+static int rockchip_p3phy_probe(struct udevice *dev)
+{
+ struct rockchip_p3phy_priv *priv = dev_get_priv(dev);
+ struct udevice *syscon;
+ int ret;
+
+ priv->mmio = (void __iomem *)dev_read_addr(dev);
+ if ((fdt_addr_t)priv->mmio == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+ "rockchip,phy-grf", &syscon);
+ if (ret) {
+ pr_err("unable to find syscon device for rockchip,phy-grf\n");
+ return ret;
+ }
+
+ priv->phy_grf = syscon_get_regmap(syscon);
+ if (IS_ERR(priv->phy_grf)) {
+ dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
+ return PTR_ERR(priv->phy_grf);
+ }
+
+ ret = reset_get_by_name(dev, "phy", &priv->p30phy);
+ if (ret) {
+ dev_err(dev, "no phy reset control specified\n");
+ return ret;
+ }
+
+ ret = clk_get_by_name(dev, "refclk_m", &priv->ref_clk_m);
+ if (ret) {
+ dev_err(dev, "failed to find ref clock M\n");
+ return PTR_ERR(&priv->ref_clk_m);
+ }
+
+ ret = clk_get_by_name(dev, "refclk_n", &priv->ref_clk_n);
+ if (ret) {
+ dev_err(dev, "failed to find ref clock N\n");
+ return PTR_ERR(&priv->ref_clk_n);
+ }
+
+ ret = clk_get_by_name(dev, "pclk", &priv->pclk);
+ if (ret) {
+ dev_err(dev, "failed to find pclk\n");
+ return PTR_ERR(&priv->pclk);
+ }
+
+ return 0;
+}
+
+static struct phy_ops rochchip_p3phy_ops = {
+ .init = rochchip_p3phy_init,
+ .exit = rochchip_p3phy_exit,
+};
+
+static const struct udevice_id rockchip_p3phy_of_match[] = {
+ { .compatible = "rockchip,rk3568-pcie3-phy" },
+ { },
+};
+
+U_BOOT_DRIVER(rockchip_pcie3phy) = {
+ .name = "rockchip_pcie3phy",
+ .id = UCLASS_PHY,
+ .of_match = rockchip_p3phy_of_match,
+ .ops = &rochchip_p3phy_ops,
+ .probe = rockchip_p3phy_probe,
+ .priv_auto = sizeof(struct rockchip_p3phy_priv),
+};
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-17 07:37:51 +0000