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-rw-r--r--drivers/pinctrl/Kconfig8
-rw-r--r--drivers/pinctrl/Makefile2
-rw-r--r--drivers/pinctrl/pinctrl-adi-adsp.c161
-rw-r--r--drivers/pinctrl/pinctrl-at91.c52
-rw-r--r--drivers/pinctrl/tegra/pinctrl-tegra.c56
5 files changed, 272 insertions, 7 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 6ee7dc1cce8..687fb339ea0 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -178,6 +178,14 @@ config PINCTRL_APPLE
both the GPIO definitions and pin control functions for each
available multiplex function.
+config PINCTRL_ADI
+ bool "ADI pinctrl driver"
+ depends on DM && ARCH_SC5XX
+ help
+ This driver enables pinctrl support on SC5xx processors. This
+ driver covers only the pin configuration functionality, and
+ GPIO functionality is contained in the separate GPIO driver.
+
config PINCTRL_AR933X
bool "QCA/Athores ar933x pin control driver"
depends on DM && SOC_AR933X
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 634047a91f4..6deb6aaf6eb 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -3,6 +3,7 @@
obj-y += pinctrl-uclass.o
obj-$(CONFIG_$(XPL_)PINCTRL_GENERIC) += pinctrl-generic.o
+obj-$(CONFIG_PINCTRL_ADI) += pinctrl-adi-adsp.o
obj-$(CONFIG_PINCTRL_APPLE) += pinctrl-apple.o
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
@@ -15,7 +16,6 @@ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_PINCTRL_QCOM) += qcom/
obj-$(CONFIG_ARCH_RENESAS) += renesas/
-obj-$(CONFIG_ARCH_RZN1) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
obj-$(CONFIG_$(XPL_)PINCTRL_TEGRA) += tegra/
diff --git a/drivers/pinctrl/pinctrl-adi-adsp.c b/drivers/pinctrl/pinctrl-adi-adsp.c
new file mode 100644
index 00000000000..debf434212d
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-adi-adsp.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa <greg.malysa@timesys.com>
+ * Additional Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ *
+ * dm pinctrl implementation for ADI ADSP SoCs
+ *
+ */
+
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+#define ADSP_PORT_MMIO_SIZE 0x80
+#define ADSP_PORT_PIN_SIZE 16
+
+#define ADSP_PORT_PORT_MUX_BITS 2
+#define ADSP_PORT_PORT_MUX_MASK 0x03
+#define ADSP_PINCTRL_FUNCTION_COUNT 4
+
+#define ADSP_PORT_REG_FER 0x00
+#define ADSP_PORT_REG_FER_SET 0x04
+#define ADSP_PORT_REG_FER_CLEAR 0x08
+#define ADSP_PORT_REG_DATA 0x0c
+#define ADSP_PORT_REG_DATA_SET 0x10
+#define ADSP_PORT_REG_DATA_CLEAR 0x14
+#define ADSP_PORT_REG_DIR 0x18
+#define ADSP_PORT_REG_DIR_SET 0x1c
+#define ADSP_PORT_REG_DIR_CLEAR 0x20
+#define ADSP_PORT_REG_INEN 0x24
+#define ADSP_PORT_REG_INEN_SET 0x28
+#define ADSP_PORT_REG_INEN_CLEAR 0x2c
+#define ADSP_PORT_REG_PORT_MUX 0x30
+#define ADSP_PORT_REG_DATA_TGL 0x34
+#define ADSP_PORT_REG_POLAR 0x38
+#define ADSP_PORT_REG_POLAR_SET 0x3c
+#define ADSP_PORT_REG_POLAR_CLEAR 0x40
+#define ADSP_PORT_REG_LOCK 0x44
+#define ADSP_PORT_REG_TRIG_TGL 0x48
+
+struct adsp_pinctrl_priv {
+ void __iomem *base;
+ int npins;
+ char pinbuf[16];
+};
+
+static u32 get_port(unsigned int pin)
+{
+ return pin / ADSP_PORT_PIN_SIZE;
+}
+
+static u32 get_offset(unsigned int pin)
+{
+ return pin % ADSP_PORT_PIN_SIZE;
+}
+
+static int adsp_pinctrl_pinmux_set(struct udevice *udev, unsigned int pin, unsigned int func)
+{
+ struct adsp_pinctrl_priv *priv = dev_get_priv(udev);
+ void __iomem *portbase;
+ u32 port, offset;
+ u32 val;
+
+ if (pin >= priv->npins)
+ return -ENODEV;
+
+ if (func >= ADSP_PINCTRL_FUNCTION_COUNT)
+ return -EINVAL;
+
+ port = get_port(pin);
+ offset = get_offset(pin);
+ portbase = priv->base + port * ADSP_PORT_MMIO_SIZE;
+
+ val = ioread32(portbase + ADSP_PORT_REG_PORT_MUX);
+ val &= ~(ADSP_PORT_PORT_MUX_MASK << (ADSP_PORT_PORT_MUX_BITS * offset));
+ val |= func << (ADSP_PORT_PORT_MUX_BITS * offset);
+ iowrite32(val, portbase + ADSP_PORT_REG_PORT_MUX);
+
+ iowrite32(BIT(offset), portbase + ADSP_PORT_REG_FER_SET);
+ return 0;
+}
+
+static int adsp_pinctrl_set_state(struct udevice *udev, struct udevice *config)
+{
+ const struct fdt_property *pinlist;
+ int length = 0;
+ int ret, i;
+ u32 pin, function;
+
+ pinlist = dev_read_prop(config, "adi,pins", &length);
+ if (!pinlist) {
+ dev_err(udev, "missing adi,pins property in pinctrl config node\n");
+ return -EINVAL;
+ }
+
+ if (length % (sizeof(uint32_t) * 2)) {
+ dev_err(udev, "adi,pins property must be a multiple of two uint32_ts\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < length / sizeof(uint32_t); i += 2) {
+ ret = dev_read_u32_index(config, "adi,pins", i, &pin);
+ if (ret)
+ return ret;
+
+ ret = dev_read_u32_index(config, "adi,pins", i + 1, &function);
+ if (ret)
+ return ret;
+
+ ret = adsp_pinctrl_pinmux_set(udev, pin, function);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+const struct pinctrl_ops adsp_pinctrl_ops = {
+ .set_state = adsp_pinctrl_set_state,
+};
+
+static int adsp_pinctrl_probe(struct udevice *udev)
+{
+ struct adsp_pinctrl_priv *priv = dev_get_priv(udev);
+
+ priv->base = dev_read_addr_ptr(udev);
+ priv->npins = dev_read_u32_default(udev, "adi,npins", 0);
+
+ if (!priv->base) {
+ dev_err(udev, "Missing or invalid pinctrl base address\n");
+ return -ENOENT;
+ }
+
+ if (!priv->npins) {
+ dev_err(udev, "Missing adi,npins property!\n");
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id adsp_pinctrl_match[] = {
+ { .compatible = "adi,adsp-pinctrl" },
+ { },
+};
+
+U_BOOT_DRIVER(adi_adsp_pinctrl) = {
+ .name = "adi_adsp_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = adsp_pinctrl_match,
+ .probe = adsp_pinctrl_probe,
+ .priv_auto = sizeof(struct adsp_pinctrl_priv),
+ .ops = &adsp_pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 5038cb535e3..2938635ed95 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -9,6 +9,8 @@
#include <dm.h>
#include <log.h>
#include <asm/global_data.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
#include <dm/pinctrl.h>
#include <asm/hardware.h>
#include <linux/bitops.h>
@@ -492,21 +494,58 @@ const struct pinctrl_ops at91_pinctrl_ops = {
.set_state = at91_pinctrl_set_state,
};
+/**
+ * at91_pinctrl_bind() - Iterates through all subnodes of the pinctrl device
+ * in the DT and binds them to U-Boot's device model. Each subnode
+ * typically represents a GPIO controller or pin configuration data.
+ *
+ * @dev: Pointer to the pinctrl device
+ *
+ * Returns 0 on success or negative error on failure
+ */
+static int at91_pinctrl_bind(struct udevice *dev)
+{
+ ofnode gpio_node;
+ struct udevice *gpio;
+ int ret;
+
+ ofnode_for_each_subnode(gpio_node, dev_ofnode(dev)) {
+ ret = lists_bind_fdt(dev, gpio_node, &gpio, NULL, false);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int at91_pinctrl_probe(struct udevice *dev)
{
struct at91_pinctrl_priv *priv = dev_get_priv(dev);
fdt_addr_t addr_base;
+ struct udevice *gpio_node;
int index;
- for (index = 0; index < MAX_GPIO_BANKS; index++) {
- addr_base = devfdt_get_addr_index(dev, index);
- if (addr_base == FDT_ADDR_T_NONE)
- break;
+ if (list_empty(&dev->child_head)) {
+ for (index = 0; index < MAX_GPIO_BANKS; index++) {
+ addr_base = devfdt_get_addr_index(dev, index);
+ if (addr_base == FDT_ADDR_T_NONE)
+ break;
- priv->reg_base[index] = (struct at91_port *)addr_base;
+ priv->reg_base[index] = (struct at91_port *)addr_base;
+ }
+ } else {
+ index = 0;
+ list_for_each_entry(gpio_node, &dev->child_head, sibling_node) {
+ addr_base = dev_read_addr(gpio_node);
+ if (addr_base == FDT_ADDR_T_NONE)
+ break;
+
+ priv->reg_base[index] = (struct at91_port *)addr_base;
+ index++;
+ }
}
- priv->nbanks = index;
+ priv->nbanks = index < MAX_GPIO_BANKS ? index : MAX_GPIO_BANKS;
return 0;
}
@@ -524,6 +563,7 @@ U_BOOT_DRIVER(atmel_sama5d3_pinctrl) = {
.id = UCLASS_PINCTRL,
.of_match = at91_pinctrl_match,
.probe = at91_pinctrl_probe,
+ .bind = at91_pinctrl_bind,
.priv_auto = sizeof(struct at91_pinctrl_priv),
.ops = &at91_pinctrl_ops,
};
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index ad7112a05e6..e6b957f5537 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -67,6 +67,58 @@ exit:
kfree(drive_group);
}
+#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
+static void tegra_pinctrl_set_mipipad(struct udevice *config, int padcnt)
+{
+ struct pmux_mipipadctrlgrp_config *mipipad_group;
+ int i, ret, pad_id;
+ const char *function;
+ const char **pads;
+
+ mipipad_group = kmalloc_array(padcnt, sizeof(*mipipad_group), GFP_KERNEL);
+ if (!mipipad_group) {
+ log_debug("%s: cannot allocate mipi pad group array\n", __func__);
+ return;
+ }
+
+ /* decode function id and fill the first copy of pmux_mipipadctrlgrp_config */
+ function = dev_read_string(config, "nvidia,function");
+ if (function)
+ for (i = 0; i < PMUX_FUNC_COUNT; i++)
+ if (tegra_pinctrl_to_func[i])
+ if (!strcmp(function, tegra_pinctrl_to_func[i]))
+ break;
+
+ mipipad_group[0].func = i;
+
+ for (i = 1; i < padcnt; i++)
+ memcpy(&mipipad_group[i], &mipipad_group[0], sizeof(mipipad_group[0]));
+
+ ret = dev_read_string_list(config, "nvidia,pins", &pads);
+ if (ret < 0) {
+ log_debug("%s: could not parse property nvidia,pins\n", __func__);
+ goto exit;
+ }
+
+ for (i = 0; i < padcnt; i++) {
+ for (pad_id = 0; pad_id < PMUX_MIPIPADCTRLGRP_COUNT; pad_id++)
+ if (tegra_pinctrl_to_mipipadgrp[pad_id])
+ if (!strcmp(pads[i], tegra_pinctrl_to_mipipadgrp[pad_id])) {
+ mipipad_group[i].grp = pad_id;
+ break;
+ }
+ }
+
+ pinmux_config_mipipadctrlgrp_table(mipipad_group, padcnt);
+
+ free(pads);
+exit:
+ kfree(mipipad_group);
+}
+#else
+static void tegra_pinctrl_set_mipipad(struct udevice *config, int padcnt) { }
+#endif
+
static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt)
{
struct pmux_pingrp_config *pinmux_group;
@@ -170,6 +222,9 @@ static int tegra_pinctrl_set_state(struct udevice *dev, struct udevice *config)
if (!strncmp(name, "drive_", 6))
/* Drive node is detected */
tegra_pinctrl_set_drive(child, ret);
+ else if (!strncmp(name, "mipi_pad_ctrl_", 14))
+ /* Handle T124 specific pinconfig */
+ tegra_pinctrl_set_mipipad(child, ret);
else
/* Pin node is detected */
tegra_pinctrl_set_pin(child, ret);
@@ -236,6 +291,7 @@ static int tegra_pinctrl_bind(struct udevice *dev)
static const struct udevice_id tegra_pinctrl_ids[] = {
{ .compatible = "nvidia,tegra30-pinmux" },
{ .compatible = "nvidia,tegra114-pinmux" },
+ { .compatible = "nvidia,tegra124-pinmux" },
{ },
};